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//=======================================================================
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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// fm_hvc_core.v
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//
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// Abstract:
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// HV counter core
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//
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// Author:
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// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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module fm_hvc_core (
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clk_vi,
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rst_x,
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// configuration registers
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i_video_start,
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// control out (only for internal use)
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o_vsync_i,
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o_hsync_i,
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// video out timing
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o_active,
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o_first_line,
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// video out
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o_r,
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o_g,
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o_b,
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o_vsync_x,
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o_hsync_x,
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o_blank_x,
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o_de
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);
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//////////////////////////////////
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// I/O port definition
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//////////////////////////////////
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input clk_vi; // 25MHz
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input rst_x;
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// configuration registers
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input i_video_start;
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// control out (only for internal use)
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output o_vsync_i;
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output o_hsync_i;
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// video out timing
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output o_active;
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output o_first_line;
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output [7:0] o_r;
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output [7:0] o_g;
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output [7:0] o_b;
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output o_vsync_x;
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output o_hsync_x;
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output o_blank_x;
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output o_de;
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//////////////////////////////////
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// reg
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//////////////////////////////////
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reg [9:0] r_hcnt;
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reg [9:0] r_vcnt;
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reg r_vsync_x;
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reg r_hsync_x;
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reg r_hsync_x_i; // internal use, vactive only
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reg r_blank_x;
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reg r_vsync_neg;
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reg r_hsync_neg;
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reg r_de;
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//////////////////////////////////
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// wire
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//////////////////////////////////
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wire w_h_end;
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wire w_v_end;
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wire w_vsync;
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wire w_hsync;
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wire w_hsync_dma;
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wire w_hactive;
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wire w_vactive_first; // for aa
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wire w_vactive;
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wire w_active;
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wire w_active_first; // for aa
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// color bar
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wire w_r_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) |
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((r_hcnt >= 252) & (r_hcnt <= 343)) |
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((r_hcnt >= 527) & (r_hcnt <= 617)) |
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((r_hcnt >= 618) & (r_hcnt <= 708));
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wire w_g_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) |
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((r_hcnt >= 252) & (r_hcnt <= 343)) |
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((r_hcnt >= 344) & (r_hcnt <= 435)) |
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((r_hcnt >= 436) & (r_hcnt <= 526));
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wire w_b_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) |
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((r_hcnt >= 344) & (r_hcnt <= 435)) |
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((r_hcnt >= 527) & (r_hcnt <= 617)) |
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((r_hcnt >= 709) & (r_hcnt <= 799));
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wire [7:0] w_r_test = {8{w_r_test_en}};
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wire [7:0] w_g_test = {8{w_g_test_en}};
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wire [7:0] w_b_test = {8{w_b_test_en}};
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wire w_hsync_x_i;
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//////////////////////////////////
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// assign
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//////////////////////////////////
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// VGA : 60Hz
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assign w_h_end = (r_hcnt == 'd799); // 800 clock
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assign w_v_end = w_h_end & (r_vcnt == 'd524); // 525 line
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assign w_vsync = ((r_vcnt == 10'd10) | (r_vcnt == 10'd11)) ? 1'b0 : 1'b1;
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assign w_hsync = ((r_hcnt >= 10'd16)&(r_hcnt <= 10'd111)) ? 1'b0 : 1'b1;
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assign w_hsync_dma = ((r_hcnt >= 10'd16)&(r_hcnt <= 10'd39)) ? 1'b0 : 1'b1;
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assign w_hactive = ((r_hcnt >= 10'd160)&(r_hcnt <= 10'd799)) ? 1'b1 : 1'b0;
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assign w_vactive = ((r_vcnt >= 10'd45)&(r_vcnt <= 10'd524)) ? 1'b1 : 1'b0;
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assign w_vactive_first = (r_vcnt == 10'd45);
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assign w_active = w_hactive & w_vactive;
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assign w_active_first = w_vactive_first;
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assign w_hsync_x_i = w_vactive & w_hsync_dma;
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// color should be black in blanking
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//assign w_r = (w_active) ? w_rgb[7:0] : 8'h00;
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//assign w_g = (w_active) ? w_rgb[15:8] : 8'h00;
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//assign w_b = (w_active) ? w_rgb[23:16] : 8'h00;
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assign o_vsync_x = r_vsync_x;//r_vsync_neg;
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assign o_hsync_x = r_hsync_x;//r_hsync_neg;
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assign o_blank_x = r_blank_x;
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assign o_de = r_de;
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assign o_r = (w_active) ? w_r_test : 8'h00;
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assign o_g = (w_active) ? w_g_test : 8'h00;
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assign o_b = (w_active) ? w_b_test : 8'h00;
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assign o_vsync_i = r_vsync_x;
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assign o_hsync_i = r_hsync_x_i;
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assign o_active = w_active;
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assign o_first_line = w_active_first;
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//////////////////////////////////
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// always
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//////////////////////////////////
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// H counter
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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r_hcnt <= 11'b0;
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end else begin
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if (w_h_end) r_hcnt <= 11'b0;
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else r_hcnt <= r_hcnt + 1'b1;
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end
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end
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// V counter
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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// r_vcnt <= 10'd0;
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// r_vcnt <= 10'd36; // this is only for faster simulatin
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r_vcnt <= 10'd9; // this is only for faster simulatin (v rise)
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end else begin
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if (w_v_end) r_vcnt <= 10'd0;
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else if (w_h_end) r_vcnt <= r_vcnt + 1'b1;
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end
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end
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// sync
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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r_vsync_x <= 1'b1;
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r_hsync_x <= 1'b1;
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r_blank_x <= 1'b1;
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r_de <= 1'b0;
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end else begin
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r_vsync_x <= w_vsync;
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r_hsync_x <= w_hsync;
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r_hsync_x_i <= w_hsync_x_i;
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r_blank_x <= w_active;
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r_de <= w_active;
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end
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end
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// neg-edge registers for output timing adjustment
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always @(negedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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r_vsync_neg <= 1'b1;
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r_hsync_neg <= 1'b1;
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end else begin
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r_vsync_neg <= r_vsync_x;
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r_hsync_neg <= r_hsync_x;
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end
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end
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endmodule
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