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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 08:16:54 July 05, 2013
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# usbhost_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE EP3C16U484C6
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set_global_assignment -name TOP_LEVEL_ENTITY d3d_top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:16:54 JULY 05, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_location_assignment PIN_G21 -to CLK
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set_location_assignment PIN_B1 -to LEDG[9]
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set_location_assignment PIN_B2 -to LEDG[8]
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set_location_assignment PIN_C2 -to LEDG[7]
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set_location_assignment PIN_C1 -to LEDG[6]
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set_location_assignment PIN_E1 -to LEDG[5]
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set_location_assignment PIN_F2 -to LEDG[4]
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set_location_assignment PIN_H1 -to LEDG[3]
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set_location_assignment PIN_J3 -to LEDG[2]
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set_location_assignment PIN_J2 -to LEDG[1]
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set_location_assignment PIN_J1 -to LEDG[0]
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set_location_assignment PIN_E4 -to SW[8]
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set_location_assignment PIN_E3 -to SW[7]
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set_location_assignment PIN_H7 -to SW[6]
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set_location_assignment PIN_J7 -to SW[5]
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set_location_assignment PIN_G5 -to SW[4]
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set_location_assignment PIN_G4 -to SW[3]
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set_location_assignment PIN_H6 -to SW[2]
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set_location_assignment PIN_H5 -to SW[1]
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set_location_assignment PIN_J6 -to SW[0]
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set_location_assignment PIN_F1 -to nBUTTON[2]
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set_location_assignment PIN_G3 -to nBUTTON[1]
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#set_location_assignment PIN_H2 -to nBUTTON[0]
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set_location_assignment PIN_H2 -to RST
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set_location_assignment PIN_U22 -to UART_RXD
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set_location_assignment PIN_U21 -to UART_TXD
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set_location_assignment PIN_V22 -to UART_RTS
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set_location_assignment PIN_V21 -to UART_CTS
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set_location_assignment PIN_J21 -to VGA_G[3]
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set_location_assignment PIN_K17 -to VGA_G[2]
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set_location_assignment PIN_J17 -to VGA_G[1]
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set_location_assignment PIN_H22 -to VGA_G[0]
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set_location_assignment PIN_L21 -to VGA_HS
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set_location_assignment PIN_L22 -to VGA_VS
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set_location_assignment PIN_H21 -to VGA_R[3]
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set_location_assignment PIN_H20 -to VGA_R[2]
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set_location_assignment PIN_H17 -to VGA_R[1]
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set_location_assignment PIN_H19 -to VGA_R[0]
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set_location_assignment PIN_K18 -to VGA_B[3]
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set_location_assignment PIN_J22 -to VGA_B[2]
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set_location_assignment PIN_K21 -to VGA_B[1]
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set_location_assignment PIN_K22 -to VGA_B[0]
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set_location_assignment PIN_E11 -to nHEX0[0]
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set_location_assignment PIN_F11 -to nHEX0[1]
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set_location_assignment PIN_H12 -to nHEX0[2]
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set_location_assignment PIN_H13 -to nHEX0[3]
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set_location_assignment PIN_G12 -to nHEX0[4]
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set_location_assignment PIN_F12 -to nHEX0[5]
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set_location_assignment PIN_F13 -to nHEX0[6]
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set_location_assignment PIN_D13 -to nHEX0[7]
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set_location_assignment PIN_A15 -to nHEX1[6]
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set_location_assignment PIN_E14 -to nHEX1[5]
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set_location_assignment PIN_B14 -to nHEX1[4]
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set_location_assignment PIN_A14 -to nHEX1[3]
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set_location_assignment PIN_C13 -to nHEX1[2]
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set_location_assignment PIN_B13 -to nHEX1[1]
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set_location_assignment PIN_A13 -to nHEX1[0]
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| 110 |
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set_location_assignment PIN_B15 -to nHEX1[7]
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set_location_assignment PIN_F14 -to nHEX2[6]
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set_location_assignment PIN_B17 -to nHEX2[5]
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set_location_assignment PIN_A17 -to nHEX2[4]
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set_location_assignment PIN_E15 -to nHEX2[3]
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set_location_assignment PIN_B16 -to nHEX2[2]
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set_location_assignment PIN_A16 -to nHEX2[1]
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set_location_assignment PIN_D15 -to nHEX2[0]
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set_location_assignment PIN_A18 -to nHEX2[7]
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set_location_assignment PIN_G15 -to nHEX3[6]
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set_location_assignment PIN_D19 -to nHEX3[5]
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set_location_assignment PIN_C19 -to nHEX3[4]
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set_location_assignment PIN_B19 -to nHEX3[3]
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set_location_assignment PIN_A19 -to nHEX3[2]
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set_location_assignment PIN_F15 -to nHEX3[1]
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set_location_assignment PIN_B18 -to nHEX3[0]
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set_location_assignment PIN_G16 -to nHEX3[7]
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set_location_assignment PIN_G8 -to DRAM_CAS_N
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| 128 |
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set_location_assignment PIN_G7 -to DRAM_CS_N
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set_location_assignment PIN_E5 -to DRAM_CLK
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set_location_assignment PIN_E6 -to DRAM_CKE
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set_location_assignment PIN_B5 -to DRAM_BA[0]
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set_location_assignment PIN_A4 -to DRAM_BA[1]
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set_location_assignment PIN_F10 -to DRAM_DQ[15]
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set_location_assignment PIN_E10 -to DRAM_DQ[14]
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set_location_assignment PIN_A10 -to DRAM_DQ[13]
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set_location_assignment PIN_B10 -to DRAM_DQ[12]
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set_location_assignment PIN_C10 -to DRAM_DQ[11]
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set_location_assignment PIN_A9 -to DRAM_DQ[10]
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set_location_assignment PIN_B9 -to DRAM_DQ[9]
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| 140 |
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set_location_assignment PIN_A8 -to DRAM_DQ[8]
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set_location_assignment PIN_F8 -to DRAM_DQ[7]
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set_location_assignment PIN_H9 -to DRAM_DQ[6]
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set_location_assignment PIN_G9 -to DRAM_DQ[5]
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set_location_assignment PIN_F9 -to DRAM_DQ[4]
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set_location_assignment PIN_E9 -to DRAM_DQ[3]
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| 146 |
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set_location_assignment PIN_H10 -to DRAM_DQ[2]
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| 147 |
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set_location_assignment PIN_G10 -to DRAM_DQ[1]
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set_location_assignment PIN_D10 -to DRAM_DQ[0]
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set_location_assignment PIN_E7 -to DRAM_DQM[0]
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| 150 |
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set_location_assignment PIN_B8 -to DRAM_DQM[1]
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set_location_assignment PIN_F7 -to DRAM_RAS_N
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set_location_assignment PIN_D6 -to DRAM_WE_N
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| 153 |
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set_location_assignment PIN_C8 -to DRAM_ADDR[12]
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| 154 |
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set_location_assignment PIN_A7 -to DRAM_ADDR[11]
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| 155 |
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set_location_assignment PIN_B4 -to DRAM_ADDR[10]
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| 156 |
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set_location_assignment PIN_B7 -to DRAM_ADDR[9]
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| 157 |
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set_location_assignment PIN_C7 -to DRAM_ADDR[8]
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| 158 |
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set_location_assignment PIN_A6 -to DRAM_ADDR[7]
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| 159 |
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set_location_assignment PIN_B6 -to DRAM_ADDR[6]
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| 160 |
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set_location_assignment PIN_C6 -to DRAM_ADDR[5]
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| 161 |
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set_location_assignment PIN_A5 -to DRAM_ADDR[4]
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| 162 |
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set_location_assignment PIN_C3 -to DRAM_ADDR[3]
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| 163 |
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set_location_assignment PIN_B3 -to DRAM_ADDR[2]
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| 164 |
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set_location_assignment PIN_A3 -to DRAM_ADDR[1]
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| 165 |
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set_location_assignment PIN_C4 -to DRAM_ADDR[0]
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| 166 |
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| 167 |
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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| 168 |
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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| 169 |
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set_location_assignment PIN_U8 -to USB_DP
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| 170 |
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set_location_assignment PIN_Y7 -to USB_DN
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| 171 |
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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| 172 |
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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| 173 |
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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| 174 |
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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| 175 |
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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| 176 |
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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| 177 |
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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| 178 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK
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| 179 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RST
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| 180 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
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| 181 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
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| 182 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
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| 183 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_DN
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| 184 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
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| 185 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
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| 186 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
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| 187 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
|
| 188 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
|
| 189 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
|
| 190 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
|
| 191 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
|
| 192 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
|
| 193 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
|
| 194 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
|
| 195 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
| 196 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
| 197 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
| 198 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
|
| 199 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
|
| 200 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
|
| 201 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
|
| 202 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
|
| 203 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
|
| 204 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
|
| 205 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
|
| 206 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
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| 207 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
|
| 208 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
|
| 209 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
|
| 210 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
|
| 211 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
|
| 212 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
|
| 213 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
|
| 214 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
|
| 215 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
|
| 216 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
|
| 217 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
|
| 218 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
|
| 219 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_DP
|
| 220 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
|
| 221 |
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
|
| 222 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
|
| 223 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
|
| 224 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
|
| 225 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
|
| 226 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
|
| 227 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
|
| 228 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
|
| 229 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
|
| 230 |
|
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
|
| 231 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
|
| 232 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
|
| 233 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
|
| 234 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
|
| 235 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
|
| 236 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
|
| 237 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
|
| 238 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
|
| 239 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
|
| 240 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
|
| 241 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
|
| 242 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
|
| 243 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
|
| 244 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
|
| 245 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
|
| 246 |
|
|
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
| 247 |
|
|
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
| 248 |
|
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
| 249 |
|
|
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
|
| 250 |
|
|
set_location_assignment PIN_K1 -to DATA
|
| 251 |
|
|
set_location_assignment PIN_K2 -to DCLK
|
| 252 |
|
|
set_location_assignment PIN_E2 -to SCE
|
| 253 |
|
|
set_location_assignment PIN_D1 -to SDO
|
| 254 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DATA
|
| 255 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DCLK
|
| 256 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SCE
|
| 257 |
|
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDO
|
| 258 |
|
|
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
| 259 |
|
|
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
| 260 |
|
|
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
| 261 |
|
|
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
| 262 |
|
|
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
|
| 263 |
|
|
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
| 264 |
|
|
set_global_assignment -name SEARCH_PATH ../../../../rtl/include
|
| 265 |
|
|
|
| 266 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_tri.v
|
| 267 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_f22_to_i.v
|
| 268 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_clip.v
|
| 269 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_cull.v
|
| 270 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_norm.v
|
| 271 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_fcnv.v
|
| 272 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_frcp_rom.v
|
| 273 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_frcp.v
|
| 274 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_fmul.v
|
| 275 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_fadd.v
|
| 276 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_sys.v
|
| 277 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_viewport.v
|
| 278 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras_state.v
|
| 279 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras_mem.v
|
| 280 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras_line.v
|
| 281 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras.v
|
| 282 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_persdiv.v
|
| 283 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_mem_arb.v
|
| 284 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_matrix.v
|
| 285 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_mem.v
|
| 286 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo.v
|
| 287 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_core.v
|
| 288 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_cmn_ram.v
|
| 289 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc_dma.v
|
| 290 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc_data.v
|
| 291 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc_core.v
|
| 292 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc.v
|
| 293 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_afifo.v
|
| 294 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/fm_hsys.v
|
| 295 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/fm_avalon.v
|
| 296 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/fm_avalon_wb.v
|
| 297 |
|
|
set_global_assignment -name QSYS_FILE d3d_system.qsys
|
| 298 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/d3d_top.v
|
| 299 |
|
|
set_global_assignment -name SIGNALTAP_FILE output_files/stp4.stp
|
| 300 |
|
|
set_global_assignment -name SDC_FILE d3d.sdc
|
| 301 |
|
|
set_global_assignment -name SIGNALTAP_FILE stp1.stp
|
| 302 |
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
