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# TCL File Generated by Component Editor 13.0sp1
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# Tue Sep 09 10:30:48 JST 2014
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# DO NOT MODIFY
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#
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# fm_3d_wrapprt "3D Core Wrapper" v1.0
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# 2014.09.09.10:30:48
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#
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module fm_3d_wrapprt
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME fm_3d_wrapprt
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP MyLib
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME "3D Core Wrapper"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL fm_3d_wrapper
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file fm_3d_wrapper.v VERILOG PATH ../../../rtl/de0/fm_3d_wrapper.v TOP_LEVEL_FILE
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file fm_3d_core.v VERILOG PATH ../../../../rtl/core/fm_3d_core.v
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add_fileset_file fm_3d_f22_to_ui.v VERILOG PATH ../../../../rtl/core/fm_3d_f22_to_i.v
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add_fileset_file fm_3d_fadd.v VERILOG PATH ../../../../rtl/core/fm_3d_fadd.v
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add_fileset_file fm_3d_fcnv.v VERILOG PATH ../../../../rtl/core/fm_3d_fcnv.v
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add_fileset_file fm_3d_fmul.v VERILOG PATH ../../../../rtl/core/fm_3d_fmul.v
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add_fileset_file fm_3d_frcp.v VERILOG PATH ../../../../rtl/core/fm_3d_frcp.v
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add_fileset_file fm_3d_frcp_rom.v VERILOG PATH ../../../../rtl/core/fm_3d_frcp_rom.v
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add_fileset_file fm_3d_norm.v VERILOG PATH ../../../../rtl/core/fm_3d_norm.v
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add_fileset_file fm_sys.v VERILOG PATH ../../../../rtl/core/fm_sys.v
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add_fileset_file fm_geo.v VERILOG PATH ../../../../rtl/core/fm_geo.v
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add_fileset_file fm_geo_mem.v VERILOG PATH ../../../../rtl/core/fm_geo_mem.v
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add_fileset_file fm_geo_matrix.v VERILOG PATH ../../../../rtl/core/fm_geo_matrix.v
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add_fileset_file fm_mem_arb.v VERILOG PATH ../../../../rtl/core/fm_mem_arb.v
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add_fileset_file fm_geo_persdiv.v VERILOG PATH ../../../../rtl/core/fm_geo_persdiv.v
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add_fileset_file fm_ras.v VERILOG PATH ../../../../rtl/core/fm_ras.v
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add_fileset_file fm_geo_tri.v VERILOG PATH ../../../../rtl/core/fm_geo_tri.v
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add_fileset_file fm_ras_line.v VERILOG PATH ../../../../rtl/core/fm_ras_line.v
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add_fileset_file fm_ras_mem.v VERILOG PATH ../../../../rtl/core/fm_ras_mem.v
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add_fileset_file fm_ras_state.v VERILOG PATH ../../../../rtl/core/fm_ras_state.v
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add_fileset_file fm_geo_viewport.v VERILOG PATH ../../../../rtl/core/fm_geo_viewport.v
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add_fileset_file fm_avalon_wb.v VERILOG PATH ../../../rtl/de0/fm_avalon_wb.v
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add_fileset_file fm_3d_wrapper.v VERILOG PATH ../../../rtl/de0/fm_3d_wrapper.v
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk_core clk Input 1
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#
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# connection point interrupt_sender
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#
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint avalon_slave
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set_interface_property interrupt_sender associatedClock clock_sink
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set_interface_property interrupt_sender associatedReset reset_sink
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set_interface_property interrupt_sender ENABLED true
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set_interface_property interrupt_sender EXPORT_OF ""
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set_interface_property interrupt_sender PORT_NAME_MAP ""
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set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_sender o_int irq Output 1
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#
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# connection point avalon_slave
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#
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add_interface avalon_slave avalon end
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set_interface_property avalon_slave addressUnits WORDS
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set_interface_property avalon_slave associatedClock clock_sink
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set_interface_property avalon_slave associatedReset reset_sink
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set_interface_property avalon_slave bitsPerSymbol 8
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set_interface_property avalon_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave burstcountUnits WORDS
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set_interface_property avalon_slave explicitAddressSpan 0
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set_interface_property avalon_slave holdTime 0
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set_interface_property avalon_slave linewrapBursts false
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set_interface_property avalon_slave maximumPendingReadTransactions 0
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set_interface_property avalon_slave readLatency 0
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set_interface_property avalon_slave readWaitTime 1
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set_interface_property avalon_slave setupTime 0
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set_interface_property avalon_slave timingUnits Cycles
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set_interface_property avalon_slave writeWaitTime 0
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set_interface_property avalon_slave ENABLED true
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set_interface_property avalon_slave EXPORT_OF ""
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set_interface_property avalon_slave PORT_NAME_MAP ""
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set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave i_avs_adr address Input 6
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add_interface_port avalon_slave i_avs_be byteenable Input 4
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add_interface_port avalon_slave i_avs_r read Input 1
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add_interface_port avalon_slave o_avs_rd readdata Output 32
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add_interface_port avalon_slave i_avs_w write Input 1
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add_interface_port avalon_slave i_avs_wd writedata Input 32
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add_interface_port avalon_slave o_avs_wait waitrequest Output 1
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set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point avalon_master
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#
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add_interface avalon_master avalon start
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set_interface_property avalon_master addressUnits SYMBOLS
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set_interface_property avalon_master associatedClock clock_sink
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set_interface_property avalon_master associatedReset reset_sink
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set_interface_property avalon_master bitsPerSymbol 8
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set_interface_property avalon_master burstOnBurstBoundariesOnly false
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set_interface_property avalon_master burstcountUnits WORDS
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set_interface_property avalon_master doStreamReads false
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set_interface_property avalon_master doStreamWrites false
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set_interface_property avalon_master holdTime 0
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set_interface_property avalon_master linewrapBursts false
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set_interface_property avalon_master maximumPendingReadTransactions 0
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set_interface_property avalon_master readLatency 0
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set_interface_property avalon_master readWaitTime 1
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set_interface_property avalon_master setupTime 0
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set_interface_property avalon_master timingUnits Cycles
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set_interface_property avalon_master writeWaitTime 0
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set_interface_property avalon_master ENABLED true
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set_interface_property avalon_master EXPORT_OF ""
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set_interface_property avalon_master PORT_NAME_MAP ""
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set_interface_property avalon_master SVD_ADDRESS_GROUP ""
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add_interface_port avalon_master o_avm_adr address Output 26
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add_interface_port avalon_master o_avm_be byteenable Output 4
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add_interface_port avalon_master o_avm_wd writedata Output 32
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add_interface_port avalon_master o_avm_blen burstcount Output 3
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add_interface_port avalon_master o_avm_r read Output 1
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add_interface_port avalon_master o_avm_w write Output 1
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add_interface_port avalon_master i_avm_wait waitrequest Input 1
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add_interface_port avalon_master i_avm_rd readdata Input 32
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add_interface_port avalon_master i_avm_rvalid readdatavalid Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_x reset_n Input 1
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