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Subversion Repositories wf3d

[/] [wf3d/] [trunk/] [implement/] [synth/] [zedboard/] [implement.tcl] - Blame information for rev 5

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Line No. Rev Author Line
1 5 specular
set PROJ_NAME polyphony
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set PROJ_DIR .
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set TOP_NAME zed_base_wrapper
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set BD_IP_DIR ./${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip
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create_project -in_memory -part xc7z020clg484-1
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set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
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set_property design_mode GateLvl [current_fileset]
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set_property parent.project_path ${PROJ_DIR}/${PROJ_NAME}.xpr [current_project]
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set_property ip_repo_paths ${PROJ_DIR}/${PROJ_NAME}.cache/ip [current_project]
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set_property ip_output_repo ${PROJ_DIR}/${PROJ_NAME}.cache/ip [current_project]
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add_files -quiet ${TOP_NAME}.dcp
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# very important
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read_xdc -prop_thru_buffers -ref zed_base_axi_gpio_0_0 -cells U0 ${BD_IP_DIR}/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_board.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_board.xdc]
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read_xdc -ref zed_base_axi_gpio_0_0 -cells U0 ${BD_IP_DIR}/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0.xdc]
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read_xdc -prop_thru_buffers -ref zed_base_axi_gpio_1_0 -cells U0 ${BD_IP_DIR}/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_board.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_board.xdc]
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read_xdc -ref zed_base_axi_gpio_1_0 -cells U0 ${BD_IP_DIR}/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0.xdc]
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read_xdc -prop_thru_buffers -ref zed_base_axi_gpio_2_0 -cells U0 ${BD_IP_DIR}/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_board.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_board.xdc]
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read_xdc -ref zed_base_axi_gpio_2_0 -cells U0 ${BD_IP_DIR}/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0.xdc]
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read_xdc -ref zed_base_processing_system7_0_0 -cells inst ${BD_IP_DIR}/zed_base_processing_system7_0_0/zed_base_processing_system7_0_0.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_processing_system7_0_0/zed_base_processing_system7_0_0.xdc]
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read_xdc -prop_thru_buffers -ref zed_base_rst_processing_system7_0_50M_0 ${BD_IP_DIR}/zed_base_rst_processing_system7_0_50M_0/zed_base_rst_processing_system7_0_50M_0_board.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_rst_processing_system7_0_50M_0/zed_base_rst_processing_system7_0_50M_0_board.xdc]
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read_xdc -ref zed_base_rst_processing_system7_0_50M_0 ${BD_IP_DIR}/zed_base_rst_processing_system7_0_50M_0/zed_base_rst_processing_system7_0_50M_0.xdc
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set_property processing_order EARLY [get_files ${BD_IP_DIR}/zed_base_rst_processing_system7_0_50M_0/zed_base_rst_processing_system7_0_50M_0.xdc]
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read_xdc user_const.xdc
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# Link
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link_design -top ${TOP_NAME} -part xc7z020clg484-1
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# Opt
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opt_design
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write_checkpoint -force ${TOP_NAME}_opt.dcp
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report_drc -file ${TOP_NAME}_drc_opted.rpt
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write_hwdef -force -file ${TOP_NAME}.hwdef
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# Place
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place_design
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write_checkpoint -force ${TOP_NAME}_placed.dcp
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report_io -file ${TOP_NAME}_io_placed.rpt
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report_utilization -file ${TOP_NAME}_utilization_placed.rpt -pb ${TOP_NAME}_utilization_placed.pb
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report_control_sets -verbose -file ${TOP_NAME}_control_sets_placed.rpt
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# Route
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route_design
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write_checkpoint -force ${TOP_NAME}_routed.dcp
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report_drc -file ${TOP_NAME}_drc_routed.rpt -pb ${TOP_NAME}_drc_routed.pb
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report_timing_summary -warn_on_violation -max_paths 10 -file ${TOP_NAME}_timing_summary_routed.rpt -rpx ${TOP_NAME}_timing_summary_routed.rpx
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report_power -file ${TOP_NAME}_power_routed.rpt -pb ${TOP_NAME}_power_summary_routed.pb
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report_route_status -file ${TOP_NAME}_route_status.rpt -pb ${TOP_NAME}_route_status.pb
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report_clock_utilization -file ${TOP_NAME}_clock_utilization_routed.rpt

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