OpenCores
URL https://opencores.org/ocsvn/wf3d/wf3d/trunk

Subversion Repositories wf3d

[/] [wf3d/] [trunk/] [implement/] [synth/] [zedboard/] [ip.tcl] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 specular 
# project configuration
2 
set PROJ_NAME polyphony
3 
set BD_NAME zed_base
4 
set BD_DIR ./${PROJ_NAME}.srcs/sources_1/bd/${BD_NAME}
5 
create_project -verbose -force -part xc7z020clg484-1 ${PROJ_NAME}
6 
set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
7 
create_bd_design -verbose ${BD_NAME}
8 
puts [get_property DIRECTORY [current_project]]
9 
#set_property ip_repo_paths G:/Xilinx/Vivado/2015.4/data/ip [current_fileset]
10 
#update_ip_catalog
11 
 
12 
startgroup
13 
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
14 
endgroup
15 
startgroup
16 
set_property -dict [list CONFIG.preset {ZedBoard}] [get_bd_cells processing_system7_0]
17 
endgroup
18 
 
19 
startgroup
20 
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {50.000000}] [get_bd_cells processing_system7_0]
21 
endgroup
22 
 
23 
startgroup
24 
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR
25 
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/DDR] [get_bd_intf_ports DDR]
26 
endgroup
27 
startgroup
28 
create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO
29 
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/FIXED_IO] [get_bd_intf_ports FIXED_IO]
30 
endgroup
31 
startgroup
32 
 
33 
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_IRQ_F2P_INTR {1}] [get_bd_cells processing_system7_0]
34 
endgroup
35 
startgroup
36 
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
37 
endgroup
38 
startgroup
39 
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP1" Clk "Auto" }  [get_bd_intf_pins axi_gpio_0/S_AXI]
40 
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "btns_5bits ( Push buttons ) " }  [get_bd_intf_pins axi_gpio_0/GPIO]
41 
endgroup
42 
startgroup
43 
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1
44 
endgroup
45 
startgroup
46 
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP1" Clk "Auto" }  [get_bd_intf_pins axi_gpio_1/S_AXI]
47 
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "leds_8bits ( LED ) " }  [get_bd_intf_pins axi_gpio_1/GPIO]
48 
endgroup
49 
startgroup
50 
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2
51 
endgroup
52 
startgroup
53 
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP1" Clk "Auto" }  [get_bd_intf_pins axi_gpio_2/S_AXI]
54 
apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "sws_8bits ( DIP switches ) " }  [get_bd_intf_pins axi_gpio_2/GPIO]
55 
endgroup
56 
startgroup
57 
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_GP0
58 
set_property -dict [list CONFIG.PROTOCOL [get_property CONFIG.PROTOCOL [get_bd_intf_pins processing_system7_0/M_AXI_GP0]] CONFIG.HAS_REGION [get_property CONFIG.HAS_REGION [get_bd_intf_pins processing_system7_0/M_AXI_GP0]] CONFIG.NUM_READ_OUTSTANDING [get_property CONFIG.NUM_READ_OUTSTANDING [get_bd_intf_pins processing_system7_0/M_AXI_GP0]] CONFIG.NUM_WRITE_OUTSTANDING [get_property CONFIG.NUM_WRITE_OUTSTANDING [get_bd_intf_pins processing_system7_0/M_AXI_GP0]]] [get_bd_intf_ports M_AXI_GP0]
59 
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_ports M_AXI_GP0]
60 
endgroup
61 
set_property name M_AXI [get_bd_intf_ports M_AXI_GP0]
62 
startgroup
63 
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_ACP
64 
set_property -dict [list CONFIG.DATA_WIDTH [get_property CONFIG.DATA_WIDTH [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.PROTOCOL [get_property CONFIG.PROTOCOL [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.ID_WIDTH [get_property CONFIG.ID_WIDTH [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.AWUSER_WIDTH [get_property CONFIG.AWUSER_WIDTH [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.ARUSER_WIDTH [get_property CONFIG.ARUSER_WIDTH [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.HAS_REGION [get_property CONFIG.HAS_REGION [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.NUM_READ_OUTSTANDING [get_property CONFIG.NUM_READ_OUTSTANDING [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.NUM_WRITE_OUTSTANDING [get_property CONFIG.NUM_WRITE_OUTSTANDING [get_bd_intf_pins processing_system7_0/S_AXI_ACP]] CONFIG.MAX_BURST_LENGTH [get_property CONFIG.MAX_BURST_LENGTH [get_bd_intf_pins processing_system7_0/S_AXI_ACP]]] [get_bd_intf_ports S_AXI_ACP]
65 
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/S_AXI_ACP] [get_bd_intf_ports S_AXI_ACP]
66 
endgroup
67 
set_property name S_AXI [get_bd_intf_ports S_AXI_ACP]
68 
connect_bd_net [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK]
69 
connect_bd_net [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
70 
startgroup
71 
create_bd_port -dir O -type clk FCLK_CLK0
72 
connect_bd_net [get_bd_pins /processing_system7_0/FCLK_CLK0] [get_bd_ports FCLK_CLK0]
73 
endgroup
74 
startgroup
75 
create_bd_port -dir O -type rst FCLK_RESET0_N
76 
connect_bd_net [get_bd_pins /processing_system7_0/FCLK_RESET0_N] [get_bd_ports FCLK_RESET0_N]
77 
endgroup
78 
set_property CONFIG.ASSOCIATED_BUSIF {M_AXI} [get_bd_ports /FCLK_CLK0]
79 
set_property CONFIG.ASSOCIATED_BUSIF {M_AXI:S_AXI} [get_bd_ports /FCLK_CLK0]
80 
startgroup
81 
create_bd_port -dir I -from 0 -to 0 -type intr IRQ_F2P
82 
connect_bd_net [get_bd_pins /processing_system7_0/IRQ_F2P] [get_bd_ports IRQ_F2P]
83 
endgroup
84 
assign_bd_address
85 
validate_bd_design
86 
save_bd_design
87 
 
88 8 specular 
# version check
89 
if {[expr [version -short]] >= 2016.3} {
90 
set_property synth_checkpoint_mode None [get_files ${BD_DIR}/${BD_NAME}.bd]
91 
}
92 5 specular 
generate_target -force all [get_files ${BD_DIR}/${BD_NAME}.bd]
93 
export_ip_user_files -of_objects [get_files ${BD_DIR}/${BD_NAME}.bd] -no_script -force -quiet
94 8 specular 
 
95 5 specular 
close_project
96 
 
97 
#write_checkpoint -force -file bd_checkpoint.dcp
98 
#synth
99 
#source zed_base_wrapper.tcl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.