1 |
5 |
specular |
set PROJ_NAME polyphony
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2 |
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set PROJ_DIR .
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3 |
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set RTL_3D_DIR ../../../rtl
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4 |
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set RTL_AXI_DIR ../../rtl/axi_cmn
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5 |
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set RTL_BD_DIR ../../rtl/zedboard
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6 |
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set RTL_HVC_DIR ../../rtl/fm_hvc
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7 |
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set TOP_NAME zed_base_wrapper
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8 |
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9 |
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create_project -in_memory -part xc7z020clg484-1
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10 |
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11 |
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#set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
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12 |
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set_property parent.project_path ${PROJ_DIR}/${PROJ_NAME}.xpr [current_project]
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13 |
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set_property default_lib xil_defaultlib [current_project]
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14 |
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set_property target_language Verilog [current_project]
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15 |
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set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
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16 |
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set_property vhdl_version vhdl_2k [current_fileset]
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17 |
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add_files ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base.bd
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18 |
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19 |
8 |
specular |
# version check
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20 |
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if {[expr [version -short]] >= 2016.3} {
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21 |
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set PS7 ps7
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22 |
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} else {
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23 |
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set PS7 processing_system7
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24 |
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}
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25 |
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26 |
5 |
specular |
set XDC_LIST "\
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27 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_board.xdc \
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28 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_ooc.xdc \
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29 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0.xdc \
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30 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_board.xdc \
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31 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_ooc.xdc \
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32 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0.xdc \
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33 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_board.xdc \
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34 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_ooc.xdc \
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35 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0.xdc \
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36 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_processing_system7_0_0/zed_base_processing_system7_0_0.xdc \
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37 |
8 |
specular |
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_${PS7}_0_50M_0/zed_base_rst_${PS7}_0_50M_0_board.xdc \
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38 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_${PS7}_0_50M_0/zed_base_rst_${PS7}_0_50M_0.xdc \
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39 |
5 |
specular |
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_xbar_0/zed_base_xbar_0_ooc.xdc \
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40 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_auto_pc_0/zed_base_auto_pc_0_ooc.xdc \
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41 |
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${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base_ooc.xdc \
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42 |
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"
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43 |
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foreach i $XDC_LIST {
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44 |
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set_property used_in_implementation false [get_files -all ${i} ]
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45 |
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}
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46 |
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47 |
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set V_LIST "\
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48 |
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${RTL_3D_DIR}/core/fm_geo_tri.v\
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49 |
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${RTL_3D_DIR}/core/fm_3d_f22_to_i.v\
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50 |
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${RTL_3D_DIR}/core/fm_geo_clip.v\
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51 |
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${RTL_3D_DIR}/core/fm_geo_cull.v\
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52 |
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${RTL_3D_DIR}/core/fm_3d_norm.v\
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53 |
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${RTL_3D_DIR}/core/fm_3d_fcnv.v\
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54 |
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${RTL_3D_DIR}/core/fm_3d_frcp_rom.v\
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55 |
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${RTL_3D_DIR}/core/fm_3d_frcp.v\
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56 |
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${RTL_3D_DIR}/core/fm_3d_fmul.v\
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57 |
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${RTL_3D_DIR}/core/fm_3d_fadd.v\
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58 |
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${RTL_3D_DIR}/core/fm_sys.v\
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59 |
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${RTL_3D_DIR}/core/fm_geo_viewport.v\
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60 |
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${RTL_3D_DIR}/core/fm_ras_state.v\
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61 |
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${RTL_3D_DIR}/core/fm_ras_mem.v\
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62 |
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${RTL_3D_DIR}/core/fm_ras_line.v\
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63 |
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${RTL_3D_DIR}/core/fm_ras.v\
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64 |
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${RTL_3D_DIR}/core/fm_geo_persdiv.v\
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65 |
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${RTL_3D_DIR}/core/fm_mem_arb.v\
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66 |
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${RTL_3D_DIR}/core/fm_geo_matrix.v\
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67 |
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${RTL_3D_DIR}/core/fm_geo_mem.v\
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68 |
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${RTL_3D_DIR}/core/fm_geo.v\
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69 |
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${RTL_3D_DIR}/core/fm_3d_core.v\
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70 |
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${RTL_BD_DIR}/polyphony_def.v\
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71 |
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${RTL_AXI_DIR}/fm_axi_s.v\
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72 |
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${RTL_AXI_DIR}/fm_4k_split.v\
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73 |
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${RTL_AXI_DIR}/fm_axi_m.v\
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74 |
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${RTL_AXI_DIR}/fm_fifo.v\
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75 |
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${RTL_AXI_DIR}/fm_dispatch.v\
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76 |
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${RTL_AXI_DIR}/fm_dispatch_dma.v\
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77 |
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${RTL_AXI_DIR}/fm_cmn_if_ff_out.v\
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78 |
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${RTL_AXI_DIR}/fm_asys.v\
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79 |
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${RTL_AXI_DIR}/fm_dma.v\
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80 |
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${RTL_AXI_DIR}/fm_mic.v\
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81 |
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${RTL_AXI_DIR}/fm_mic_cnv.v\
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82 |
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${RTL_AXI_DIR}/fm_cmn_bfifo.v\
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83 |
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${RTL_AXI_DIR}/fm_cmn_bram_01.v\
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84 |
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${RTL_AXI_DIR}/fm_cinterface.v\
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85 |
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${RTL_AXI_DIR}/fm_dinterface.v\
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86 |
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${RTL_AXI_DIR}/fm_ififo.v\
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87 |
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${RTL_AXI_DIR}/fm_port_unit.v\
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88 |
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${RTL_AXI_DIR}/fm_port_priority.v\
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89 |
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${RTL_AXI_DIR}/fm_raw_fifo.v\
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90 |
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${RTL_HVC_DIR}/fm_hvc.v\
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91 |
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${RTL_HVC_DIR}/fm_hvc_core.v\
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92 |
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${RTL_HVC_DIR}/fm_hvc_dma.v\
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93 |
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${RTL_HVC_DIR}/fm_hvc_data.v\
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94 |
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${RTL_HVC_DIR}/fm_cmn_ram.v\
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95 |
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${RTL_HVC_DIR}/fm_afifo.v\
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96 |
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${RTL_BD_DIR}/zq_top.v\
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97 |
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${RTL_BD_DIR}/${TOP_NAME}.v \
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98 |
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"
|
99 |
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foreach i $V_LIST {
|
100 |
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read_verilog -library xil_defaultlib ${i}
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101 |
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}
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102 |
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103 |
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read_xdc user_const.xdc
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104 |
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set_property used_in_implementation false [get_files user_const.xdc]
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105 |
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106 |
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read_xdc dont_touch.xdc
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107 |
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set_property used_in_implementation false [get_files dont_touch.xdc]
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108 |
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|
109 |
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synth_design -top ${TOP_NAME} -part xc7z020clg484-1 -verilog_define PP_BUSWIDTH_64=1 -include_dirs {../../rtl/zedboard ../../rtl/axi_cmn} -fanout_limit 10000 -flatten_hierarchy rebuilt
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110 |
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write_checkpoint -force ${TOP_NAME}.dcp
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111 |
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report_utilization -file ${TOP_NAME}_utilization_synth.rpt -pb ${TOP_NAME}_utilization_synth.pb
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