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Subversion Repositories wf3d

[/] [wf3d/] [trunk/] [implement/] [synth/] [zedboard/] [synth.tcl] - Blame information for rev 8

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Line No. Rev Author Line
1 5 specular 
set PROJ_NAME polyphony
2 
set PROJ_DIR .
3 
set RTL_3D_DIR ../../../rtl
4 
set RTL_AXI_DIR ../../rtl/axi_cmn
5 
set RTL_BD_DIR ../../rtl/zedboard
6 
set RTL_HVC_DIR ../../rtl/fm_hvc
7 
set TOP_NAME zed_base_wrapper
8 
 
9 
create_project -in_memory -part xc7z020clg484-1
10 
 
11 
#set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
12 
set_property parent.project_path ${PROJ_DIR}/${PROJ_NAME}.xpr [current_project]
13 
set_property default_lib xil_defaultlib [current_project]
14 
set_property target_language Verilog [current_project]
15 
set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
16 
set_property vhdl_version vhdl_2k [current_fileset]
17 
add_files ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base.bd
18 
 
19 8 specular 
# version check
20 
if {[expr [version -short]] >= 2016.3} {
21 
  set PS7 ps7
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} else {
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  set PS7 processing_system7
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}
25 
 
26 5 specular 
set XDC_LIST "\
27 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_board.xdc \
28 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_ooc.xdc \
29 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0.xdc \
30 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_board.xdc \
31 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_ooc.xdc \
32 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0.xdc \
33 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_board.xdc \
34 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_ooc.xdc \
35 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0.xdc \
36 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_processing_system7_0_0/zed_base_processing_system7_0_0.xdc \
37 8 specular 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_${PS7}_0_50M_0/zed_base_rst_${PS7}_0_50M_0_board.xdc \
38 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_${PS7}_0_50M_0/zed_base_rst_${PS7}_0_50M_0.xdc \
39 5 specular 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_xbar_0/zed_base_xbar_0_ooc.xdc \
40 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_auto_pc_0/zed_base_auto_pc_0_ooc.xdc \
41 
  ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base_ooc.xdc \
42 
"
43 
foreach i $XDC_LIST {
44 
  set_property used_in_implementation false [get_files -all ${i} ]
45 
}
46 
 
47 
set V_LIST "\
48 
  ${RTL_3D_DIR}/core/fm_geo_tri.v\
49 
  ${RTL_3D_DIR}/core/fm_3d_f22_to_i.v\
50 
  ${RTL_3D_DIR}/core/fm_geo_clip.v\
51 
  ${RTL_3D_DIR}/core/fm_geo_cull.v\
52 
  ${RTL_3D_DIR}/core/fm_3d_norm.v\
53 
  ${RTL_3D_DIR}/core/fm_3d_fcnv.v\
54 
  ${RTL_3D_DIR}/core/fm_3d_frcp_rom.v\
55 
  ${RTL_3D_DIR}/core/fm_3d_frcp.v\
56 
  ${RTL_3D_DIR}/core/fm_3d_fmul.v\
57 
  ${RTL_3D_DIR}/core/fm_3d_fadd.v\
58 
  ${RTL_3D_DIR}/core/fm_sys.v\
59 
  ${RTL_3D_DIR}/core/fm_geo_viewport.v\
60 
  ${RTL_3D_DIR}/core/fm_ras_state.v\
61 
  ${RTL_3D_DIR}/core/fm_ras_mem.v\
62 
  ${RTL_3D_DIR}/core/fm_ras_line.v\
63 
  ${RTL_3D_DIR}/core/fm_ras.v\
64 
  ${RTL_3D_DIR}/core/fm_geo_persdiv.v\
65 
  ${RTL_3D_DIR}/core/fm_mem_arb.v\
66 
  ${RTL_3D_DIR}/core/fm_geo_matrix.v\
67 
  ${RTL_3D_DIR}/core/fm_geo_mem.v\
68 
  ${RTL_3D_DIR}/core/fm_geo.v\
69 
  ${RTL_3D_DIR}/core/fm_3d_core.v\
70 
  ${RTL_BD_DIR}/polyphony_def.v\
71 
  ${RTL_AXI_DIR}/fm_axi_s.v\
72 
  ${RTL_AXI_DIR}/fm_4k_split.v\
73 
  ${RTL_AXI_DIR}/fm_axi_m.v\
74 
  ${RTL_AXI_DIR}/fm_fifo.v\
75 
  ${RTL_AXI_DIR}/fm_dispatch.v\
76 
  ${RTL_AXI_DIR}/fm_dispatch_dma.v\
77 
  ${RTL_AXI_DIR}/fm_cmn_if_ff_out.v\
78 
  ${RTL_AXI_DIR}/fm_asys.v\
79 
  ${RTL_AXI_DIR}/fm_dma.v\
80 
  ${RTL_AXI_DIR}/fm_mic.v\
81 
  ${RTL_AXI_DIR}/fm_mic_cnv.v\
82 
  ${RTL_AXI_DIR}/fm_cmn_bfifo.v\
83 
  ${RTL_AXI_DIR}/fm_cmn_bram_01.v\
84 
  ${RTL_AXI_DIR}/fm_cinterface.v\
85 
  ${RTL_AXI_DIR}/fm_dinterface.v\
86 
  ${RTL_AXI_DIR}/fm_ififo.v\
87 
  ${RTL_AXI_DIR}/fm_port_unit.v\
88 
  ${RTL_AXI_DIR}/fm_port_priority.v\
89 
  ${RTL_AXI_DIR}/fm_raw_fifo.v\
90 
  ${RTL_HVC_DIR}/fm_hvc.v\
91 
  ${RTL_HVC_DIR}/fm_hvc_core.v\
92 
  ${RTL_HVC_DIR}/fm_hvc_dma.v\
93 
  ${RTL_HVC_DIR}/fm_hvc_data.v\
94 
  ${RTL_HVC_DIR}/fm_cmn_ram.v\
95 
  ${RTL_HVC_DIR}/fm_afifo.v\
96 
  ${RTL_BD_DIR}/zq_top.v\
97 
  ${RTL_BD_DIR}/${TOP_NAME}.v \
98 
"
99 
foreach i $V_LIST {
100 
  read_verilog  -library xil_defaultlib ${i}
101 
}
102 
 
103 
read_xdc user_const.xdc
104 
set_property used_in_implementation false [get_files user_const.xdc]
105 
 
106 
read_xdc dont_touch.xdc
107 
set_property used_in_implementation false [get_files dont_touch.xdc]
108 
 
109 
synth_design -top ${TOP_NAME} -part xc7z020clg484-1 -verilog_define PP_BUSWIDTH_64=1 -include_dirs {../../rtl/zedboard ../../rtl/axi_cmn} -fanout_limit 10000 -flatten_hierarchy rebuilt
110 
write_checkpoint -force ${TOP_NAME}.dcp
111 
report_utilization -file ${TOP_NAME}_utilization_synth.rpt -pb ${TOP_NAME}_utilization_synth.pb

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