OpenCores
URL https://opencores.org/ocsvn/wf3d/wf3d/trunk

Subversion Repositories wf3d

[/] [wf3d/] [trunk/] [readme.txt] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 specular
Wire-Frame 3D Graphics Accelerator IP Core
2
Project Monophony
3
================================================
4 4 specular
Author: Kenji Ishimaru 
5 2 specular
 
6 4 specular
2016/08/14
7
new demo appication is added.
8
 
9 2 specular
2015/09/30
10
 
11
Overview
12
------------------------------------------
13
This IP Core is a wire-frame 3D hardware accelerator.
14
 
15
Features:
16
 - Hardware Geometry Engine and Rasterizer
17
   - Model-View-Projection matrix transformation
18
   - Clipping
19
   - Back-face culling
20
   - Viewport mapping
21
   - Wire-Frame rasterization with 8 bit color
22
   - DMAC for reading 3D object vertices
23
     - support triangle format only.
24
       (does NOT support triangle strip, point, line etc.)
25
  - Screen size: up to 2014 x 1536(QXGA)
26
  - Small logic consumption
27
  - Low bandwidth requirement
28
 
29
The IP Core does NOT support:
30
 - Memory clear DMAC
31
 - Filled triangle rasterization
32
 - Texture mapping
33
 - Lighting
34
 
35
Additional resources:
36
 - Sample FPGA system implementation (DE0)
37
   - with original VGA controller
38
 - Demo applications
39
 - C API for controlling 3D scene
40
 - 3D model convert script
41
 
42
For more details,
43
please see doc/3DGraphics_IPCore_Specification.pdf.
44
 
45
 
46
Directories
47
---------------------------------------
48
 
49
The directory structure looks as follows:
50
doc/            - Documentation
51
rtl/            - HDL source code
52
scenario/       - Simulation test benches
53
bin/            - Simulation scripts
54
sim_work/       - Simulation work directory
55
implement/      - FPGA implementation example (DE0)
56
tool/           - 3D model convert tool and sample.
57
clib/           - C API source code
58
demo_app/       - Demo applications
59
 
60
IP Core Source Code
61
----------------------------
62
The IP Core is written by verilog-HDL. The source code is Vendor independent.
63
does not require any Vendor specific module.
64
 
65
Simulation
66
----------------------------
67
scenario directory contains simple rendering bench.
68
the rendering result  is converted to bmp file.
69
 
70
For more details, please see sim_work/readme.txt
71
 
72
FPGA Sample Implementation
73
----------------------------
74
FPGA system implementation sample is available.
75
The target board is DE0.
76
The project data is tested on Quartus II Version 13.1
77
 
78
For more details, please see implement/readme.txt
79
 
80
Graphics C API
81
----------------------------
82
clib/ contains C API source code for this IP Core.
83
The API controls 3D scene, and controls IP Core by register configuration.
84
 
85
For more details,
86
please see doc/3DGraphics_C_Library_Specification.pdf.
87
 
88
 
89
Demo Application
90
----------------------------
91
demo_app/ contains demo applications.
92
simple_cube: rotating cube demo
93
main_cubes:  rotating cubes. matrix push/pop demo
94
main_bear:   bear characters
95
main_hand:   hand animation
96
 
97
Screen shots of these demos are available in screen_shot/
98
 
99
3D Data Tool
100
----------------------------
101
tool/objcnv.pl perl script convertes .obj format 3D data to
102
C float array format, and output as C header file.
103
 
104
For more details, please see tool/readme.txt

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.