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//=======================================================================
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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// floating point to integer conversion
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//
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// Abstract:
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// IP Core top module
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//
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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module fm_3d_f22_to_i (
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i_a,
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o_b
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);
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///////////////////////////////////////////
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// port definition
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///////////////////////////////////////////
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input [21:0] i_a; // input s1, e5, f1.15
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output [15:0] o_b; // 2's complement value
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///////////////////////////////////////////
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// wire definition
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///////////////////////////////////////////
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// intermidiate wire
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wire [4:0] w_exp;
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wire [15:0] w_fraction;
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wire w_s;
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wire [15:0] w_ui;
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wire [15:0] w_ui_2c;
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///////////////////////////////////////////
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// assign statement
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///////////////////////////////////////////
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assign w_s = i_a[21];
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assign w_exp = i_a[20:16];
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assign w_fraction = i_a[15:0];
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assign w_ui = f_ftoi(w_exp, w_fraction);
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assign w_ui_2c = ~w_ui + 1'b1;
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assign o_b = (w_s) ? w_ui_2c : w_ui;
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///////////////////////////////////////////
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// function statement
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///////////////////////////////////////////
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function [15:0] f_ftoi;
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input [4:0] exp;
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input [15:0] frac;
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reg [5:0] ee;
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begin
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ee = exp - 4'd15; // remove bias
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if (ee[5]) begin
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f_ftoi = 16'h0;
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end else begin
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case (ee[4:0])
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5'd0: f_ftoi = {15'b0,frac[15]}; // bias 0
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5'd1: f_ftoi = {14'b0,frac[15:14]};
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5'd2: f_ftoi = {13'b0,frac[15:13]};
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5'd3: f_ftoi = {12'b0,frac[15:12]};
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5'd4: f_ftoi = {11'b0,frac[15:11]};
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5'd5: f_ftoi = {10'b0,frac[15:10]};
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5'd6: f_ftoi = {9'b0,frac[15:9]};
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5'd7: f_ftoi = {8'b0,frac[15:8]};
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5'd8: f_ftoi = {7'b0,frac[15:7]};
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5'd9: f_ftoi = {6'b0,frac[15:6]};
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5'd10: f_ftoi = {5'b0,frac[15:5]};
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5'd11: f_ftoi = {4'b0,frac[15:4]};
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5'd12: f_ftoi = {3'b0,frac[15:3]};
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5'd13: f_ftoi = {2'b0,frac[15:2]};
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5'd14: f_ftoi = {1'b0,frac[15:1]};
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5'd15: f_ftoi = frac[15:0];
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default: f_ftoi = 16'h0;
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endcase
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end
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end
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endfunction
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endmodule
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