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//=======================================================================
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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// fm_geo_clip.v
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//
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// Abstract:
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// Clipping module. generate clipping code.
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//
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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`include "fm_3d_define.v"
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module fm_geo_clip (
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input clk_core,
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input rst_x,
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output o_state,
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// vertex input
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input i_en,
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output o_ack,
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input [21:0] i_vx,
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input [21:0] i_vy,
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input [21:0] i_vz,
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input [21:0] i_vw,
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// vertex output
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output o_en,
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input i_ack,
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output [21:0] o_vx,
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output [21:0] o_vy,
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output [21:0] o_vw,
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output [5:0] o_outcode
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);
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localparam P_IDLE = 'd0; // X_M1_PLANE
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localparam P_X_P1_PLANE = 'd1;
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localparam P_Y_M1_PLANE = 'd2;
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localparam P_Y_P1_PLANE = 'd3;
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localparam P_Z_M1_PLANE = 'd4;
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localparam P_Z_P1_PLANE = 'd5;
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localparam P_WADD0 = 'd6;
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localparam P_WADD1 = 'd7;
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localparam P_WADD2 = 'd8;
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localparam P_DONE = 'd9;
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//////////////////////////////////
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// regs
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//////////////////////////////////
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reg [3:0] r_state;
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reg [21:0] r_vx;
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reg [21:0] r_vy;
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reg [21:0] r_vz;
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reg [21:0] r_vw;
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reg [5:0] r_bc;
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//////////////////////////////////
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// wire
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//////////////////////////////////
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wire w_set_vtx;
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wire [21:0] w_add_in_a;
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wire [21:0] w_add_in_b;
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wire [21:0] w_add_out;
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wire w_adsb;
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wire [5:0] w_set_bc;
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//////////////////////////////////
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// assign
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//////////////////////////////////
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assign o_state = (r_state == P_IDLE);
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assign w_set_vtx = (r_state == P_IDLE) & i_en;
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assign o_en = (r_state == P_DONE);
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assign o_ack = (r_state == P_IDLE);
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assign o_vx = r_vx;
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assign o_vy = r_vy;
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assign o_vw = r_vw;
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assign w_add_in_a = (r_state == P_IDLE) ? i_vw : r_vw; // W
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assign w_add_in_b = (r_state == P_X_P1_PLANE) ? r_vx : // x,y,z
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(r_state == P_Y_M1_PLANE) ? r_vy :
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(r_state == P_Y_P1_PLANE) ? r_vy :
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(r_state == P_Z_M1_PLANE) ? r_vz :
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(r_state == P_Z_P1_PLANE) ? r_vz :
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i_vx;
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assign w_adsb = (r_state == P_IDLE) |
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(r_state == P_Y_M1_PLANE) |
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(r_state == P_Z_M1_PLANE);
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assign w_set_bc[0] = (r_state == P_Y_P1_PLANE);
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assign w_set_bc[1] = (r_state == P_Z_M1_PLANE);
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assign w_set_bc[2] = (r_state == P_Z_P1_PLANE);
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assign w_set_bc[3] = (r_state == P_WADD0);
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assign w_set_bc[4] = (r_state == P_WADD1);
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assign w_set_bc[5] = (r_state == P_WADD2);
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// BC < 0 : outside
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// BC = 0 : on the plane
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// BC > 0 : inside
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assign o_outcode = r_bc;
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// o_outcode[0] : -X plane
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// o_outcode[1] : +X plane
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// o_outcode[2] : -Y plane
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// o_outcode[3] : +Y plane
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// o_outcode[4] : -Z plane
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// o_outcode[5] : +Z plane
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//////////////////////////////////
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// always
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//////////////////////////////////
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always @(posedge clk_core) begin
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if (w_set_vtx) begin
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r_vx <= i_vx;
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r_vy <= i_vy;
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r_vz <= i_vz;
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r_vw <= i_vw;
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end
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end
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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`else
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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if (rst_x == `D3D_RESET_POL) begin
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r_bc <= 6'b0;
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end else begin
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if (w_set_bc[0]) r_bc[0] <= w_add_out[21];
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if (w_set_bc[1]) r_bc[1] <= w_add_out[21];
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if (w_set_bc[2]) r_bc[2] <= w_add_out[21];
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if (w_set_bc[3]) r_bc[3] <= w_add_out[21];
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if (w_set_bc[4]) r_bc[4] <= w_add_out[21];
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if (w_set_bc[5]) r_bc[5] <= w_add_out[21];
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end
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end
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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`else
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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if (rst_x == `D3D_RESET_POL) begin
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r_state <= P_IDLE;
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end else begin
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case (r_state)
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P_IDLE: begin // P_X_M1_PLANE
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if (i_en) r_state <= P_X_P1_PLANE;
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end
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P_X_P1_PLANE: r_state <= P_Y_M1_PLANE;
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P_Y_M1_PLANE: r_state <= P_Y_P1_PLANE;
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P_Y_P1_PLANE: r_state <= P_Z_M1_PLANE;
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P_Z_M1_PLANE: r_state <= P_Z_P1_PLANE;
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P_Z_P1_PLANE: r_state <= P_WADD0;
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P_WADD0: r_state <= P_WADD1;
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P_WADD1: r_state <= P_WADD2;
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P_WADD2: r_state <= P_DONE;
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P_DONE: begin
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if (i_ack) r_state <= P_IDLE;
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end
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endcase
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end
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end
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//////////////////////////////////
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// module instance
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//////////////////////////////////
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fm_3d_fadd u_fadd (
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.clk_core(clk_core),
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.i_en(1'b1),
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.i_a(w_add_in_a),
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.i_b(w_add_in_b),
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.i_adsb(w_adsb),
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.o_c(w_add_out)
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);
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endmodule
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