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[/] [wf3d/] [trunk/] [rtl/] [core/] [fm_ras_mem.v] - Blame information for rev 2

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//=======================================================================
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// Project Monophony
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//   Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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//   fm_ras_mem.v
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//
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// Abstract:
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//   Write a pixel to mein memory
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//   generate linear address from x, y position
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//
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// Author:
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//   Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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//  -Redistributions of source code must retain the above copyright notice,
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//   this list of conditions and the following disclaimer.
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//  -Redistributions in binary form must reproduce the above copyright notice,
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//   this list of conditions and the following disclaimer in the documentation
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//   and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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`include "fm_3d_define.v"
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module fm_ras_mem (
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  // system
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  input         clk_core,
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  input         rst_x,
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  // Register Configuration
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  input [15:0]  i_scr_w,
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  input [15:0]  i_scr_h_m1,
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  input [29:0]  i_pixel_top_address,
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  input [7:0]   i_pixel_color,
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  input         i_y_flip,
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  // Pixel In
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  input         i_en,
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  output        o_ack,
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  input  [`D3D_FTOI_WIDTH-1:0] i_x,
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  input  [`D3D_FTOI_WIDTH-1:0] i_y,
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  // Pixel Write Memory I/F (Write Only)
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  output        o_req_m,
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  output [31:0] o_adrs_m,
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  input         i_ack_m,
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  output [3:0]  o_be_m,
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  output [31:0] o_dbw_m
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);
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localparam P_IDLE = 'd0;
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localparam P_REQ = 'd1;
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//////////////////////////////////
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// reg
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//////////////////////////////////
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reg         r_state;
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reg [1:0]   r_x;
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reg [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-2:0] r_adrs_m;  // word address
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//////////////////////////////////
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// wire
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//////////////////////////////////
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wire        w_set_adrs;
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wire [`D3D_FTOI_WIDTH+`D3D_FTOI_WIDTH-2:0] w_adrs;
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wire [`D3D_FTOI_WIDTH-1:0]  w_y;
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wire [29:0] w_top_adrs;
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//////////////////////////////////
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// assign
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//////////////////////////////////
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assign o_req_m = (r_state == P_REQ);
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assign o_be_m = (r_x[1:0] == 2'b00) ? 4'h1 :
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                (r_x[1:0] == 2'b01) ? 4'h2 :
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                (r_x[1:0] == 2'b10) ? 4'h4 : 4'h8;
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assign o_dbw_m = {4{i_pixel_color}};
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// Byte address
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//assign w_y = (i_y_flip) ? 'd479 - i_y : i_y;
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assign w_y = (i_y_flip) ? i_scr_h_m1 - i_y : i_y;
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// i_scr_w/4 : 1 pixel = 8bit
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assign w_adrs = i_scr_w[15:2]*w_y + i_x[`D3D_FTOI_WIDTH-1:2];  // exp: 640x480 = 307200(4b000h)
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assign w_set_adrs = (r_state == P_IDLE) |
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                    ((r_state == P_REQ)&i_ack_m&i_en);
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assign w_top_adrs = i_pixel_top_address + r_adrs_m;
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assign o_adrs_m = {w_top_adrs,2'h0};
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assign o_ack = (r_state == P_REQ) & i_ack_m;
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//////////////////////////////////
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// always
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//////////////////////////////////
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always @(posedge clk_core) begin
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  if (w_set_adrs) begin
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    r_x <= i_x[1:0];
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    r_adrs_m <= w_adrs;
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  end
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end
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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`else
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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  if (rst_x == `D3D_RESET_POL) begin
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    r_state <= P_IDLE;
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  end else begin
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    case (r_state)
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      P_IDLE: begin
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        if (i_en) r_state <= P_REQ;
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      end
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      P_REQ: begin
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        if (i_ack_m) begin
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           if (i_en) r_state <= P_REQ;
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           else r_state <= P_IDLE;
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        end
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      end
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    endcase
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  end
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end
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`ifdef RTL_DEBUG
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  always @(posedge clk_core) begin
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     if (i_en & o_ack) $display("write pixel at x,y = %d %d, color = %h",i_x,i_y,i_pixel_color);
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  end
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`endif
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endmodule

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