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[/] [wiegand_ctl/] [trunk/] [bench/] [testbench_rx_top.v.bak] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  weigand_tx_top.v                                            ////
////                                                              ////
////                                                              ////
////  This file is part of the Time Triggered Protocol Controller ////
////  http://www.opencores.org/projects/weigand/                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Jeff Anderson                                          ////
////       jeaander@opencores.org                                 ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The Weigand protocol is maintained by                        ////
//// This product has been tested to interoperate with certified  ////
//// devices, but has not been certified itself.  This product    ////
//// should be certified through prior to claiming strict         ////
//// adherence to the standard.                                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//  Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
 
module testbench_top;
  reg [5:0]   wb_addr_i;
  reg [31:0]  wb_dat_i;
  wire [31:0]  wb_dat_o;
  reg         wb_cyc_i;
  reg         wb_stb_i;
  reg [2:0]   wb_cti_i;
  reg [3:0]  wb_sel_i;
  reg         wb_we_i;
  reg         wb_rst_i;
  reg         wb_clk_i;
 
  //DUTs
  //wiegand_tx_top wiegand_tx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
  //                              wb_ack_o,wb_err_o,wb_rty_o);
 
  //wiegand_rx_top wiegand_rx_top(one_i,zero_i,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_we_i,wb_addr_i,
  //                              wb_ack_o,wb_err_o,wb_rty_o);
 
  //tasks for simulation
 
  initial begin
    wb_addr_i = 6'h0;
    wb_dat_i = 32'h0;
    wb_cyc_i = 1'b0;
    wb_stb_i = 1'b0;
    wb_we_i = 1'b0;
    wb_rst_i = 1'b0;
    wb_clk_i = 1'b0;
  end
 
  always
    #5 wb_clk_i = !wb_clk_i;
 
  task wb_rst;
    begin
          wb_rst_i = 1'b1;
      #20 wb_rst_i = 1'b0;
    end
  endtask
 
  task wb_write_async;
    input [31:0] wb_data;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WIEGAND_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_write_sync;
    input [31:0] wb_data;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WIEGAND_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WIEGAND_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writep2p_async;
    input [31:0] p2p;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_P2P;
        wb_dat_i = p2p;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writepw_async;
    input [31:0] pw;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_PW;
        wb_dat_i = pw;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writesize_async;
    input [31:0] size;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_MSGSIZE;
        wb_dat_i = (size & 32'h7F);
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writesend_async;
    input [31:0] size;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_MSGSIZE;
        wb_dat_i = (size | 32'h80);
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_read_async;
    begin
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b0;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
      end
    end
  endtask
 
  task wb_read_sync;
    begin
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b0;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
      end
    end
  endtask
 
endmodule

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Subversion Repositories wiegand_ctl

[/] [wiegand_ctl/] [trunk/] [bench/] [testbench_rx_top.v.bak] - Blame information for rev 14

Line No.	Rev	Author	Line
1	14	jeaander	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// weigand_tx_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the Time Triggered Protocol Controller ////`
7			`//// http://www.opencores.org/projects/weigand/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Jeff Anderson ////`
12			`//// jeaander@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2013 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//// The Weigand protocol is maintained by ////`
44			`//// This product has been tested to interoperate with certified ////`
45			`//// devices, but has not been certified itself. This product ////`
46			`//// should be certified through prior to claiming strict ////`
47			`//// adherence to the standard. ////`
48			`//// ////`
49			`//////////////////////////////////////////////////////////////////////`
50			`//`
51			`// Revisions at end of file`
52			`//`
53
54			`include "timescale.v"
55			`include "wiegand_defines.v"
56
57			`module testbench_top;`
58			`reg [5:0] wb_addr_i;`
59			`reg [31:0] wb_dat_i;`
60			`wire [31:0] wb_dat_o;`
61			`reg wb_cyc_i;`
62			`reg wb_stb_i;`
63			`reg [2:0] wb_cti_i;`
64			`reg [3:0] wb_sel_i;`
65			`reg wb_we_i;`
66			`reg wb_rst_i;`
67			`reg wb_clk_i;`
68
69			`//DUTs`
70			`//wiegand_tx_top wiegand_tx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,`
71			`// wb_ack_o,wb_err_o,wb_rty_o);`
72
73			`//wiegand_rx_top wiegand_rx_top(one_i,zero_i,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_we_i,wb_addr_i,`
74			`// wb_ack_o,wb_err_o,wb_rty_o);`
75
76			`//tasks for simulation`
77
78			`initial begin`
79			`wb_addr_i = 6'h0;`
80			`wb_dat_i = 32'h0;`
81			`wb_cyc_i = 1'b0;`
82			`wb_stb_i = 1'b0;`
83			`wb_we_i = 1'b0;`
84			`wb_rst_i = 1'b0;`
85			`wb_clk_i = 1'b0;`
86			`end`
87
88			`always`
89			`#5 wb_clk_i = !wb_clk_i;`
90
91			`task wb_rst;`
92			`begin`
93			`wb_rst_i = 1'b1;`
94			`#20 wb_rst_i = 1'b0;`
95			`end`
96			`endtask`
97
98			`task wb_write_async;`
99			`input [31:0] wb_data;`
100			`begin`
101			`@ (posedge wb_clk_i) begin`
102			wb_addr_i = `WIEGAND_ADDR;
103			`wb_dat_i = wb_data;`
104			`wb_stb_i = 1'b1;`
105			`wb_cyc_i = 1'b1;`
106			`wb_we_i = 1'b1;`
107			`end`
108			`@ (posedge wb_clk_i) begin`
109			`wb_addr_i = 6'h0;`
110			`wb_dat_i = 32'h0;`
111			`wb_stb_i = 1'b0;`
112			`wb_cyc_i = 1'b0;`
113			`wb_we_i = 1'b0;`
114			`end`
115			`end`
116			`endtask`
117
118			`task wb_write_sync;`
119			`input [31:0] wb_data;`
120			`begin`
121			`@ (posedge wb_clk_i) begin`
122			wb_addr_i = `WIEGAND_ADDR;
123			`wb_dat_i = wb_data;`
124			`wb_stb_i = 1'b1;`
125			`wb_cyc_i = 1'b1;`
126			`wb_we_i = 1'b1;`
127			`end`
128			`@ (posedge wb_clk_i) begin`
129			wb_addr_i = `WIEGAND_ADDR;
130			`wb_dat_i = wb_data;`
131			`wb_stb_i = 1'b1;`
132			`wb_cyc_i = 1'b1;`
133			`wb_we_i = 1'b1;`
134			`end`
135			`@ (posedge wb_clk_i) begin`
136			`wb_addr_i = 6'h0;`
137			`wb_dat_i = 32'h0;`
138			`wb_stb_i = 1'b0;`
139			`wb_cyc_i = 1'b0;`
140			`wb_we_i = 1'b0;`
141			`end`
142			`end`
143			`endtask`
144
145			`task wb_writep2p_async;`
146			`input [31:0] p2p;`
147			`begin`
148			`@ (posedge wb_clk_i) begin`
149			wb_addr_i = `WB_CNFG_P2P;
150			`wb_dat_i = p2p;`
151			`wb_stb_i = 1'b1;`
152			`wb_cyc_i = 1'b1;`
153			`wb_we_i = 1'b1;`
154			`end`
155			`@ (posedge wb_clk_i) begin`
156			`wb_addr_i = 6'h0;`
157			`wb_dat_i = 32'h0;`
158			`wb_stb_i = 1'b0;`
159			`wb_cyc_i = 1'b0;`
160			`wb_we_i = 1'b0;`
161			`end`
162			`end`
163			`endtask`
164
165			`task wb_writepw_async;`
166			`input [31:0] pw;`
167			`begin`
168			`@ (posedge wb_clk_i) begin`
169			wb_addr_i = `WB_CNFG_PW;
170			`wb_dat_i = pw;`
171			`wb_stb_i = 1'b1;`
172			`wb_cyc_i = 1'b1;`
173			`wb_we_i = 1'b1;`
174			`end`
175			`@ (posedge wb_clk_i) begin`
176			`wb_addr_i = 6'h0;`
177			`wb_dat_i = 32'h0;`
178			`wb_stb_i = 1'b0;`
179			`wb_cyc_i = 1'b0;`
180			`wb_we_i = 1'b0;`
181			`end`
182			`end`
183			`endtask`
184
185			`task wb_writesize_async;`
186			`input [31:0] size;`
187			`begin`
188			`@ (posedge wb_clk_i) begin`
189			wb_addr_i = `WB_CNFG_MSGSIZE;
190			`wb_dat_i = (size & 32'h7F);`
191			`wb_stb_i = 1'b1;`
192			`wb_cyc_i = 1'b1;`
193			`wb_we_i = 1'b1;`
194			`end`
195			`@ (posedge wb_clk_i) begin`
196			`wb_addr_i = 6'h0;`
197			`wb_dat_i = 32'h0;`
198			`wb_stb_i = 1'b0;`
199			`wb_cyc_i = 1'b0;`
200			`wb_we_i = 1'b0;`
201			`end`
202			`end`
203			`endtask`
204
205			`task wb_writesend_async;`
206			`input [31:0] size;`
207			`begin`
208			`@ (posedge wb_clk_i) begin`
209			wb_addr_i = `WB_CNFG_MSGSIZE;
210			`wb_dat_i = (size \| 32'h80);`
211			`wb_stb_i = 1'b1;`
212			`wb_cyc_i = 1'b1;`
213			`wb_we_i = 1'b1;`
214			`end`
215			`@ (posedge wb_clk_i) begin`
216			`wb_addr_i = 6'h0;`
217			`wb_dat_i = 32'h0;`
218			`wb_stb_i = 1'b0;`
219			`wb_cyc_i = 1'b0;`
220			`wb_we_i = 1'b0;`
221			`end`
222			`end`
223			`endtask`
224
225			`task wb_read_async;`
226			`begin`
227			`@ (posedge wb_clk_i) begin`
228			`wb_stb_i = 1'b1;`
229			`wb_cyc_i = 1'b1;`
230			`wb_we_i = 1'b0;`
231			`end`
232			`@ (posedge wb_clk_i) begin`
233			`wb_stb_i = 1'b0;`
234			`wb_cyc_i = 1'b0;`
235			`end`
236			`end`
237			`endtask`
238
239			`task wb_read_sync;`
240			`begin`
241			`@ (posedge wb_clk_i) begin`
242			`wb_stb_i = 1'b1;`
243			`wb_cyc_i = 1'b1;`
244			`wb_we_i = 1'b0;`
245			`end`
246			`@ (posedge wb_clk_i) begin`
247			`wb_stb_i = 1'b1;`
248			`wb_cyc_i = 1'b1;`
249			`end`
250			`@ (posedge wb_clk_i) begin`
251			`wb_stb_i = 1'b0;`
252			`wb_cyc_i = 1'b0;`
253			`end`
254			`end`
255			`endtask`
256
257			`endmodule`