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[/] [wiegand_ctl/] [trunk/] [bench/] [testbench_top.v.bak] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  weigand_tx_top.v                                            ////
////                                                              ////
////                                                              ////
////  This file is part of the Time Triggered Protocol Controller ////
////  http://www.opencores.org/projects/weigand/                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Jeff Anderson                                          ////
////       jeaander@opencores.org                                 ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The Weigand protocol is maintained by                        ////
//// This product has been tested to interoperate with certified  ////
//// devices, but has not been certified itself.  This product    ////
//// should be certified through prior to claiming strict         ////
//// adherence to the standard.                                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//  Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
 
module testbench_top;
  reg [5:0]   wb_addr_i;
  reg [31:0]  wb_dat_i;
  wire [31:0] wb_dat_o;
  wire [31:0] wb_dat_o_rx;
  reg         wb_cyc_i;
  reg         wb_stb_i;
  reg [2:0]   wb_cti_i;
  reg [3:0]   wb_sel_i;
  reg         wb_we_i;
  reg         wb_rst_i;
  reg         wb_clk_i;
  reg         one_i, zero_i;
 
  //DUTs
  wiegand_tx_top wiegand_tx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
                                wb_ack_o,wb_err_o,wb_rty_o);
 
  wiegand_rx_top wiegand_rx_top(one_i,zero_i,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o_rx,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
                                wb_ack_o_rx,wb_err_o_rx,wb_rty_o_rx);
 
  //tasks for simulation
 
  initial begin
    wb_addr_i = 6'h0;
    wb_dat_i = 32'h0;
    wb_cyc_i = 1'b0;
    wb_stb_i = 1'b0;
    wb_we_i = 1'b0;
    wb_rst_i = 1'b0;
    wb_clk_i = 1'b0;
    one_i = 1'b1;
    zero_i = 1'b1;
  end
 
  always
    #5 wb_clk_i = !wb_clk_i;
 
  /**********************   tasks run by testcases for this testbench ******************/
  //Wiegand bus write tasks
  task wiegand_write;
    input [63:0] wiegand_data;
    input [5:0]  word_length;
    input [5:0]  p2p;
    input [5:0]  pw;
    integer i;
    integer j;
    begin
      j = 0;
      repeat (word_length) begin
        @ (posedge wb_clk_i) begin
          if (wiegand_data[j] == 1'b0) begin
            wiegand0(pw);
          end
          else begin
            wiegand1(pw);
          end
          i = 0;
          while(i <= p2p) begin
            @ (posedge wb_clk_i) begin i=i+1; end
          end
        end
      end
    end
  endtask
 
  task wiegand0;
    input [5:0] pw;
    integer i;
    begin
      for (i = 0; i <= pw; i=i+1) begin
        @(posedge wb_clk_i)  zero_i = 1'b0;
      end
      zero_i = 1'b1;
    end
  endtask
 
  task wiegand1;
    input [5:0] pw;
    integer i;
    begin
      for (i = 0; i <= pw; i=i+1) begin
        @(posedge wb_clk_i)  one_i = 1'b0;
      end
      one_i = 1'b1;
    end
  endtask
 
  //Wishbone readn adn write tasks
  task wb_rst;
    begin
          wb_rst_i = 1'b1;
      #20 wb_rst_i = 1'b0;
    end
  endtask
 
  task wb_write_async;
    input [31:0] wb_data;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WIEGAND_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_write_sync;
    input [31:0] wb_data;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WIEGAND_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WIEGAND_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writep2p_async;
    input [31:0] p2p;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_P2P;
        wb_dat_i = p2p;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writepw_async;
    input [31:0] pw;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_PW;
        wb_dat_i = pw;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writesize_async;
    input [31:0] size;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_MSGSIZE;
        wb_dat_i = (size & 32'h7F);
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writesend_async;
    input [31:0] size;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_MSGSIZE;
        wb_dat_i = (size | 32'h80);
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_read_async;
    begin
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b0;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
      end
    end
  endtask
 
  task wb_read_sync;
    begin
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b0;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
      end
    end
  endtask
 
endmodule

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Subversion Repositories wiegand_ctl

[/] [wiegand_ctl/] [trunk/] [bench/] [testbench_top.v.bak] - Blame information for rev 14

Line No.	Rev	Author	Line
1	14	jeaander	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// weigand_tx_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the Time Triggered Protocol Controller ////`
7			`//// http://www.opencores.org/projects/weigand/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Jeff Anderson ////`
12			`//// jeaander@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2013 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//// The Weigand protocol is maintained by ////`
44			`//// This product has been tested to interoperate with certified ////`
45			`//// devices, but has not been certified itself. This product ////`
46			`//// should be certified through prior to claiming strict ////`
47			`//// adherence to the standard. ////`
48			`//// ////`
49			`//////////////////////////////////////////////////////////////////////`
50			`//`
51			`// Revisions at end of file`
52			`//`
53
54			`include "timescale.v"
55			`include "wiegand_defines.v"
56
57			`module testbench_top;`
58			`reg [5:0] wb_addr_i;`
59			`reg [31:0] wb_dat_i;`
60			`wire [31:0] wb_dat_o;`
61			`wire [31:0] wb_dat_o_rx;`
62			`reg wb_cyc_i;`
63			`reg wb_stb_i;`
64			`reg [2:0] wb_cti_i;`
65			`reg [3:0] wb_sel_i;`
66			`reg wb_we_i;`
67			`reg wb_rst_i;`
68			`reg wb_clk_i;`
69			`reg one_i, zero_i;`
70
71			`//DUTs`
72			`wiegand_tx_top wiegand_tx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,`
73			`wb_ack_o,wb_err_o,wb_rty_o);`
74
75			`wiegand_rx_top wiegand_rx_top(one_i,zero_i,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o_rx,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,`
76			`wb_ack_o_rx,wb_err_o_rx,wb_rty_o_rx);`
77
78			`//tasks for simulation`
79
80			`initial begin`
81			`wb_addr_i = 6'h0;`
82			`wb_dat_i = 32'h0;`
83			`wb_cyc_i = 1'b0;`
84			`wb_stb_i = 1'b0;`
85			`wb_we_i = 1'b0;`
86			`wb_rst_i = 1'b0;`
87			`wb_clk_i = 1'b0;`
88			`one_i = 1'b1;`
89			`zero_i = 1'b1;`
90			`end`
91
92			`always`
93			`#5 wb_clk_i = !wb_clk_i;`
94
95			`/******************** tasks run by testcases for this testbench ****************/`
96			`//Wiegand bus write tasks`
97			`task wiegand_write;`
98			`input [63:0] wiegand_data;`
99			`input [5:0] word_length;`
100			`input [5:0] p2p;`
101			`input [5:0] pw;`
102			`integer i;`
103			`integer j;`
104			`begin`
105			`j = 0;`
106			`repeat (word_length) begin`
107			`@ (posedge wb_clk_i) begin`
108			`if (wiegand_data[j] == 1'b0) begin`
109			`wiegand0(pw);`
110			`end`
111			`else begin`
112			`wiegand1(pw);`
113			`end`
114			`i = 0;`
115			`while(i <= p2p) begin`
116			`@ (posedge wb_clk_i) begin i=i+1; end`
117			`end`
118			`end`
119			`end`
120			`end`
121			`endtask`
122
123			`task wiegand0;`
124			`input [5:0] pw;`
125			`integer i;`
126			`begin`
127			`for (i = 0; i <= pw; i=i+1) begin`
128			`@(posedge wb_clk_i) zero_i = 1'b0;`
129			`end`
130			`zero_i = 1'b1;`
131			`end`
132			`endtask`
133
134			`task wiegand1;`
135			`input [5:0] pw;`
136			`integer i;`
137			`begin`
138			`for (i = 0; i <= pw; i=i+1) begin`
139			`@(posedge wb_clk_i) one_i = 1'b0;`
140			`end`
141			`one_i = 1'b1;`
142			`end`
143			`endtask`
144
145			`//Wishbone readn adn write tasks`
146			`task wb_rst;`
147			`begin`
148			`wb_rst_i = 1'b1;`
149			`#20 wb_rst_i = 1'b0;`
150			`end`
151			`endtask`
152
153			`task wb_write_async;`
154			`input [31:0] wb_data;`
155			`begin`
156			`@ (posedge wb_clk_i) begin`
157			wb_addr_i = `WIEGAND_ADDR;
158			`wb_dat_i = wb_data;`
159			`wb_stb_i = 1'b1;`
160			`wb_cyc_i = 1'b1;`
161			`wb_we_i = 1'b1;`
162			`end`
163			`@ (posedge wb_clk_i) begin`
164			`wb_addr_i = 6'h0;`
165			`wb_dat_i = 32'h0;`
166			`wb_stb_i = 1'b0;`
167			`wb_cyc_i = 1'b0;`
168			`wb_we_i = 1'b0;`
169			`end`
170			`end`
171			`endtask`
172
173			`task wb_write_sync;`
174			`input [31:0] wb_data;`
175			`begin`
176			`@ (posedge wb_clk_i) begin`
177			wb_addr_i = `WIEGAND_ADDR;
178			`wb_dat_i = wb_data;`
179			`wb_stb_i = 1'b1;`
180			`wb_cyc_i = 1'b1;`
181			`wb_we_i = 1'b1;`
182			`end`
183			`@ (posedge wb_clk_i) begin`
184			wb_addr_i = `WIEGAND_ADDR;
185			`wb_dat_i = wb_data;`
186			`wb_stb_i = 1'b1;`
187			`wb_cyc_i = 1'b1;`
188			`wb_we_i = 1'b1;`
189			`end`
190			`@ (posedge wb_clk_i) begin`
191			`wb_addr_i = 6'h0;`
192			`wb_dat_i = 32'h0;`
193			`wb_stb_i = 1'b0;`
194			`wb_cyc_i = 1'b0;`
195			`wb_we_i = 1'b0;`
196			`end`
197			`end`
198			`endtask`
199
200			`task wb_writep2p_async;`
201			`input [31:0] p2p;`
202			`begin`
203			`@ (posedge wb_clk_i) begin`
204			wb_addr_i = `WB_CNFG_P2P;
205			`wb_dat_i = p2p;`
206			`wb_stb_i = 1'b1;`
207			`wb_cyc_i = 1'b1;`
208			`wb_we_i = 1'b1;`
209			`end`
210			`@ (posedge wb_clk_i) begin`
211			`wb_addr_i = 6'h0;`
212			`wb_dat_i = 32'h0;`
213			`wb_stb_i = 1'b0;`
214			`wb_cyc_i = 1'b0;`
215			`wb_we_i = 1'b0;`
216			`end`
217			`end`
218			`endtask`
219
220			`task wb_writepw_async;`
221			`input [31:0] pw;`
222			`begin`
223			`@ (posedge wb_clk_i) begin`
224			wb_addr_i = `WB_CNFG_PW;
225			`wb_dat_i = pw;`
226			`wb_stb_i = 1'b1;`
227			`wb_cyc_i = 1'b1;`
228			`wb_we_i = 1'b1;`
229			`end`
230			`@ (posedge wb_clk_i) begin`
231			`wb_addr_i = 6'h0;`
232			`wb_dat_i = 32'h0;`
233			`wb_stb_i = 1'b0;`
234			`wb_cyc_i = 1'b0;`
235			`wb_we_i = 1'b0;`
236			`end`
237			`end`
238			`endtask`
239
240			`task wb_writesize_async;`
241			`input [31:0] size;`
242			`begin`
243			`@ (posedge wb_clk_i) begin`
244			wb_addr_i = `WB_CNFG_MSGSIZE;
245			`wb_dat_i = (size & 32'h7F);`
246			`wb_stb_i = 1'b1;`
247			`wb_cyc_i = 1'b1;`
248			`wb_we_i = 1'b1;`
249			`end`
250			`@ (posedge wb_clk_i) begin`
251			`wb_addr_i = 6'h0;`
252			`wb_dat_i = 32'h0;`
253			`wb_stb_i = 1'b0;`
254			`wb_cyc_i = 1'b0;`
255			`wb_we_i = 1'b0;`
256			`end`
257			`end`
258			`endtask`
259
260			`task wb_writesend_async;`
261			`input [31:0] size;`
262			`begin`
263			`@ (posedge wb_clk_i) begin`
264			wb_addr_i = `WB_CNFG_MSGSIZE;
265			`wb_dat_i = (size \| 32'h80);`
266			`wb_stb_i = 1'b1;`
267			`wb_cyc_i = 1'b1;`
268			`wb_we_i = 1'b1;`
269			`end`
270			`@ (posedge wb_clk_i) begin`
271			`wb_addr_i = 6'h0;`
272			`wb_dat_i = 32'h0;`
273			`wb_stb_i = 1'b0;`
274			`wb_cyc_i = 1'b0;`
275			`wb_we_i = 1'b0;`
276			`end`
277			`end`
278			`endtask`
279
280			`task wb_read_async;`
281			`begin`
282			`@ (posedge wb_clk_i) begin`
283			`wb_stb_i = 1'b1;`
284			`wb_cyc_i = 1'b1;`
285			`wb_we_i = 1'b0;`
286			`end`
287			`@ (posedge wb_clk_i) begin`
288			`wb_stb_i = 1'b0;`
289			`wb_cyc_i = 1'b0;`
290			`end`
291			`end`
292			`endtask`
293
294			`task wb_read_sync;`
295			`begin`
296			`@ (posedge wb_clk_i) begin`
297			`wb_stb_i = 1'b1;`
298			`wb_cyc_i = 1'b1;`
299			`wb_we_i = 1'b0;`
300			`end`
301			`@ (posedge wb_clk_i) begin`
302			`wb_stb_i = 1'b1;`
303			`wb_cyc_i = 1'b1;`
304			`end`
305			`@ (posedge wb_clk_i) begin`
306			`wb_stb_i = 1'b0;`
307			`wb_cyc_i = 1'b0;`
308			`end`
309			`end`
310			`endtask`
311
312			`endmodule`