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[/] [wiegand_ctl/] [trunk/] [sim/] [work/] [testcase_1/] [_primary.vhd] - Blame information for rev 16

Line No.	Rev	Author	Line
1	16	jeaander	`library verilog;`
2			`use verilog.vl_types.all;`
3			`entity testcase_1 is`
4			`end testcase_1;`