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[/] [wiegand_ctl/] [trunk/] [syn/] [altera/] [wiegand_tx/] [output_files/] [wiegand_tx_top.eda.rpt] - Blame information for rev 17

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Line No. Rev Author Line
1 17 jeaander 
EDA Netlist Writer report for wiegand_tx_top
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Mon Feb 16 11:00:08 2015
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Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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  1. Legal Notice
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  2. EDA Netlist Writer Summary
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  3. Simulation Settings
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  4. Simulation Generated Files
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  5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
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the Altera MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors.  Please refer to the applicable
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agreement for further details.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary                                        ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Mon Feb 16 11:00:08 2015 ;
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; Revision Name             ; wiegand_tx_top                        ;
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; Top-level Entity Name     ; wiegand_tx_top                        ;
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; Family                    ; Cyclone IV GX                         ;
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; Simulation Files Creation ; Successful                            ;
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+---------------------------+---------------------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings                                                                                                           ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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; Option                                                                                            ; Setting                   ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
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; Generate netlist for functional simulation only                                                   ; Off                       ;
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; Time scale                                                                                        ; 1 ps                      ;
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; Truncate long hierarchy paths                                                                     ; Off                       ;
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; Map illegal HDL characters                                                                        ; Off                       ;
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; Flatten buses into individual nodes                                                               ; Off                       ;
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; Maintain hierarchy                                                                                ; Off                       ;
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; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
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; Enable glitch filtering                                                                           ; Off                       ;
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; Do not write top level VHDL entity                                                                ; Off                       ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
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; Architecture name in VHDL output netlist                                                          ; structure                 ;
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; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
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; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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+----------------------------------------------------------------------------------------------------------------------------+
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; Simulation Generated Files                                                                                                 ;
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+----------------------------------------------------------------------------------------------------------------------------+
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; Generated Files                                                                                                            ;
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+----------------------------------------------------------------------------------------------------------------------------+
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_85c_slow.vo     ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_0c_slow.vo      ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_min_1200mv_0c_fast.vo    ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top.vo                       ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_85c_v_slow.sdo  ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_0c_v_slow.sdo   ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_min_1200mv_0c_v_fast.sdo ;
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; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_v.sdo                    ;
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+----------------------------------------------------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus II 64-Bit EDA Netlist Writer
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    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
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    Info: Processing started: Mon Feb 16 11:00:06 2015
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_top
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Info (204019): Generated file wiegand_tx_top_6_1200mv_85c_slow.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top_6_1200mv_0c_slow.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top_min_1200mv_0c_fast.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top_6_1200mv_85c_v_slow.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top_6_1200mv_0c_v_slow.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top_min_1200mv_0c_v_fast.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file wiegand_tx_top_v.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation tool
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Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
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    Info: Peak virtual memory: 511 megabytes
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    Info: Processing ended: Mon Feb 16 11:00:08 2015
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    Info: Elapsed time: 00:00:02
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    Info: Total CPU time (on all processors): 00:00:02
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