Subversion Repositories wiegand_ctl

****** PlanAhead v14.7 (64-bit)

  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013

    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAhead

INFO: [Common 17-290] Got license for PlanAhead

INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml

Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]

Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]

start_gui

source C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top/pa.fromNetlist.tcl

# create_project -name wiegand_tx_top -dir "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top/planAhead_run_1" -part xc3s700anfgg484-4

# set_property design_mode GateLvl [get_property srcset [current_run -impl]]

# set_property edif_top_file "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top/wiegand_tx_top.ngc" [ get_property srcset [ current_run ] ]

# add_files -norecurse { {C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top} }

# set_param project.pinAheadLayout  yes

# set_property target_constrs_file "wiegand_tx_top.ucf" [current_fileset -constrset]

Adding file 'C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top/wiegand_tx_top.ucf' to fileset 'constrs_1'

# add_files [list {wiegand_tx_top.ucf}] -fileset [get_property constrset [current_run]]

# link_design

Design is defaulting to srcset: sources_1

Design is defaulting to constrset: constrs_1

Design is defaulting to project part: xc3s700anfgg484-4

Release 14.7 - ngc2edif P.20131013 (nt64)

Reading design wiegand_tx_top.ngc ...

   ignored.

   Preping design's networks ...

  finished :Prep

ngc2edif: Total memory usage is 80076 kilobytes

Parsing EDIF File [./planAhead_run_1/wiegand_tx_top.data/cache/wiegand_tx_top_ngc_zx.edif]

INFO: [Designutils 20-910] Reading macro library C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/hd_int_macros.edn

Finished Parsing EDIF File [C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/hd_int_macros.edn]

Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/ClockBuffers.xml

Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/IOStandards.xml

INFO: [Timing 38-34] Done reading timing library C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/spartan3a-4.lib.

Parsing UCF File [C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top/wiegand_tx_top.ucf]

Finished Parsing UCF File [C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/ise/wiegand_tx_top/wiegand_tx_top.ucf]

INFO: [Project 1-111] Unisim Transformation Summary:

No Unisim elements were transformed.

Phase 0 | Netlist Checksum: 35859b22

link_design: Time (s): elapsed = 00:00:11 . Memory (MB): peak = 565.117 ; gain = 144.438

startgroup

set_property package_pin A2 [get_ports one_o]

endgroup

startgroup

set_property package_pin A3 [get_ports zero_o]

endgroup

save_constraints

exit

ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.

INFO: [Common 17-83] Releasing license: PlanAhead