Subversion Repositories wiegand_ctl

Release 14.7 par P.20131013 (nt64)

Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

JEFFA-PC::  Mon Feb 16 11:08:38 2015

par -w -intstyle ise -ol high -t 1 wiegand_tx_top_map.ncd wiegand_tx_top.ncd

wiegand_tx_top.pcf

Constraints file: wiegand_tx_top.pcf.

Loading device for application Rf_Device from file '3s700a.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.

   "wiegand_tx_top" is an NCD, version 3.2, device xc3s700an, package fgg484, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

Device speed data version:  "PRODUCTION 1.42 2013-10-13".

Design Summary Report:

 Number of External IOBs                          80 out of 372    21%

   Number of External Input IOBs                 43

      Number of External Input IBUFs             43

   Number of External Output IOBs                37

      Number of External Output IOBs             37

        Number of LOCed External Output IOBs      2 out of 37      5%

   Number of External Bidir IOBs                  0

   Number of BUFGMUXs                        1 out of 24      4%

   Number of Slices                        257 out of 5888    4%

      Number of SLICEMs                      0 out of 2944    0%

Overall effort level (-ol):   High

Placer effort level (-pl):    High

Placer cost table entry (-t): 1

Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 2 secs

Finished initial Timing Analysis.  REAL time: 2 secs

Starting Placer

Total REAL time at the beginning of Placer: 2 secs

Total CPU  time at the beginning of Placer: 2 secs

Phase 1.1  Initial Placement Analysis

Phase 1.1  Initial Placement Analysis (Checksum:6abb9d7) REAL time: 2 secs

Phase 2.7  Design Feasibility Check

INFO:Place:834 - Only a subset of IOs are locked. Out of 37 IOs, 2 are locked and 35 are not locked. If you would like

   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.

Phase 2.7  Design Feasibility Check (Checksum:6abb9d7) REAL time: 3 secs

Phase 3.31  Local Placement Optimization

Phase 3.31  Local Placement Optimization (Checksum:6abb9d7) REAL time: 3 secs

Phase 4.2  Initial Clock and IO Placement

.....

Phase 4.2  Initial Clock and IO Placement (Checksum:48ff9b0d) REAL time: 5 secs

Phase 5.30  Global Clock Region Assignment

Phase 5.30  Global Clock Region Assignment (Checksum:48ff9b0d) REAL time: 5 secs

Phase 6.36  Local Placement Optimization

Phase 6.36  Local Placement Optimization (Checksum:48ff9b0d) REAL time: 5 secs

Phase 7.3  Local Placement Optimization

.....

Phase 7.3  Local Placement Optimization (Checksum:52b13a2d) REAL time: 7 secs

Phase 8.5  Local Placement Optimization

Phase 8.5  Local Placement Optimization (Checksum:52b13a2d) REAL time: 7 secs

Phase 9.8  Global Placement

...............................

.........................

.............................

................

..............

Phase 9.8  Global Placement (Checksum:74ecfc9) REAL time: 7 secs

Phase 10.5  Local Placement Optimization

Phase 10.5  Local Placement Optimization (Checksum:74ecfc9) REAL time: 7 secs

Phase 11.18  Placement Optimization

Phase 11.18  Placement Optimization (Checksum:6048e613) REAL time: 9 secs

Phase 12.5  Local Placement Optimization

Phase 12.5  Local Placement Optimization (Checksum:6048e613) REAL time: 9 secs

Total REAL time to Placer completion: 9 secs

Total CPU  time to Placer completion: 9 secs

Writing design to file wiegand_tx_top.ncd

Starting Router

Phase  1  : 1954 unrouted;      REAL time: 14 secs

Phase  2  : 1763 unrouted;      REAL time: 14 secs

Phase  3  : 433 unrouted;      REAL time: 14 secs

Phase  4  : 433 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 15 secs

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 15 secs

Updating file: wiegand_tx_top.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 15 secs

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 15 secs

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 15 secs

Total REAL time to Router completion: 15 secs

Total CPU time to Router completion: 15 secs

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|      wb_clk_i_BUFGP |  BUFGMUX_X1Y0| No   |  190 |  0.178     |  1.153      |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing

                                            |             |    Slack   | Achievable | Errors |    Score

----------------------------------------------------------------------------------------------------------

  TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 2 | SETUP       |     1.742ns|    16.516ns|       0|           0

----------------------------------------------------------------------------------------------------------

All constraints were met.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 16 secs

Total CPU time to PAR completion: 16 secs

Peak Memory Usage:  373 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Timing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 0

Number of info messages: 1

Writing design to file wiegand_tx_top.ncd

PAR done!