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jeaander |
Release 14.7 par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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JEFFA-PC:: Mon Feb 16 11:08:38 2015
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par -w -intstyle ise -ol high -t 1 wiegand_tx_top_map.ncd wiegand_tx_top.ncd
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wiegand_tx_top.pcf
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Constraints file: wiegand_tx_top.pcf.
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Loading device for application Rf_Device from file '3s700a.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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"wiegand_tx_top" is an NCD, version 3.2, device xc3s700an, package fgg484, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.42 2013-10-13".
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Design Summary Report:
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Number of External IOBs 80 out of 372 21%
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Number of External Input IOBs 43
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Number of External Input IBUFs 43
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Number of External Output IOBs 37
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Number of External Output IOBs 37
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Number of LOCed External Output IOBs 2 out of 37 5%
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Number of External Bidir IOBs 0
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Number of BUFGMUXs 1 out of 24 4%
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Number of Slices 257 out of 5888 4%
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Number of SLICEMs 0 out of 2944 0%
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Overall effort level (-ol): High
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 2 secs
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Finished initial Timing Analysis. REAL time: 2 secs
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Starting Placer
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Total REAL time at the beginning of Placer: 2 secs
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Total CPU time at the beginning of Placer: 2 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:6abb9d7) REAL time: 2 secs
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Phase 2.7 Design Feasibility Check
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INFO:Place:834 - Only a subset of IOs are locked. Out of 37 IOs, 2 are locked and 35 are not locked. If you would like
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to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
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Phase 2.7 Design Feasibility Check (Checksum:6abb9d7) REAL time: 3 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:6abb9d7) REAL time: 3 secs
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Phase 4.2 Initial Clock and IO Placement
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.....
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Phase 4.2 Initial Clock and IO Placement (Checksum:48ff9b0d) REAL time: 5 secs
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Phase 5.30 Global Clock Region Assignment
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Phase 5.30 Global Clock Region Assignment (Checksum:48ff9b0d) REAL time: 5 secs
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Phase 6.36 Local Placement Optimization
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Phase 6.36 Local Placement Optimization (Checksum:48ff9b0d) REAL time: 5 secs
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Phase 7.3 Local Placement Optimization
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.....
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Phase 7.3 Local Placement Optimization (Checksum:52b13a2d) REAL time: 7 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:52b13a2d) REAL time: 7 secs
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Phase 9.8 Global Placement
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...............................
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.........................
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.............................
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................
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..............
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Phase 9.8 Global Placement (Checksum:74ecfc9) REAL time: 7 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:74ecfc9) REAL time: 7 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:6048e613) REAL time: 9 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:6048e613) REAL time: 9 secs
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Total REAL time to Placer completion: 9 secs
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Total CPU time to Placer completion: 9 secs
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Writing design to file wiegand_tx_top.ncd
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Starting Router
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Phase 1 : 1954 unrouted; REAL time: 14 secs
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Phase 2 : 1763 unrouted; REAL time: 14 secs
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Phase 3 : 433 unrouted; REAL time: 14 secs
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Phase 4 : 433 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 15 secs
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Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 15 secs
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Updating file: wiegand_tx_top.ncd with current fully routed design.
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Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 15 secs
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Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 15 secs
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Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 15 secs
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Total REAL time to Router completion: 15 secs
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Total CPU time to Router completion: 15 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| wb_clk_i_BUFGP | BUFGMUX_X1Y0| No | 190 | 0.178 | 1.153 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 2 | SETUP | 1.742ns| 16.516ns| 0| 0
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 16 secs
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Total CPU time to PAR completion: 16 secs
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Peak Memory Usage: 373 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 1
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Writing design to file wiegand_tx_top.ncd
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PAR done!
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