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jeaander |
Release 14.7 Map P.20131013 (nt64)
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Xilinx Map Application Log File for Design 'wiegand_tx_top'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc3s700an-fgg484-4 -cm area -ir off -pr
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off -c 100 -o wiegand_tx_top_map.ncd wiegand_tx_top.ngd wiegand_tx_top.pcf
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Target Device : xc3s700an
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Target Package : fgg484
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Target Speed : -4
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Mapper Version : spartan3a -- $Revision: 1.55 $
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Mapped Date : Mon Feb 16 11:08:32 2015
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Running related packing...
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Updating timing models...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 0
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Logic Utilization:
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Number of Slice Flip Flops: 318 out of 11,776 2%
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Number of 4 input LUTs: 305 out of 11,776 2%
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Logic Distribution:
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Number of occupied Slices: 257 out of 5,888 4%
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Number of Slices containing only related logic: 257 out of 257 100%
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Number of Slices containing unrelated logic: 0 out of 257 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Total Number of 4 input LUTs: 305 out of 11,776 2%
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Number of bonded IOBs: 80 out of 372 21%
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Number of BUFGMUXs: 1 out of 24 4%
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Average Fanout of Non-Clock Nets: 3.79
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Peak Memory Usage: 346 MB
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Total REAL time to MAP completion: 3 secs
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Total CPU time to MAP completion: 2 secs
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Mapping completed.
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See MAP report file "wiegand_tx_top_map.mrp" for details.
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