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jeaander |
Release 14.7 Map P.20131013 (nt64)
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Xilinx Mapping Report File for Design 'wiegand_tx_top'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc3s700an-fgg484-4 -cm area -ir off -pr
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off -c 100 -o wiegand_tx_top_map.ncd wiegand_tx_top.ngd wiegand_tx_top.pcf
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Target Device : xc3s700an
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Target Package : fgg484
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Target Speed : -4
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Mapper Version : spartan3a -- $Revision: 1.55 $
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Mapped Date : Mon Feb 16 11:08:32 2015
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 0
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Logic Utilization:
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Number of Slice Flip Flops: 318 out of 11,776 2%
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Number of 4 input LUTs: 305 out of 11,776 2%
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Logic Distribution:
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Number of occupied Slices: 257 out of 5,888 4%
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Number of Slices containing only related logic: 257 out of 257 100%
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Number of Slices containing unrelated logic: 0 out of 257 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Total Number of 4 input LUTs: 305 out of 11,776 2%
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Number of bonded IOBs: 80 out of 372 21%
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Number of BUFGMUXs: 1 out of 24 4%
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Average Fanout of Non-Clock Nets: 3.79
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Peak Memory Usage: 346 MB
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Total REAL time to MAP completion: 3 secs
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Total CPU time to MAP completion: 2 secs
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Timing Report
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Section 11 - Configuration String Information
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Section 12 - Control Set Information
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Section 13 - Utilization by Hierarchy
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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Section 3 - Informational
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-------------------------
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INFO:LIT:243 - Logical network wb_cti_i<2> has no load.
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INFO:LIT:395 - The above info message is repeated 6 more times for the following
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(max. 5 shown):
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wb_cti_i<1>,
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wb_cti_i<0>,
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wb_sel_i<3>,
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wb_sel_i<2>,
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wb_sel_i<1>
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To see the details of these info messages, please use the -detail switch.
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INFO:MapLib:562 - No environment variables are currently set.
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs.
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Section 4 - Removed Logic Summary
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---------------------------------
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2 block(s) optimized away
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Section 5 - Removed Logic
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-------------------------
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND |
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| | | | | Term | Strength | Rate | | | Delay | |
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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| one_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_ack_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_adr_i<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_adr_i<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_adr_i<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_adr_i<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_adr_i<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_adr_i<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_clk_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_cyc_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<8> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<9> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<10> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<11> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<12> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<13> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<14> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<15> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<16> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<17> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<18> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<19> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<20> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<21> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<22> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<23> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<24> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<25> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<26> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<27> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<28> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<29> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<30> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_i<31> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_dat_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<24> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<25> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<26> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<27> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<28> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<29> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<30> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_dat_o<31> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_err_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_rst_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_rty_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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| wb_stb_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| wb_we_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| zero_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Timing Report
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--------------------------
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This design was not run using timing mode.
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Section 11 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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Section 12 - Control Set Information
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------------------------------------
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No control set information for this architecture.
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Section 13 - Utilization by Hierarchy
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-------------------------------------
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Use the "-detail" map option to print out the Utilization by Hierarchy section.
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