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Subversion Repositories wisbone_2_ahb

[/] [wisbone_2_ahb/] [branches/] [toomuch/] [svtb/] [avm_svtb/] [wb_ahb_stim_gen.svh] - Blame information for rev 11

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//******************************************************************************************************
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// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
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//File name             :       wb_ahb_stim_gen.svh
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//Designaer             :       Ravi S Gupta
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//Date                  :       4 Sept, 2007
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//Description           :       Stimulus Generation for WISHBONE_AHB Bridge
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//Revision              :       1.0
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//******************************************************************************************************
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// class to generate write and read packet
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import avm_pkg::*;
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import global::*;
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class wb_ahb_stim_gen extends avm_named_component;
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avm_blocking_put_port#( wb_req_pkt) initiator_port;
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tlm_fifo#(wb_req_pkt) fifo;
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        function new(string name ,avm_named_component parent);
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                super.new(name,parent);
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                initiator_port=new("initiatot_port",this);
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                fifo =new("fifo",this);
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        endfunction
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task stimulus(input int count = 41);
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        wb_req_pkt p;
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//*****************************************
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//Write operations with no wait states
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//*****************************************
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                for(int i=0; i<11 ;i++)
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                begin
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                                p.wr='b1;
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                                p.adr=i+1;
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                                p.dat=i;
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                                p.stb='b1;
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                                write_to_pipe(p);
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                end
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//************************************************
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//Write operations with wait states from AHB Slave
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//************************************************
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                for(int i=10;i<16;i++)
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                begin
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                                p.wr='b1;//Wait state from AHB SLAVE
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                                p.stb='b1;
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                                write_to_pipe(p);
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                end
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//*****************************************
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//Write operations with no wait states
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//*****************************************
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                for(int i=15; i<21 ;i++)
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                begin
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                                p.wr='b1;
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                                p.adr=i+1;
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                                p.dat=i;
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                                p.stb='b1;
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                                write_to_pipe(p);
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                end
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//***********************************************
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//Write operations with wait states from WB Master
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//***********************************************
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                for(int i=20;i<26;i++)
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                begin
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                                p.stb='b0;
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                                p.wr='b1;//Wait state from AHB SLAVE
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                write_to_pipe(p);
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                end
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//*****************************************
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//Write operations with no wait states
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//*****************************************
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                for(int i=25; i<31 ;i++)
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                begin
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                                p.wr='b1;
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                                p.adr=i+1;
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                                p.dat=i;
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                                p.stb='b1;
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                                write_to_pipe(p);
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                end
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//*************************************
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//Read operations without wait states
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//*************************************
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                for(int i=30; i<41 ;i++)
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                begin
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                                p.wr='b0;
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                                p.adr=i+1;
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                                p.stb='b1;
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                                write_to_pipe(p);
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                end
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//**********************************************
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//Read operations with wait states from AHB Slave
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//**********************************************
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                for(int i=40; i<51 ;i++)
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                begin
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                                p.wr='b0;
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                                p.stb='b1;
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                                write_to_pipe(p);
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                end
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//*************************************
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//Read operations without wait states
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//*************************************
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                for(int i=50; i<61 ;i++)
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                begin
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                                p.wr='b0;
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                                p.stb='b1;
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                                p.adr=i+1;
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                                write_to_pipe(p);
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                end
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//**********************************************
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//Read operations with wait states from WB Master
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//**********************************************
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                for(int i=60; i<71 ;i++)
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                begin
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                                p.wr='b0;
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                                p.stb='b0;
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                                write_to_pipe(p);
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                end
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//*************************************
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//Read operations without wait states
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//*************************************
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                for(int i=70; i<81 ;i++)
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                begin
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                                p.wr='b0;
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                                p.stb='b1;
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                                p.adr=i+1;
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                                write_to_pipe(p);
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                end
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//*****************************************
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//Write operations with no wait states
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//*****************************************
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                for(int i=80; i<91 ;i++)
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                begin
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                                p.wr='b1;
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                                p.stb='b1;
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                                p.adr=i+1;
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                                p.dat=i;
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                                write_to_pipe(p);
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                end
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endtask
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// task to push transaction in the fifo
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task write_to_pipe(wb_req_pkt p);
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                initiator_port.put(p);
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endtask
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endclass

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