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[/] [wisbone_2_ahb/] [tags/] [t3/] [svtb/] [avm_svtb/] [wb_ahb_responder.svh] - Blame information for rev 11

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//******************************************************************************************************
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
 
 
//File name             :       wb_ahb_responder.svh
//Designer              :       Ravi S Gupta
//Date                  :       4 Sept, 2007
//Description           :       Response from AHB to the Inputs from Wishbone
//Revision              :       1.0
 
//******************************************************************************************************
 
 
// responder class
import avm_pkg::*;
import global::*;
class wb_ahb_responder extends avm_threaded_component;
 
int cnt;
// local memory in AHB slave model
logic [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
 
logic [AWIDTH-1:0] haddr_temp;
logic [DWIDTH-1 :0] hrdata_temp;
logic hwrite_temp;
 
virtual wb_ahb_if pin_if;
 
        function new(string name ,avm_named_component parent);
                super.new(name,parent);
                pin_if   =null;
        endfunction
 
// task to sample address
task samp_addr;
        forever
                begin
                @(posedge pin_if.master_wb.clk_i);
                                if(pin_if.master_wb.rst_i)
                                        begin
                                        pin_if.slave_ba.hready='b0;
                                        pin_if.slave_ba.hwdata='bx;
                                        pin_if.slave_ba.hresp='b00;
 
                                        end
                                else if(!pin_if.slave_ba.hwrite)
                                        begin
                                        pin_if.slave_ba.hrdata= #2 pin_if.slave_ba.haddr+1;
                                        end
                end
endtask
 
 
task response;
        forever
        begin
        @(posedge pin_if.master_wb.clk_i);
        end
endtask
 
//*****************************************
//Write operations with no wait states
//*****************************************
task wait_state_by_slave;
        pin_if.slave_ba.hready='b1;
                do
                        begin
                        @(posedge pin_if.master_wb.clk_i);
                        cnt++;
                        end
                while (cnt <= 9);//Write operations with no wait states for 10 clk cycles
//************************************************
//Write operations with wait states from AHB Slave
//************************************************
        #2 pin_if.slave_ba.hready='b0;
        cnt=0;
                do
                        begin
                        @(posedge pin_if.master_wb.clk_i);
                        ++cnt;
                        end
                while (cnt <= 4);// 5 clock cycle asserted AHB Master is in Wait State
//*****************************************
//Write operations with no wait states
//*****************************************
        #2 pin_if.slave_ba.hready='b1;
        cnt=0;
                do
                        begin
                        @(posedge pin_if.master_wb.clk_i);
                        cnt++;
                        end
                while (cnt <= 4);//Write operations with no wait states for 5 clk cycles
//***********************************************
//Write operations with wait states from WB Master
//***********************************************
         #2 pin_if.slave_ba.hready='b1;
        cnt=0;
                do
                        begin
                        @(posedge pin_if.master_wb.clk_i);
                        ++cnt;
                        end
                while (cnt <= 4);// 5 clock cycle deasserted WB Master is in Wait State
//*****************************************
//Write operations with no wait states
//*****************************************
        #2 pin_if.slave_ba.hready='b1;
        cnt=0;
                do
                        begin
                        @(posedge pin_if.master_wb.clk_i);
                        cnt++;
                        end
                while (cnt <= 4);//Write operations with no wait states for 5 clk cycles
 
//*************************************
//Read operations without wait states
//*************************************
        #2 pin_if.slave_ba.hready='b1;
        cnt=0;
                do
                        begin
                                @(posedge pin_if.master_wb.clk_i);
                        cnt++;
                        end
        while (cnt <= 9);// Read operations with no wait states for 10 clk cycles
 
//**********************************************
//Read operations with wait states from AHB Slave
//**********************************************
        #2 pin_if.slave_ba.hready='b0;
        cnt=0;
                do
                        begin
                                @(posedge pin_if.master_wb.clk_i);
                        ++cnt;
                        end
        while (cnt <= 9);// 10 clock cycle asserted AHB Master is in Wait State
 
//*************************************
//Read operations without wait states
//*************************************
        #2 pin_if.slave_ba.hready='b1;
        cnt=0;
                do
                        begin
                                @(posedge pin_if.master_wb.clk_i);
                        cnt++;
                        end
        while (cnt <= 9);// Read operations with no wait states for 10 clk cycles
//**********************************************
//Read operations with wait states from WB Master
//**********************************************
        #2 pin_if.slave_ba.hready='b1;
        cnt=0;
                do
                        begin
                                @(posedge pin_if.master_wb.clk_i);
                        ++cnt;
                        end
                while (cnt <= 9);// 10 clock cycle  asserted WB Master in in Wait state
 
endtask
// run all task
task run;
        fork
        samp_addr;
        response;
        join
endtask
 
endclass

Line No.	Rev	Author	Line
1	5	toomuch	`//******************************************************************************************************`
2			`// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.`
3
4
5			`//File name : wb_ahb_responder.svh`
6	8	toomuch	`//Designer : Ravi S Gupta`
7			`//Date : 4 Sept, 2007`
8	5	toomuch	`//Description : Response from AHB to the Inputs from Wishbone`
9			`//Revision : 1.0`
10
11			`//******************************************************************************************************`
12
13
14			`// responder class`
15			`import avm_pkg::*;`
16			`import global::*;`
17			`class wb_ahb_responder extends avm_threaded_component;`
18
19			`int cnt;`
20	8	toomuch	`// local memory in AHB slave model`
21			`logic [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];`
22
23			`logic [AWIDTH-1:0] haddr_temp;`
24			`logic [DWIDTH-1 :0] hrdata_temp;`
25			`logic hwrite_temp;`
26
27	5	toomuch	`virtual wb_ahb_if pin_if;`
28
29			`function new(string name ,avm_named_component parent);`
30			`super.new(name,parent);`
31			`pin_if =null;`
32			`endfunction`
33
34	8	toomuch	`// task to sample address`
35			`task samp_addr;`
36			`forever`
37			`begin`
38			`@(posedge pin_if.master_wb.clk_i);`
39	5	toomuch	`if(pin_if.master_wb.rst_i)`
40			`begin`
41			`pin_if.slave_ba.hready='b0;`
42			`pin_if.slave_ba.hwdata='bx;`
43			`pin_if.slave_ba.hresp='b00;`
44	8	toomuch
45	5	toomuch	`end`
46	8	toomuch	`else if(!pin_if.slave_ba.hwrite)`
47	5	toomuch	`begin`
48	8	toomuch	`pin_if.slave_ba.hrdata= #2 pin_if.slave_ba.haddr+1;`
49	5	toomuch	`end`
50			`end`
51			`endtask`
52
53	8	toomuch
54			`task response;`
55			`forever`
56			`begin`
57			`@(posedge pin_if.master_wb.clk_i);`
58			`end`
59			`endtask`
60
61	5	toomuch	`//*****************************************`
62			`//Write operations with no wait states`
63			`//*****************************************`
64			`task wait_state_by_slave;`
65			`pin_if.slave_ba.hready='b1;`
66			`do`
67			`begin`
68			`@(posedge pin_if.master_wb.clk_i);`
69			`cnt++;`
70			`end`
71	8	toomuch	`while (cnt <= 9);//Write operations with no wait states for 10 clk cycles`
72	5	toomuch	`//************************************************`
73			`//Write operations with wait states from AHB Slave`
74			`//************************************************`
75			`#2 pin_if.slave_ba.hready='b0;`
76			`cnt=0;`
77			`do`
78			`begin`
79			`@(posedge pin_if.master_wb.clk_i);`
80			`++cnt;`
81			`end`
82	8	toomuch	`while (cnt <= 4);// 5 clock cycle asserted AHB Master is in Wait State`
83	5	toomuch	`//*****************************************`
84			`//Write operations with no wait states`
85			`//*****************************************`
86			`#2 pin_if.slave_ba.hready='b1;`
87			`cnt=0;`
88			`do`
89			`begin`
90			`@(posedge pin_if.master_wb.clk_i);`
91			`cnt++;`
92			`end`
93	8	toomuch	`while (cnt <= 4);//Write operations with no wait states for 5 clk cycles`
94	5	toomuch	`//***********************************************`
95			`//Write operations with wait states from WB Master`
96			`//***********************************************`
97			`#2 pin_if.slave_ba.hready='b1;`
98			`cnt=0;`
99			`do`
100			`begin`
101			`@(posedge pin_if.master_wb.clk_i);`
102			`++cnt;`
103			`end`
104	8	toomuch	`while (cnt <= 4);// 5 clock cycle deasserted WB Master is in Wait State`
105	5	toomuch	`//*****************************************`
106			`//Write operations with no wait states`
107			`//*****************************************`
108			`#2 pin_if.slave_ba.hready='b1;`
109			`cnt=0;`
110			`do`
111			`begin`
112			`@(posedge pin_if.master_wb.clk_i);`
113			`cnt++;`
114			`end`
115	8	toomuch	`while (cnt <= 4);//Write operations with no wait states for 5 clk cycles`
116	5	toomuch
117			`//*************************************`
118			`//Read operations without wait states`
119			`//*************************************`
120			`#2 pin_if.slave_ba.hready='b1;`
121			`cnt=0;`
122			`do`
123			`begin`
124			`@(posedge pin_if.master_wb.clk_i);`
125			`cnt++;`
126			`end`
127	8	toomuch	`while (cnt <= 9);// Read operations with no wait states for 10 clk cycles`
128	5	toomuch
129			`//**********************************************`
130			`//Read operations with wait states from AHB Slave`
131			`//**********************************************`
132	8	toomuch	`#2 pin_if.slave_ba.hready='b0;`
133	5	toomuch	`cnt=0;`
134			`do`
135			`begin`
136			`@(posedge pin_if.master_wb.clk_i);`
137			`++cnt;`
138			`end`
139	8	toomuch	`while (cnt <= 9);// 10 clock cycle asserted AHB Master is in Wait State`
140	5	toomuch
141			`//*************************************`
142			`//Read operations without wait states`
143			`//*************************************`
144			`#2 pin_if.slave_ba.hready='b1;`
145			`cnt=0;`
146			`do`
147			`begin`
148			`@(posedge pin_if.master_wb.clk_i);`
149			`cnt++;`
150			`end`
151	8	toomuch	`while (cnt <= 9);// Read operations with no wait states for 10 clk cycles`
152	5	toomuch	`//**********************************************`
153			`//Read operations with wait states from WB Master`
154			`//**********************************************`
155	8	toomuch	`#2 pin_if.slave_ba.hready='b1;`
156	5	toomuch	`cnt=0;`
157			`do`
158			`begin`
159			`@(posedge pin_if.master_wb.clk_i);`
160			`++cnt;`
161			`end`
162	8	toomuch	`while (cnt <= 9);// 10 clock cycle asserted WB Master in in Wait state`
163	5	toomuch
164			`endtask`
165	8	toomuch	`// run all task`
166			`task run;`
167			`fork`
168			`samp_addr;`
169			`response;`
170			`join`
171			`endtask`
172	5	toomuch
173			`endclass`

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[/] [wisbone_2_ahb/] [tags/] [t3/] [svtb/] [avm_svtb/] [wb_ahb_responder.svh] - Blame information for rev 11