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[/] [wisbone_2_ahb/] [trunk/] [bench/] [ahbmas_wbslv_top_tb.v] - Blame information for rev 11

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//******************************************************************************************************
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
 
 
//File name             :       ahbmas_wbslv_top_tb.v
//Designer              :       Ravi S Gupta
//Date                  :       23 May, 2007
//Description   :       Wishbone to AHB interface protocol converter Testbench
//Revision              :       1.0
 
 
//******************************************************************************************************
 
//DEFINES
`define DEL 1 //Clock to output delay, zero time delays can cause problems
//TOP MODULE
module AHBMAS_WBSLV_TOP_tb  ;
//PARAMETERS
parameter DWIDTH  = 32 ;
parameter AWIDTH  = 32 ;
parameter TON = 5 ;
parameter TOFF = 5 ;
 
integer  address = 0;
integer data = 0;
//SIGNAL DECLARATIONS
  wire  [1:0]  htrans   ;
  reg    stb_i   ;
  reg  [DWIDTH-1:0]  data_i   ;
  wire    hwrite   ;
  reg  [3:0]  sel_i   ;
  reg  [DWIDTH-1:0]  hrdata   ;
  wire    ack_o   ;
  reg    hready   ;
  wire  [DWIDTH-1:0]  data_o   ;
  wire  [2:0]  hburst   ;
  wire  [31:0]  hwdata   ;
  reg  [1:0]  hresp   ;
  reg  [AWIDTH-1:0]  addr_i   ;
  wire  [AWIDTH-1:0]  haddr   ;
  wire  [2:0]  hsize   ;
  reg    we_i   ;
  reg    cyc_i   ;
  reg    clk_i  ;
  reg    rst_i  ;
  reg   hclk;
  reg   hresetn;
 
//MAIN CODE
//Instantiate the DUT
  AHBMAS_WBSLV_TOP    #( DWIDTH , AWIDTH  )
   DUT  (
       .htrans (htrans ) ,
      .stb_i (stb_i ) ,
      .data_i (data_i ) ,
      .hwrite (hwrite ) ,
      .sel_i (sel_i ) ,
      .hrdata (hrdata ) ,
      .ack_o (ack_o ) ,
      .hready (hready ) ,
      .data_o (data_o ) ,
      .hburst (hburst ) ,
      .hwdata (hwdata ) ,
      .hresp (hresp ) ,
      .addr_i (addr_i ) ,
      .haddr (haddr ) ,
      .hsize (hsize ) ,
      .we_i (we_i ) ,
      .cyc_i (cyc_i ) ,
          .clk_i (clk_i),
          .rst_i (rst_i),
          .hclk (hclk),
          .hresetn(hresetn));
 
// Clock Generation
        always begin
                #TOFF //clk generation with OFF timeperiod = 5
                clk_i = 'b0;
                #TON //clk generation with ON timeperiod = 5
                clk_i = 'b1;
        end
// local memory in AHB slave model
        reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
        reg [AWIDTH-1:0] haddr_temp;
        reg [DWIDTH-1 :0] hrdata_temp;
        reg hwrite_temp;
 
//      always@(posedge clk_i)
//              hrdata <= hrdata_temp;
//*************************************************
// AHB slave model
//*************************************************
 
        always @(posedge clk_i) begin
                if (hready) begin
                        haddr_temp <= #2 haddr;
                        hwrite_temp<=#2 hwrite;
                        if (hwrite_temp) begin
                                ahb_mem[haddr_temp] <= #2 hwdata;                       // data stored in ahb slave
                        end
                        else if (!hwrite) begin
                                hrdata <= #2 ahb_mem[haddr];
                        end
                end
        end
 
//*****************************************
//Write operations with no wait states
//*****************************************
task write_data;
 
                input [AWIDTH-1:0] addr;
                input [DWIDTH-1:0] Data;
                        begin
                        #2
                        cyc_i=1'b1;
                        stb_i=1'b1;
                        we_i=1'b1;
                        //if(ack_o) begin
                        addr_i <= addr;
                        data_i <= Data;//Send Data
                        //end
                        hready <= 'b1;
                        end
endtask
//************************************************
//Write operations with wait states from AHB Slave
//************************************************
task write_data_WSAHB;
                begin
                @(posedge clk_i) begin
                #2 cyc_i = 1'b1;
                stb_i = 1'b1;
                we_i = 1'b1;
                hready = 1'b0;          //AHB Master is in Wait State
                end
        end
 
endtask
 
//***********************************************
//Write operations with wait states from WB Master
//***********************************************
task write_data_WSWB;
                begin
                @(posedge clk_i) begin
                #2 cyc_i = 1'b1;
                stb_i = 1'b0;//WB Master is in Wait State
                we_i = 1'b1;
                hready = 1'b1;
                end
        end
 
endtask
 
//*************************************
//Read operations without wait states
//*************************************
task read_data;
        input [31:0] addr;
        begin #2
                cyc_i=1'b1;
                stb_i=1'b1;
                we_i=1'b0;
                if (ack_o) begin
                        addr_i = addr;
                end
        //      else begin
//                      hrdata_temp = ahb_mem[haddr];
//              end
                hready = 1'b1;
        end
endtask
//**********************************************
//Read operations with wait states from AHB Slave
//**********************************************
task read_data_WSAHB;
begin
                @(posedge clk_i) begin
                #2 cyc_i = 1'b1;
                stb_i = 1'b1;
                we_i = 1'b0;
                hready = 1'b0;          //AHB Master is in Wait State
                end
end
endtask
 
//**********************************************
//Read operations with wait states from WB Master
//**********************************************
task read_data_WSWB;
begin
                @(posedge clk_i) begin
                #2 cyc_i = 1'b1;
                stb_i = 1'b0;           //WB Master in in Wait state
                we_i = 1'b0;
                hready = 1'b1;
                end
end
endtask
 
 
 
// Initialize Inputs
        initial
                begin
                        clk_i=1'b0;
 
                        rst_i = 'b0;
                        #2
                        rst_i = 'b1;
                        #23
                        rst_i = 'b0;                    // reset for more than one clock cycle
 
                        hready = 1'b1;
                        hresp = 2'b00;
                        # 20 cyc_i='b0;
                        stb_i='b0;
                        sel_i=4'b0000;
 
 
//*************************************
//Block Write cycle
//*************************************
                repeat(7) begin
                        address = address + 1;
                        @(posedge clk_i) write_data(address, data);                     // format : write_data(A[n+1], d[n])
                        data = data +1;
                end
//*************************************
//Write cycle with wait states from AHB Slave
//*************************************
        //      #10;
                repeat(2)
                write_data_WSAHB;
//*************************************
//Block Write cycle
//*************************************
        //      #10;
                repeat(4) begin
                        address = address + 1;
                        @(posedge clk_i) write_data(address, data);                     // format : write_data(A[n+1], d[n])
                        data = data +1;
                end
//*************************************
//Write cycle with wait states from WB Master
//*************************************
        //      #10;
                repeat(2)
                write_data_WSWB;
 
//*************************************
//Block Write cycle
//*************************************
        //      #10;
                repeat(4) begin
                        address = address + 1;
                        @(posedge clk_i) write_data(address, data);                     // format : write_data(A[n+1], d[n])
                        data = data +1;
                end
 
//*************************************
//Block Read cycle
//*************************************
        //      #10;
                repeat(6) begin
                        @(posedge clk_i) read_data(address);
                        address = address -1;
                end
 
//*************************************
//Read cycle with Wait State from AHB Slave
//*************************************
        //      #10;
                repeat(2)
                read_data_WSAHB;
 
//*************************************
//Block Read cycle
//*************************************
        //      #10;
                repeat(4) begin
                        @(posedge clk_i) read_data(address);
                        address = address -1;
                end
 
//*************************************
//Read cycle with Wait State from WB Master
//*************************************
        //      #10;
                repeat(2)
                read_data_WSWB;
//*************************************
//Block Read cycle
//*************************************
        //      #10;
                repeat(5) begin
                        address = address + 1;
                        @(posedge clk_i) write_data(address, data);                     // format : write_data(A[n+1], d[n])
                        data = data +1;
                end
 
//*************************************
//Block Write cycle
//*************************************
                repeat(4) begin
                        address = address + 1;
                        @(posedge clk_i) write_data(address, data);                     // format : write_data(A[n+1], d[n])
                        data = data +1;
                end
 
                        #20 stb_i='b0;
                        #5       cyc_i='b0;
 
                #200 $stop;
        end
 
endmodule

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Subversion Repositories wisbone_2_ahb

[/] [wisbone_2_ahb/] [trunk/] [bench/] [ahbmas_wbslv_top_tb.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	2	toomuch	`//******************************************************************************************************`
2			`// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.`
3
4
5			`//File name : ahbmas_wbslv_top_tb.v`
6			`//Designer : Ravi S Gupta`
7			`//Date : 23 May, 2007`
8			`//Description : Wishbone to AHB interface protocol converter Testbench`
9			`//Revision : 1.0`
10
11
12			`//******************************************************************************************************`
13
14			`//DEFINES`
15			`define DEL 1 //Clock to output delay, zero time delays can cause problems
16			`//TOP MODULE`
17			`module AHBMAS_WBSLV_TOP_tb ;`
18			`//PARAMETERS`
19			`parameter DWIDTH = 32 ;`
20			`parameter AWIDTH = 32 ;`
21			`parameter TON = 5 ;`
22			`parameter TOFF = 5 ;`
23
24			`integer address = 0;`
25			`integer data = 0;`
26			`//SIGNAL DECLARATIONS`
27			`wire [1:0] htrans ;`
28			`reg stb_i ;`
29			`reg [DWIDTH-1:0] data_i ;`
30			`wire hwrite ;`
31			`reg [3:0] sel_i ;`
32			`reg [DWIDTH-1:0] hrdata ;`
33			`wire ack_o ;`
34			`reg hready ;`
35			`wire [DWIDTH-1:0] data_o ;`
36			`wire [2:0] hburst ;`
37			`wire [31:0] hwdata ;`
38			`reg [1:0] hresp ;`
39			`reg [AWIDTH-1:0] addr_i ;`
40			`wire [AWIDTH-1:0] haddr ;`
41			`wire [2:0] hsize ;`
42			`reg we_i ;`
43			`reg cyc_i ;`
44			`reg clk_i ;`
45			`reg rst_i ;`
46			`reg hclk;`
47			`reg hresetn;`
48
49			`//MAIN CODE`
50			`//Instantiate the DUT`
51			`AHBMAS_WBSLV_TOP #( DWIDTH , AWIDTH )`
52			`DUT (`
53			`.htrans (htrans ) ,`
54			`.stb_i (stb_i ) ,`
55			`.data_i (data_i ) ,`
56			`.hwrite (hwrite ) ,`
57			`.sel_i (sel_i ) ,`
58			`.hrdata (hrdata ) ,`
59			`.ack_o (ack_o ) ,`
60			`.hready (hready ) ,`
61			`.data_o (data_o ) ,`
62			`.hburst (hburst ) ,`
63			`.hwdata (hwdata ) ,`
64			`.hresp (hresp ) ,`
65			`.addr_i (addr_i ) ,`
66			`.haddr (haddr ) ,`
67			`.hsize (hsize ) ,`
68			`.we_i (we_i ) ,`
69			`.cyc_i (cyc_i ) ,`
70			`.clk_i (clk_i),`
71			`.rst_i (rst_i),`
72			`.hclk (hclk),`
73			`.hresetn(hresetn));`
74
75			`// Clock Generation`
76			`always begin`
77			`#TOFF //clk generation with OFF timeperiod = 5`
78			`clk_i = 'b0;`
79			`#TON //clk generation with ON timeperiod = 5`
80			`clk_i = 'b1;`
81			`end`
82			`// local memory in AHB slave model`
83			`reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];`
84			`reg [AWIDTH-1:0] haddr_temp;`
85			`reg [DWIDTH-1 :0] hrdata_temp;`
86			`reg hwrite_temp;`
87
88			`// always@(posedge clk_i)`
89			`// hrdata <= hrdata_temp;`
90			`//*************************************************`
91			`// AHB slave model`
92			`//*************************************************`
93
94			`always @(posedge clk_i) begin`
95			`if (hready) begin`
96			`haddr_temp <= #2 haddr;`
97			`hwrite_temp<=#2 hwrite;`
98			`if (hwrite_temp) begin`
99			`ahb_mem[haddr_temp] <= #2 hwdata; // data stored in ahb slave`
100			`end`
101			`else if (!hwrite) begin`
102			`hrdata <= #2 ahb_mem[haddr];`
103			`end`
104			`end`
105			`end`
106
107			`//*****************************************`
108			`//Write operations with no wait states`
109			`//*****************************************`
110			`task write_data;`
111
112			`input [AWIDTH-1:0] addr;`
113			`input [DWIDTH-1:0] Data;`
114			`begin`
115			`#2`
116			`cyc_i=1'b1;`
117			`stb_i=1'b1;`
118			`we_i=1'b1;`
119			`//if(ack_o) begin`
120			`addr_i <= addr;`
121			`data_i <= Data;//Send Data`
122			`//end`
123			`hready <= 'b1;`
124			`end`
125			`endtask`
126			`//************************************************`
127			`//Write operations with wait states from AHB Slave`
128			`//************************************************`
129			`task write_data_WSAHB;`
130			`begin`
131			`@(posedge clk_i) begin`
132			`#2 cyc_i = 1'b1;`
133			`stb_i = 1'b1;`
134			`we_i = 1'b1;`
135			`hready = 1'b0; //AHB Master is in Wait State`
136			`end`
137			`end`
138
139			`endtask`
140
141			`//***********************************************`
142			`//Write operations with wait states from WB Master`
143			`//***********************************************`
144			`task write_data_WSWB;`
145			`begin`
146			`@(posedge clk_i) begin`
147			`#2 cyc_i = 1'b1;`
148			`stb_i = 1'b0;//WB Master is in Wait State`
149			`we_i = 1'b1;`
150			`hready = 1'b1;`
151			`end`
152			`end`
153
154			`endtask`
155
156			`//*************************************`
157			`//Read operations without wait states`
158			`//*************************************`
159			`task read_data;`
160			`input [31:0] addr;`
161			`begin #2`
162			`cyc_i=1'b1;`
163			`stb_i=1'b1;`
164			`we_i=1'b0;`
165			`if (ack_o) begin`
166			`addr_i = addr;`
167			`end`
168			`// else begin`
169			`// hrdata_temp = ahb_mem[haddr];`
170			`// end`
171			`hready = 1'b1;`
172			`end`
173			`endtask`
174			`//**********************************************`
175			`//Read operations with wait states from AHB Slave`
176			`//**********************************************`
177			`task read_data_WSAHB;`
178			`begin`
179			`@(posedge clk_i) begin`
180			`#2 cyc_i = 1'b1;`
181			`stb_i = 1'b1;`
182			`we_i = 1'b0;`
183			`hready = 1'b0; //AHB Master is in Wait State`
184			`end`
185			`end`
186			`endtask`
187
188			`//**********************************************`
189			`//Read operations with wait states from WB Master`
190			`//**********************************************`
191			`task read_data_WSWB;`
192			`begin`
193			`@(posedge clk_i) begin`
194			`#2 cyc_i = 1'b1;`
195			`stb_i = 1'b0; //WB Master in in Wait state`
196			`we_i = 1'b0;`
197			`hready = 1'b1;`
198			`end`
199			`end`
200			`endtask`
201
202
203
204			`// Initialize Inputs`
205			`initial`
206			`begin`
207			`clk_i=1'b0;`
208
209			`rst_i = 'b0;`
210			`#2`
211			`rst_i = 'b1;`
212			`#23`
213			`rst_i = 'b0; // reset for more than one clock cycle`
214
215			`hready = 1'b1;`
216			`hresp = 2'b00;`
217			`# 20 cyc_i='b0;`
218			`stb_i='b0;`
219			`sel_i=4'b0000;`
220
221
222			`//*************************************`
223			`//Block Write cycle`
224			`//*************************************`
225			`repeat(7) begin`
226			`address = address + 1;`
227			`@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])`
228			`data = data +1;`
229			`end`
230			`//*************************************`
231			`//Write cycle with wait states from AHB Slave`
232			`//*************************************`
233			`// #10;`
234			`repeat(2)`
235			`write_data_WSAHB;`
236			`//*************************************`
237			`//Block Write cycle`
238			`//*************************************`
239			`// #10;`
240			`repeat(4) begin`
241			`address = address + 1;`
242			`@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])`
243			`data = data +1;`
244			`end`
245			`//*************************************`
246			`//Write cycle with wait states from WB Master`
247			`//*************************************`
248			`// #10;`
249			`repeat(2)`
250			`write_data_WSWB;`
251
252			`//*************************************`
253			`//Block Write cycle`
254			`//*************************************`
255			`// #10;`
256			`repeat(4) begin`
257			`address = address + 1;`
258			`@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])`
259			`data = data +1;`
260			`end`
261
262			`//*************************************`
263			`//Block Read cycle`
264			`//*************************************`
265			`// #10;`
266			`repeat(6) begin`
267			`@(posedge clk_i) read_data(address);`
268			`address = address -1;`
269			`end`
270
271			`//*************************************`
272			`//Read cycle with Wait State from AHB Slave`
273			`//*************************************`
274			`// #10;`
275			`repeat(2)`
276			`read_data_WSAHB;`
277
278			`//*************************************`
279			`//Block Read cycle`
280			`//*************************************`
281			`// #10;`
282			`repeat(4) begin`
283			`@(posedge clk_i) read_data(address);`
284			`address = address -1;`
285			`end`
286
287			`//*************************************`
288			`//Read cycle with Wait State from WB Master`
289			`//*************************************`
290			`// #10;`
291			`repeat(2)`
292			`read_data_WSWB;`
293			`//*************************************`
294			`//Block Read cycle`
295			`//*************************************`
296			`// #10;`
297			`repeat(5) begin`
298			`address = address + 1;`
299			`@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])`
300			`data = data +1;`
301			`end`
302
303			`//*************************************`
304			`//Block Write cycle`
305			`//*************************************`
306			`repeat(4) begin`
307			`address = address + 1;`
308			`@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])`
309			`data = data +1;`
310			`end`
311
312			`#20 stb_i='b0;`
313			`#5 cyc_i='b0;`
314
315			`#200 $stop;`
316			`end`
317
318			`endmodule`