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[/] [wishbone_bfm/] [trunk/] [rtl/] [wbtb_1m_1s.vhd] - Blame information for rev 2

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1 2 amulcock
-------------------------------------------------------------------------------
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----                                                                       ----
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---- WISHBONE XXX IP Core                                                  ----
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----                                                                       ----
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---- This file is part of the XXX project                                                          ----
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---- http://www.opencores.org/cores/xxx/                                                   ----
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----                                                                       ----
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---- Description                                                           ----
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---- Implementation of XXX IP core according to                            ----
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---- XXX IP core specification document.                                   ----
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----                                                                       ----
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---- To Do:                                                                ----
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----    NA                                                                 ----
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----                                                                       ----
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---- Author(s):                                                            ----
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----   Andrew Mulcock, amulcock@opencores.org                              ----
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----                                                                       ----
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-------------------------------------------------------------------------------
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----                                                                       ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG                          ----
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----                                                                       ----
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---- This source file may be used and distributed without                  ----
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---- restriction provided that this copyright statement is not             ----
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---- removed from the file and that any derivative work contains           ----
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---- the original copyright notice and the associated disclaimer.          ----
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----                                                                       ----
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---- This source file is free software; you can redistribute it            ----
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---- and/or modify it under the terms of the GNU Lesser General            ----
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---- Public License as published by the Free Software Foundation           ----
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---- either version 2.1 of the License, or (at your option) any            ----
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---- later version.                                                        ----
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----                                                                       ----
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---- This source is distributed in the hope that it will be                ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied            ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR               ----
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---- PURPOSE. See the GNU Lesser General Public License for more           ----
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---- details.                                                              ----
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----                                                                       ----
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---- You should have received a copy of the GNU Lesser General             ----
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---- Public License along with this source; if not, download it            ----
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---- from http://www.opencores.org/lgpl.shtml                              ----
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----                                                                       ----
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-------------------------------------------------------------------------------
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----                                                                       ----
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-- CVS Revision History                                                    ----
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----                                                                       ----
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-- $Log: not supported by cvs2svn $                                                                   ----
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----                                                                       ----
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--
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-- wbtb_1m_1s
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-- 
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-- this testbench joins together 
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--  one wishbone master and one wishbone slave,
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--  along with the required sys_con module
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--
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--  having only on emaster and one slave, no logic is 
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--   required, outputs of one connect to inputs of the other.
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--
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use work.io_pack.all;
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library ieee;
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use ieee.std_logic_1164.all;
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ENTITY wbtb_1m_1s_vhd IS
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END wbtb_1m_1s_vhd;
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ARCHITECTURE behavior OF wbtb_1m_1s_vhd IS
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        -- Component Declaration for wishbone system controler
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        COMPONENT syscon
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        PORT(
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        RST_sys    : in  std_logic;
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        CLK_stop   : in  std_logic;
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        RST_O      : out std_logic;
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        CLK_O      : out std_logic
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                );
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        END COMPONENT;
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        -- Component Declaration for wishbone master
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        COMPONENT wb_master
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        PORT(
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                RST_I : IN std_logic;
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                CLK_I : IN std_logic;
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                DAT_I : IN std_logic_vector(31 downto 0);
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                ACK_I : IN std_logic;
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                ERR_I : IN std_logic;
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                RTY_I : IN std_logic;
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                SEL_O : OUT std_logic_vector(3 downto 0);
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                RST_sys : OUT std_logic;
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                CLK_stop : OUT std_logic;
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                ADR_O : OUT std_logic_vector(31 downto 0);
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                DAT_O : OUT std_logic_vector(31 downto 0);
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                WE_O : OUT std_logic;
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                STB_O : OUT std_logic;
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                CYC_O : OUT std_logic;
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                LOCK_O : OUT std_logic;
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        CYCLE_IS : OUT cycle_type
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                );
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        END COMPONENT;
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        --Inputs
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        SIGNAL RST_I :  std_logic := '0';
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        SIGNAL CLK_I :  std_logic := '0';
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        SIGNAL ACK_I :  std_logic := '0';
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        SIGNAL ERR_I :  std_logic := '0';
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        SIGNAL RTY_I :  std_logic := '0';
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        SIGNAL DAT_I :  std_logic_vector(31 downto 0) := (others=>'0');
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        --Outputs
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        SIGNAL RST_sys :  std_logic;
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        SIGNAL CLK_stop :  std_logic;
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        SIGNAL ADR_O :  std_logic_vector(31 downto 0);
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        SIGNAL DAT_O :  std_logic_vector(31 downto 0);
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        SIGNAL WE_O :  std_logic;
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        SIGNAL STB_O :  std_logic;
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        SIGNAL CYC_O :  std_logic;
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        SIGNAL LOCK_O :  std_logic;
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        SIGNAL SEL_O :  std_logic_vector(3 downto 0);
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    SIGNAL CYCLE_IS : cycle_type;
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-- ---------------------------------------------------------------
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BEGIN
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-- ---------------------------------------------------------------
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        -- Instantiate the system controler
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        sys_con: syscon PORT MAP(
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                RST_sys => RST_sys,
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                CLK_stop => CLK_stop,
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                RST_O => RST_I,
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                CLK_O => CLK_I
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        );
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        -- Instantiate the wishbone master
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        wb_m1: wb_master PORT MAP(
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                RST_sys => RST_sys,
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                CLK_stop => CLK_stop,
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                RST_I => RST_I,
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                CLK_I => CLK_I,
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                ADR_O => ADR_O,
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                DAT_I => DAT_I,
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                DAT_O => DAT_O,
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                WE_O => WE_O,
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                STB_O => STB_O,
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                CYC_O => CYC_O,
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                ACK_I => ACK_I,
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                ERR_I => ERR_I,
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                RTY_I => RTY_I,
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                LOCK_O => LOCK_O,
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                SEL_O => SEL_O,
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        CYCLE_IS => CYCLE_IS
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        );
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    ACK_I <= STB_O; -- temp wire strobe to ack
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END;

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