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amulcock |
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---- ----
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---- WISHBONE wishbone out port from b3 spec IP Core ----
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---- ----
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---- This file is part of the wishbone out port from b3 spec project ----
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---- http://www.opencores.org/cores/xxx/ ----
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---- ----
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---- Description ----
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---- Implementation of the wishbone out port from b3 spec IP core ----
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---- according to wishbone out port from b3 spec IP core specification ----
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---- document. ----
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---- ----
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---- To Do: ----
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---- NA ----
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---- ----
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---- Taken directly from the wishbone out port from b3 spec, appendix A ----
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---- Changes made, 'tidy up', I like things in lines ----
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---- change name, as Xilinx tools ( 9.2 sp 4 ) do not like ----
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---- entity same name as the file name. ----
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---- Used others clause for sync reset. ----
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---- ----
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---- Author(s): ----
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---- Andrew Mulcock, amulcock@opencores.org ----
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---- ----
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-------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-------------------------------------------------------------------------------
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-- ----
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-- CVS Revision History ----
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-- ----
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-- $Log: not supported by cvs2svn $ ----
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-- ----
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library ieee;
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use ieee.std_logic_1164.all;
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entity WB_OPRT_16 is
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port(
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-- WISHBONE SLAVE interface:
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ACK_O : out std_logic;
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CLK_I : in std_logic;
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DAT_I : in std_logic_vector( 15 downto 0 );
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DAT_O : out std_logic_vector( 15 downto 0 );
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RST_I : in std_logic;
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SEL_I : in std_logic_vector( 1 downto 0 );
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STB_I : in std_logic;
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WE_I : in std_logic;
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-- Output port (non-WISHBONE signals):
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PRT_O : out std_logic_vector( 15 downto 0 )
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);
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end entity WB_OPRT_16;
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architecture rtl of WB_OPRT_16 is
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signal QH: std_logic_vector( 7 downto 0 );
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signal QL: std_logic_vector( 7 downto 0 );
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begin
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REG: process( CLK_I )
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begin
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if( rising_edge( CLK_I ) ) then
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if( RST_I = '1' ) then
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QH <= (others => '0');
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elsif( (STB_I and WE_I and SEL_I(1)) = '1' ) then
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QH <= DAT_I( 15 downto 8 );
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else
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QH <= QH;
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end if;
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end if;
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if( rising_edge( CLK_I ) ) then
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if( RST_I = '1' ) then
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QL <= (others => '0');
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elsif( (STB_I and WE_I and SEL_I(0)) = '1' ) then
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QL <= DAT_I( 7 downto 0 );
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else
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QL <= QL;
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end if;
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end if;
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end process REG;
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ACK_O <= STB_I;
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DAT_O( 15 downto 8 ) <= QH;
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DAT_O( 7 downto 0 ) <= QL;
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PRT_O( 15 downto 8 ) <= QH;
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PRT_O( 7 downto 0 ) <= QL;
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end architecture rtl;
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