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jclaytons |
--------------------------------------------------------------------------
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-- Package of bit sync and DPLL components
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--
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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library work;
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use work.convert_pack.all;
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package spi_pack is
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component spi_flash_interface
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generic(
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NUM_CS : natural; -- Number of SPI device selects
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DEF_R_0 : unsigned(31 downto 0); -- SPI Chip Selects
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DEF_R_1 : unsigned(31 downto 0); -- SPI Command byte
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DEF_R_2 : unsigned(31 downto 0) -- SPI Address (24 bits)
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);
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port (
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-- System Clock and Clock Enable
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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sys_clk_en : in std_logic;
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-- Bus interface
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adr_i : in unsigned(3 downto 0);
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sel_i : in std_logic;
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we_i : in std_logic;
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dat_i : in unsigned(31 downto 0);
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dat_o : out unsigned(31 downto 0);
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ack_o : out std_logic;
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-- SPI interface
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-- "hold" and "WP" are not implemented.
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spi_cs_o : out unsigned(NUM_CS-1 downto 0);
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spi_sck_o : out std_logic;
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spi_so_o : out std_logic;
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spi_si_i : in std_logic
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);
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end component;
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component spi_flash_sys_init
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generic(
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SYS_CLK_RATE : real;
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FLASH_IDLE : natural; -- Number of ms idle before RAM-mapped FLASH operation closeout
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DECODE_BITS : natural; -- Number of init address upper-bits decoded to select individual SPI devices.
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DEF_R_0 : unsigned(31 downto 0) := str2u("00000001",32); -- low-level SPI Chip Select control
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DEF_R_1 : unsigned(31 downto 0) := str2u("00000003",32); -- low-level SPI Command byte
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DEF_R_2 : unsigned(31 downto 0) := str2u("007F0000",32); -- low-level SPI Address
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DEF_R_3 : unsigned(31 downto 0) := str2u("007F0000",32); -- Init Address
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DEF_R_4 : unsigned(31 downto 0) := str2u("00000100",32); -- Init Bytes
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DEF_R_5 : unsigned(31 downto 0) := str2u("00000001",32) -- Init Settings
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);
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port (
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-- System Clock and Clock Enable
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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sys_clk_en : in std_logic;
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-- Bus interface
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adr_i : in unsigned(3 downto 0);
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sel_i : in std_logic;
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we_i : in std_logic;
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dat_i : in unsigned(31 downto 0);
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dat_o : out unsigned(31 downto 0);
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ack_o : out std_logic;
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-- RAM mapped SPI FLASH access port
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-- (fl_ack_o may take ~5ms during page program)
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fl_adr_i : in unsigned(31 downto 0);
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fl_sel_i : in std_logic;
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fl_we_i : in std_logic;
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fl_dat_i : in unsigned(7 downto 0);
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fl_dat_o : out unsigned(7 downto 0);
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fl_ack_o : out std_logic;
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-- Init data output port
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init_adr_o : out unsigned(31 downto 0);
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init_dat_o : out unsigned(7 downto 0);
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init_cyc_o : out std_logic;
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init_ack_i : in std_logic;
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init_fin_o : out std_logic; -- Stays high when init is finished
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-- SPI interface
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-- "hold" and "WP" are not implemented.
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spi_adr_o : out unsigned(DECODE_BITS-1 downto 0);
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spi_cs_o : out std_logic;
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spi_sck_o : out std_logic;
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spi_so_o : out std_logic;
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spi_si_i : in std_logic
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);
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end component;
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component spi_flash_simulator
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generic(
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SYS_CLK_RATE : real;
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FLASH_ADR_BITS : natural; -- Flash memory size is based on this
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FLASH_INIT : string -- Default RX packet digestion settings
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);
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port (
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-- System Clock and Clock Enable
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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sys_clk_en : in std_logic;
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-- SPI interface
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-- "hold" and "WP" are not implemented.
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spi_cs_i : in std_logic;
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spi_sck_i : in std_logic;
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spi_si_i : in std_logic;
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spi_so_o : out std_logic
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);
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end component;
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end spi_pack;
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-------------------------------------------------------------------------------
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-- SPI Flash Interface
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-------------------------------------------------------------------------------
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--
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-- Author: John Clayton
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-- Date : July 26, 2013 Created this module starting with code copied from
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-- another module.
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-- July 31, 2013 Modified this module in simulation, until it looked
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-- correct. Tested in hardware. It works!
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-- Aug. 10, 2013 Refined the design so that it enforces a minimum
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-- spi_cs_o high time between assertions, thus allowing
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-- the design to actually program SPI FLASH chips using
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-- a 50 MHz clock, instead of just at 25 MHz.
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--
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-- Description
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-------------------------------------------------------------------------------
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-- This module is an interface to a SPI serial FLASH memory. The code was
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-- written in order to keep it as generic as possible, but without many
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-- extra frills. The module was written by reading the Adesto Technologies
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-- AT25DF641 and ST Micro M25P64 datasheets.
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--
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-- There are three registers involved in its use. There is one for the
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-- SPI command byte, one for the 24-bit SPI address, and one for data to
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-- be read from, or written to, the SPI serial FLASH device.
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--
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-- The SPI serial FLASH interface is implemented using four signals:
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-- spi_cs_o = SPI chip select outputs
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-- spi_sck_o = Serial Clock output
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-- spi_si_i = Serial Data input
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-- spi_so_o = Serial Data output
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--
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-- For multiple SPI devices, the spi_cs_o output is implemented as a bus
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-- of register driven outputs. The size of the bus is controlled by generics,
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-- allowing any number of SPI devices to be selected. Because these outputs
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-- are not decoded as a 1-active-of-N type signal, it is possible to select
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-- multiple devices simultaneously, which may work well for writing and
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-- erasing, but not for reading. You have been warned!
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--
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-- The spi_sck_o output is generated at half the sys_clk rate, and it is
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-- not adjustable. To obtain operation at lower clock rates without
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-- using a lower sys_clk frequency, consider slowing down the operation
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-- of this module by the use of the sys_clk_en signal.
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--
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-- This module takes the approach that the serial communication with the
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-- SPI device is not continuous. Instead, the command is completed in
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-- segments or phases. To begin a command, a bus write to the SPI chip
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-- select register asserts '0' on the desired chip select bits. Then, a write
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-- to the command register causes the command to be sent out, generating a
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-- burst of eight clock pulses. Another separate bus cycle is then required
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-- in order to send out the address. After that, bus cycles can be used to
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-- either read or write data bytes. At the conclusion of those activities,
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-- the command can be terminated or executed by simply writing to the SPI
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-- chip select register to raise the chip select bit back to a '1'.
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--
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-- This approach works because the spi_sck_o output is under control of
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-- this module.
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--
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-- There are no provisions for use of the "hold" or "WP" (write protect)
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-- signals. If desired, it might be possible to use sys_clk_en as a hold
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-- signal, although this has not been tested or investigated in any detail.
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--
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-- The registers are summarized as follows:
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--
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-- Address Structure Function
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-- ------- --------- -----------------------------------------------------
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-- 0x0 (N:0) SPI chip Selects, where N=NUM_CS-1.
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-- 0x1 (7:0) SPI Command Byte
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-- 0x2 (23:0) SPI Address Bytes
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-- 0x3+ (7:0) SPI Data
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--
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-- Notes on Registers:
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--
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-- (0x0) SPI Chip Selects
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--
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-- Writing to this register selects which associated spi_cs_o outputs are
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-- active. The spi_cs_o outputs are driven directly from the register,
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-- and can be changed at any time. SPI chip selects are low asserted,
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-- so the bits in this register are loaded with all ones initially.
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-- To initiate a command, the appropriate spi_cs_o bit must be cleared
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-- to zero. To conclude and execute a command, the spi_cs_o bit must
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-- be set back to one.
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-- Reading this register returns the contents, but does not affect the
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-- SPI interface.
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-- Care should be exercised when using this register with multiple SPI
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-- devices, as it is possible to activate more than one device. This
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-- may work well for writing to the devices, but will result in data bit
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-- collisions if multiple devices are read simultaneously.
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--
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-- (0x1) SPI Command Byte
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--
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-- Writing to this register causes the contents to be updated, and also
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-- sends out the new contents in serial form, most significant bit first.
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-- Reading this register returns the contents, but does not affect the
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-- SPI interface.
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--
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-- (0x2) SPI Address Bytes
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--
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-- Writing to this register causes the contents to be updated, and also
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-- sends out the new contents in serial form, most significant bit first.
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-- Reading this register returns the contents, but does not affect the
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-- SPI interface.
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--
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-- (0x3+) SPI Data Byte (Addresses in the range [0x3..0xF] access this.)
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--
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-- There is no local storage register inside the module for this address.
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-- Writing to this address causes the data to be sent out in serial form,
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-- most significant bit first.
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-- Reading this address causes a burst of eight clock pulses to be issued
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-- from the SPI interface, effectively reading in eight bits and returning
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-- them in parallel over the bus interface.
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-- Successive reads or writes therefore program or read successive locations
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-- in the SPI device.
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-- It should be noted that the SPI serial FLASH devices may allow continuous
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-- reads which go on indefinitely, cycling through the entire contents of
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-- the FLASH array. On the other hand, writes are buffered inside the
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-- FLASH device, so that a "Byte/Page Program" instruction may allow from
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-- 1 to 256 sequential bytes to be programmed. If more bytes are sent to
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-- the FLASH device, it may simply cause the FIFO buffer inside the FLASH
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-- device to hold the last 256 bytes for programming, discarding the bytes
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-- which were written at first.
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--
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-- The sys_rst_n input is an asynchronous reset.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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library work;
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use work.convert_pack.all;
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entity spi_flash_interface is
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generic(
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NUM_CS : natural := 1; -- Number of SPI device selects
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DEF_R_0 : unsigned(31 downto 0) := str2u("00000001",32); -- SPI Chip Selects
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DEF_R_1 : unsigned(31 downto 0) := str2u("00000003",32); -- SPI Command byte
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DEF_R_2 : unsigned(31 downto 0) := str2u("007F0000",32) -- SPI Address (24 bits)
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);
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port (
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-- System Clock and Clock Enable
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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sys_clk_en : in std_logic;
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-- Bus interface
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adr_i : in unsigned(3 downto 0);
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sel_i : in std_logic;
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we_i : in std_logic;
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dat_i : in unsigned(31 downto 0);
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dat_o : out unsigned(31 downto 0);
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ack_o : out std_logic;
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-- SPI interface
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-- "hold" and "WP" are not implemented.
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spi_cs_o : out unsigned(NUM_CS-1 downto 0);
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spi_sck_o : out std_logic;
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spi_so_o : out std_logic;
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spi_si_i : in std_logic
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);
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end spi_flash_interface;
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architecture beh of spi_flash_interface is
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-- Constants
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constant DAT_SIZE : natural := 32;
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-- Internal signal declarations
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signal reg_cs : unsigned(NUM_CS-1 downto 0);
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signal reg_cmd : unsigned(7 downto 0);
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signal reg_adr : unsigned(23 downto 0);
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signal sr : unsigned(7 downto 0);
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signal clk_count : unsigned(4 downto 0);
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signal ack : std_logic;
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-- For the state machine
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type FSM_STATE_TYPE is (IDLE, SEND_CMD, SEND_ADR, SHIFT_A2, SHIFT_A1, SHIFT_A0, GET_BYTE, GIVE_ACK);
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signal fsm_state : FSM_STATE_TYPE;
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-----------------------------------------------------------------------------
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begin
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-- Register read mux
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with (adr_i) select
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dat_o <=
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u_resize(reg_cs,DAT_SIZE) when "0000",
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u_resize(reg_cmd,DAT_SIZE) when "0001",
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u_resize(reg_adr,DAT_SIZE) when "0010",
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u_resize(sr,DAT_SIZE) when others;
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-- Create acknowledge signal
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ack <= '1' when sel_i='1' and fsm_state=GIVE_ACK else '0';
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ack_o <= ack;
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-- Create SPI signals
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spi_cs_o <= reg_cs;
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spi_so_o <= sr(7);
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spi_sck_o <= clk_count(0);
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-- The main process
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main_proc: process(sys_clk, sys_rst_n)
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begin
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if (sys_rst_n='0') then
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reg_cs <= DEF_R_0(NUM_CS-1 downto 0);
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reg_cmd <= DEF_R_1(reg_cmd'length-1 downto 0);
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reg_adr <= DEF_R_2(reg_adr'length-1 downto 0);
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sr <= (others=>'0');
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clk_count <= to_unsigned(0,clk_count'length);
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fsm_state <= IDLE;
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elsif (sys_clk'event and sys_clk='1') then
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|
if (sys_clk_en='1') then
|
337 |
|
|
-- Decrement the clock counter
|
338 |
|
|
if (clk_count>0) then
|
339 |
|
|
clk_count <= clk_count-1;
|
340 |
|
|
-- Handle the shift register
|
341 |
|
|
if (fsm_state=GET_BYTE and clk_count(0)='0') or (fsm_state/=GET_BYTE and clk_count(0)='1') then
|
342 |
|
|
sr <= sr(6 downto 0) & spi_si_i;
|
343 |
|
|
end if;
|
344 |
|
|
end if;
|
345 |
|
|
-- Handle state transitions
|
346 |
|
|
case (fsm_state) is
|
347 |
|
|
|
348 |
|
|
when IDLE =>
|
349 |
|
|
null;
|
350 |
|
|
|
351 |
|
|
when SEND_CMD =>
|
352 |
|
|
sr <= reg_cmd;
|
353 |
|
|
clk_count <= to_unsigned(16,clk_count'length);
|
354 |
|
|
fsm_state <= SHIFT_A0;
|
355 |
|
|
|
356 |
|
|
when SEND_ADR =>
|
357 |
|
|
sr <= reg_adr(23 downto 16);
|
358 |
|
|
clk_count <= to_unsigned(16,clk_count'length);
|
359 |
|
|
fsm_state <= SHIFT_A2;
|
360 |
|
|
|
361 |
|
|
when SHIFT_A2 =>
|
362 |
|
|
if (clk_count=0) then
|
363 |
|
|
sr <= reg_adr(15 downto 8);
|
364 |
|
|
clk_count <= to_unsigned(16,clk_count'length);
|
365 |
|
|
fsm_state <= SHIFT_A1;
|
366 |
|
|
end if;
|
367 |
|
|
|
368 |
|
|
when SHIFT_A1 =>
|
369 |
|
|
if (clk_count=0) then
|
370 |
|
|
sr <= reg_adr(7 downto 0);
|
371 |
|
|
clk_count <= to_unsigned(16,clk_count'length);
|
372 |
|
|
fsm_state <= SHIFT_A0;
|
373 |
|
|
end if;
|
374 |
|
|
|
375 |
|
|
when SHIFT_A0 =>
|
376 |
|
|
if (clk_count=0) then
|
377 |
|
|
fsm_state <= GIVE_ACK;
|
378 |
|
|
end if;
|
379 |
|
|
|
380 |
|
|
when GET_BYTE =>
|
381 |
|
|
if (clk_count=0) then
|
382 |
|
|
fsm_state <= GIVE_ACK;
|
383 |
|
|
end if;
|
384 |
|
|
|
385 |
|
|
when GIVE_ACK =>
|
386 |
|
|
fsm_state <= IDLE;
|
387 |
|
|
|
388 |
|
|
--when others =>
|
389 |
|
|
-- fsm_state <= IDLE;
|
390 |
|
|
end case;
|
391 |
|
|
|
392 |
|
|
-- Handle bus writes to registers
|
393 |
|
|
if (fsm_state=IDLE and sel_i='1' and we_i='1') then
|
394 |
|
|
case (adr_i) is
|
395 |
|
|
when "0000" =>
|
396 |
|
|
reg_cs <= dat_i(NUM_CS-1 downto 0);
|
397 |
|
|
fsm_state <= GIVE_ACK;
|
398 |
|
|
when "0001" =>
|
399 |
|
|
reg_cmd <= dat_i(reg_cmd'length-1 downto 0);
|
400 |
|
|
fsm_state <= SEND_CMD;
|
401 |
|
|
when "0010" =>
|
402 |
|
|
reg_adr <= dat_i(reg_adr'length-1 downto 0);
|
403 |
|
|
fsm_state <= SEND_ADR;
|
404 |
|
|
when others => null;
|
405 |
|
|
sr <= dat_i(sr'length-1 downto 0);
|
406 |
|
|
clk_count <= to_unsigned(16,clk_count'length);
|
407 |
|
|
fsm_state <= SHIFT_A0;
|
408 |
|
|
end case;
|
409 |
|
|
end if;
|
410 |
|
|
-- Handle SPI read cycle
|
411 |
|
|
if (fsm_state=IDLE and sel_i='1' and we_i='0') then
|
412 |
|
|
case (adr_i) is
|
413 |
|
|
when "0000" =>
|
414 |
|
|
fsm_state <= GIVE_ACK;
|
415 |
|
|
when "0001" =>
|
416 |
|
|
fsm_state <= GIVE_ACK;
|
417 |
|
|
when "0010" =>
|
418 |
|
|
fsm_state <= GIVE_ACK;
|
419 |
|
|
when others =>
|
420 |
|
|
clk_count <= to_unsigned(16,clk_count'length);
|
421 |
|
|
fsm_state <= GET_BYTE;
|
422 |
|
|
end case;
|
423 |
|
|
end if;
|
424 |
|
|
|
425 |
|
|
end if; -- sys_clk_en
|
426 |
|
|
end if; -- sys_clk
|
427 |
|
|
end process;
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
end beh;
|
431 |
|
|
|
432 |
|
|
-------------------------------------------------------------------------------
|
433 |
|
|
-- SPI Flash System Initializer
|
434 |
|
|
-------------------------------------------------------------------------------
|
435 |
|
|
--
|
436 |
|
|
-- Author: John Clayton
|
437 |
|
|
-- Date : July 31, 2013 Created this module starting with code copied from
|
438 |
|
|
-- another module. Began writing description.
|
439 |
|
|
-- Aug. 5, 2013 Simulated the design. Revamped the register
|
440 |
|
|
-- structure, added init_chain feature. Combined
|
441 |
|
|
-- states in fl_state FSM.
|
442 |
|
|
-- Aug. 7, 2013 Added explicit reset bit.
|
443 |
|
|
--
|
444 |
|
|
-- Description
|
445 |
|
|
-------------------------------------------------------------------------------
|
446 |
|
|
-- This module uses an interface to SPI serial FLASH memory devices to allow
|
447 |
|
|
-- reading/writing/erasing of the FLASH. It includes a state machine that
|
448 |
|
|
-- coordinates many of the required commands automatically, to make the
|
449 |
|
|
-- process of reading and writing SPI FLASH appear as though a simple RAM
|
450 |
|
|
-- is being used. Moreover, the state machine has an initialization mode
|
451 |
|
|
-- which can read bytes out of the selected SPI FLASH device and present
|
452 |
|
|
-- them on an 8-bit parallel output port.
|
453 |
|
|
--
|
454 |
|
|
-- The actual rate of outputting "initialization bytes" is determined by
|
455 |
|
|
-- the init_ack_i input, up to the maximum available rate Fmax of approx.
|
456 |
|
|
-- 2.7 MBytes/second. This maximum byte transfer rate is calculated
|
457 |
|
|
-- according to the following formula:
|
458 |
|
|
--
|
459 |
|
|
-- Fmax = (Fsys_clk / N)
|
460 |
|
|
--
|
461 |
|
|
-- Where N=18 sys_clks required per byte obtained, and Fsys_clk is
|
462 |
|
|
-- currently 50 MHz. Other sys_clk rates would also work.
|
463 |
|
|
--
|
464 |
|
|
-- The init_adr_o output allows the outgoing bytes to be treated in
|
465 |
|
|
-- different ways, or stored into different places, depending on the address
|
466 |
|
|
-- setting being used. Note that the init_adr_o output is taken directly
|
467 |
|
|
-- from the init address register, which refers to the addresses within
|
468 |
|
|
-- the SPI devices themselves. This signal therefore not required to be
|
469 |
|
|
-- used as-is during initialization. Feel free to substitute any addresses
|
470 |
|
|
-- you want, or re-map the initialization addresses as needed.
|
471 |
|
|
--
|
472 |
|
|
-- The idea is that the parallel output bytes can be used to send commands
|
473 |
|
|
-- on a system bus. One way to do this is to attach a UART, which would
|
474 |
|
|
-- inject ASCII characters into an ASCII command interpreter, such as
|
475 |
|
|
-- "async_syscon" or "udp_ip_syscon".
|
476 |
|
|
--
|
477 |
|
|
-- Another way would be to send the bytes into a binary command interpreter.
|
478 |
|
|
--
|
479 |
|
|
-- Another way would be to attach the init port as a requester on the arbiter
|
480 |
|
|
-- for the target bus.
|
481 |
|
|
--
|
482 |
|
|
-- In addition to creating initialization commands at power on, the output
|
483 |
|
|
-- bytes can also be treated as DSP samples of a waveform. Thus, the output
|
484 |
|
|
-- could be used to generate audio "sound bytes" [pun intended] at a set
|
485 |
|
|
-- sample rate and bits per sample.
|
486 |
|
|
--
|
487 |
|
|
-- In fact, it is conceivable that through the use of a command interpreter,
|
488 |
|
|
-- a final initialization command could reprogram the initialization address
|
489 |
|
|
-- and quantity, in order to begin a whole new initialization sequence! Oh,
|
490 |
|
|
-- the sheer joy of it! If there is no command interpreter being used, there
|
491 |
|
|
-- is an alternative method of achieving this serial-init-sequencing joy.
|
492 |
|
|
-- A chain enable bit is provided in the initialization settings register
|
493 |
|
|
-- which causes the initialization sequencer to "re-up" by using the last
|
494 |
|
|
-- eight bytes of the current initialization sequence as a new address and
|
495 |
|
|
-- quantity for the next one. Isn't that simply grand?
|
496 |
|
|
--
|
497 |
|
|
-- Think of what you could do... You could set up registers in the first
|
498 |
|
|
-- initialization sequence, and then invoke another sequence which would
|
499 |
|
|
-- play some kind of audio greeting. It could be music, or perhaps a voice.
|
500 |
|
|
-- Like the audio might say "System is now fully functional, and ready!"
|
501 |
|
|
-- Like that. You know, it isn't bad to have a healthy imagination.
|
502 |
|
|
-- At least, that's what I imagine.
|
503 |
|
|
--
|
504 |
|
|
-- As a corollary benefit of implementing the initialization function, an
|
505 |
|
|
-- additional SPI FLASH memory mapping "feature" is provided. This means
|
506 |
|
|
-- that the entire contents of the SPI FLASH device is memory mapped, with a
|
507 |
|
|
-- separate address for each byte within the device. Sequential reads and
|
508 |
|
|
-- writes are allowed within this address space, and the needed WREN and
|
509 |
|
|
-- other commands to perform the reads/writes are performed automatically.
|
510 |
|
|
-- This also means that the bus cycle acknowledge signal when using the
|
511 |
|
|
-- memory mapped region can take quite a long time to appear, on the order
|
512 |
|
|
-- of 5 ms. Also note that the key word when using the memory mapped
|
513 |
|
|
-- region is "sequential." This is so important that this module actually
|
514 |
|
|
-- enforces sequential accesses, by keeping a copy of the initial address
|
515 |
|
|
-- and incrementing that during the session. The "session" begins when
|
516 |
|
|
-- an access is requested within the memory mapped region, and ends when
|
517 |
|
|
-- an "access idle" timeout is reached. Therefore, temporally-sequential
|
518 |
|
|
-- accesses which attempt to decrement the address, or jump around in
|
519 |
|
|
-- other ways, will actually result in sequential bytes being read/written
|
520 |
|
|
-- during the session.
|
521 |
|
|
--
|
522 |
|
|
-- The system initializer is an extension of a much simpler register-based
|
523 |
|
|
-- "low-level" SPI Flash interface module. The "low-level" features are
|
524 |
|
|
-- preserved in this module.
|
525 |
|
|
--
|
526 |
|
|
-- The original interface was written in order to be as generic as possible,
|
527 |
|
|
-- without many extra frills. The module was written by and tested using
|
528 |
|
|
-- the Adesto Technologies AT25DF641 and ST Micro M25P64 datasheets. Also,
|
529 |
|
|
-- hardware testing was initially done on the M25P64 mounted on a Lattice
|
530 |
|
|
-- Semiconductor "Versa" FPGA development board. Nevertheless, this design
|
531 |
|
|
-- should work quite easily with other SPI FLASH devices and other FPGAs.
|
532 |
|
|
--
|
533 |
|
|
-- For the basic SPI interface, there are three registers involved.
|
534 |
|
|
-- There is one for the SPI command byte, one for the 24-bit SPI address,
|
535 |
|
|
-- and one for data to be read from, or written to, the SPI serial FLASH
|
536 |
|
|
-- device. The basic interface was preserved in order to allow for any
|
537 |
|
|
-- desired command to be explicitly executed via register accesses.
|
538 |
|
|
--
|
539 |
|
|
-- The SPI serial FLASH interface is implemented using four signals:
|
540 |
|
|
-- spi_cs_o = SPI chip select outputs
|
541 |
|
|
-- spi_sck_o = Serial Clock output
|
542 |
|
|
-- spi_si_i = Serial Data input
|
543 |
|
|
-- spi_so_o = Serial Data output
|
544 |
|
|
--
|
545 |
|
|
-- For multiple SPI devices, the spi_cs_o output is implemented as a bus
|
546 |
|
|
-- of register driven outputs. The size of the bus is controlled by generics,
|
547 |
|
|
-- allowing any number of SPI devices to be selected. Because these outputs
|
548 |
|
|
-- are not decoded as a 1-active-of-N type signal, it is possible to select
|
549 |
|
|
-- multiple devices simultaneously, which may work well for writing and
|
550 |
|
|
-- erasing, but not for reading. You have been warned!
|
551 |
|
|
--
|
552 |
|
|
-- The spi_sck_o output is generated at half the sys_clk rate, and it is
|
553 |
|
|
-- not adjustable. To obtain operation at lower clock rates without
|
554 |
|
|
-- using a lower sys_clk frequency, consider slowing down the operation
|
555 |
|
|
-- of this module by the use of the sys_clk_en signal.
|
556 |
|
|
--
|
557 |
|
|
-- This module takes the approach that the serial communication with the
|
558 |
|
|
-- SPI device is not continuous. Instead, the command is completed in
|
559 |
|
|
-- segments or phases. To begin a command, a bus write to the SPI chip
|
560 |
|
|
-- select register asserts '0' on the desired chip select bits. Then, a write
|
561 |
|
|
-- to the command register causes the command to be sent out, generating a
|
562 |
|
|
-- burst of eight clock pulses. Another separate bus cycle is then required
|
563 |
|
|
-- in order to send out the address. After that, bus cycles can be used to
|
564 |
|
|
-- either read or write data bytes. At the conclusion of those activities,
|
565 |
|
|
-- the command can be terminated or executed by simply writing to the SPI
|
566 |
|
|
-- chip select register to raise the chip select bit back to a '1'.
|
567 |
|
|
--
|
568 |
|
|
-- This approach works because the spi_sck_o output is under control of
|
569 |
|
|
-- this module.
|
570 |
|
|
--
|
571 |
|
|
-- There are no provisions for use of the "hold" or "WP" (write protect)
|
572 |
|
|
-- signals. If desired, it might be possible to use sys_clk_en as a hold
|
573 |
|
|
-- signal, although this has not been tested or investigated in any detail.
|
574 |
|
|
--
|
575 |
|
|
-- The registers are summarized as follows:
|
576 |
|
|
--
|
577 |
|
|
-- Address Structure Function
|
578 |
|
|
-- ------- -------------- -----------------------------------------------------
|
579 |
|
|
-- 0x0 (N+16:16,N:0) SPI chip Selects, where N=NUM_CS-1.
|
580 |
|
|
-- 0x1 (7:0) SPI Command Byte
|
581 |
|
|
-- 0x2 (23:0) SPI Address Bytes
|
582 |
|
|
-- 0x3 (31:0) Init Address
|
583 |
|
|
-- 0x4 (31:0) Init Quantity (bytes)
|
584 |
|
|
-- 0x5 (3:0) Init Settings
|
585 |
|
|
-- 0x6+ (7:0) SPI Data
|
586 |
|
|
--
|
587 |
|
|
-- Notes on Registers:
|
588 |
|
|
--
|
589 |
|
|
-- (0x0) low-level SPI Chip Select control
|
590 |
|
|
--
|
591 |
|
|
-- This register contains a single bit, which is directly mapped to the
|
592 |
|
|
-- spi_cs_o output during low-level SPI operations. During ram mapped
|
593 |
|
|
-- operations and initialization sequences, the spi_cs_o output is
|
594 |
|
|
-- controlled automatically by a state machine so that during those
|
595 |
|
|
-- operations, this bit has no effect.
|
596 |
|
|
--
|
597 |
|
|
-- (0x1) low-level SPI Command Byte
|
598 |
|
|
--
|
599 |
|
|
-- This is part of the low-level SPI interface, and is not involved in
|
600 |
|
|
-- initialization or RAM mapping of the SPI devices.
|
601 |
|
|
--
|
602 |
|
|
-- Writing to this register causes the contents to be updated, and also
|
603 |
|
|
-- sends out the new contents in serial form, most significant bit first.
|
604 |
|
|
-- Reading this register returns the contents, but does not affect the
|
605 |
|
|
-- SPI interface.
|
606 |
|
|
--
|
607 |
|
|
-- (0x2) low-level SPI Address
|
608 |
|
|
--
|
609 |
|
|
-- This is part of the low-level SPI interface, and is not involved in
|
610 |
|
|
-- initialization or RAM mapping of the SPI devices.
|
611 |
|
|
--
|
612 |
|
|
-- Writing to this register causes the contents to be updated, and also
|
613 |
|
|
-- sends out the new contents in serial form, most significant bits first.
|
614 |
|
|
-- Reading this register returns the contents, but does not affect the
|
615 |
|
|
-- SPI interface.
|
616 |
|
|
--
|
617 |
|
|
-- The number of bytes used for SPI addresses is set by the constant
|
618 |
|
|
-- SPI_ADR_BYTES.
|
619 |
|
|
--
|
620 |
|
|
-- (0x3) Init Address
|
621 |
|
|
--
|
622 |
|
|
-- Bits (31:0) contain the initialization address, which consists of
|
623 |
|
|
-- four bytes: [decode][sector][page][byte]
|
624 |
|
|
-- This grouping of fields is actually based on the size of the
|
625 |
|
|
-- SPI FLASH devices being tested. If larger devices are used,
|
626 |
|
|
-- for example, then the [decode] field may use fewer bits, and
|
627 |
|
|
-- the [sector] field may grow. Similarly, the [page] field might
|
628 |
|
|
-- change if the devices being used have pages larger than 256
|
629 |
|
|
-- bytes. So, it's a matter of interpretation. The main idea is
|
630 |
|
|
-- for form a flat address space which maps all the attached SPI
|
631 |
|
|
-- devices.
|
632 |
|
|
--
|
633 |
|
|
-- (0x4) Initialization Quantity (Bytes)
|
634 |
|
|
-- This register contains the number of bytes to read from the SPI
|
635 |
|
|
-- FLASH device during an initialization operation.
|
636 |
|
|
-- The number can be quite large, up to 0x800000 (8 Mbytes) for the
|
637 |
|
|
-- AT25DF641 and M25P64. In anticipation of larger future devices,
|
638 |
|
|
-- this field was made a full 32-bits, allowing up to 4 gigabytes.
|
639 |
|
|
-- Operation of the initialization cycle begins immediately once
|
640 |
|
|
-- this field is set to anything greater than zero. Also, the
|
641 |
|
|
-- quantity is "live" and it decrements during initialization.
|
642 |
|
|
--
|
643 |
|
|
-- (0x5) Init Settings
|
644 |
|
|
--
|
645 |
|
|
-- Bit (0) is the R/W Access Enable bit. Set this bit in order to
|
646 |
|
|
-- freely read and write to the SPI FLASH via the memory mapped
|
647 |
|
|
-- interface. When it is cleared, the memory mapped interface does
|
648 |
|
|
-- not respond with a bus cycle acknowledge, since it is not
|
649 |
|
|
-- operating.
|
650 |
|
|
-- Bit (1) is the Initialization chain enable bit. Setting this bit
|
651 |
|
|
-- causes the last eight bytes of the initialization to be withheld.
|
652 |
|
|
-- Instead of being sent out as bus cycles on the parallel init bus,
|
653 |
|
|
-- the bytes are used to reset the initializer for another run
|
654 |
|
|
-- using a new address and a new quantity. Since the init_ack_i
|
655 |
|
|
-- input is used to throttle initialization cycles when delays are
|
656 |
|
|
-- required, no delay is provided within the eight "re-up" bytes.
|
657 |
|
|
-- The re-up bytes are composed of four address bytes, followed by
|
658 |
|
|
-- four quantity bytes. The fields are stored least significant
|
659 |
|
|
-- byte first.
|
660 |
|
|
-- Bit (2) is the Erase bit. Set this bit to erase the sector
|
661 |
|
|
-- currently selected by the [sector] field in the address register.
|
662 |
|
|
-- Note that sector erase times can be on the order of seconds.
|
663 |
|
|
-- (Typically 1s, but up to 3s for M25P64. Typically 400ms, but
|
664 |
|
|
-- up to 950ms for AT25DF641.) Since the erase operation is
|
665 |
|
|
-- self-timed inside the device, this module polls the device status
|
666 |
|
|
-- register to see when the erase operation is completed. When it
|
667 |
|
|
-- is, the erase bit is then cleared. No other operations are
|
668 |
|
|
-- possible while this is occurring. Because the sector erase can
|
669 |
|
|
-- take so long, there is a way to break out by using the explicit
|
670 |
|
|
-- reset bit. Also, there is no automatic timeout from the sector
|
671 |
|
|
-- erase operation.
|
672 |
|
|
-- Bit (3) is an explicit reset bit. Setting it resets both state
|
673 |
|
|
-- machines. It is a write only bit, and returns a '0' when read.
|
674 |
|
|
-- It can be used to "break out" of an operation, such as a long
|
675 |
|
|
-- sector erase.
|
676 |
|
|
--
|
677 |
|
|
-- (0x6+) SPI Data Byte (System cycles in the range [0x6..0xF] access this.)
|
678 |
|
|
--
|
679 |
|
|
-- This is part of the low-level SPI interface, and is not involved in
|
680 |
|
|
-- initialization or RAM mapping of the SPI devices.
|
681 |
|
|
--
|
682 |
|
|
-- There is no local storage register inside the module for this address.
|
683 |
|
|
-- Writing to this address causes the data to be sent out in serial form,
|
684 |
|
|
-- most significant bit first.
|
685 |
|
|
-- Reading this address causes a burst of eight clock pulses to be issued
|
686 |
|
|
-- from the SPI interface, effectively reading in eight bits and returning
|
687 |
|
|
-- them in parallel over the bus interface.
|
688 |
|
|
-- Successive reads or writes therefore program or read successive locations
|
689 |
|
|
-- in the SPI device.
|
690 |
|
|
-- It should be noted that the SPI serial FLASH devices may allow continuous
|
691 |
|
|
-- reads which go on indefinitely, cycling through the entire contents of
|
692 |
|
|
-- the FLASH array. On the other hand, writes are buffered inside the
|
693 |
|
|
-- FLASH device, so that a "Byte/Page Program" instruction may allow from
|
694 |
|
|
-- 1 to 256 sequential bytes to be programmed. If more bytes are sent to
|
695 |
|
|
-- the FLASH device, it may simply cause the FIFO buffer inside the FLASH
|
696 |
|
|
-- device to hold the last 256 bytes for programming, discarding the bytes
|
697 |
|
|
-- which were written at first.
|
698 |
|
|
--
|
699 |
|
|
-- The sys_rst_n input is an asynchronous reset.
|
700 |
|
|
|
701 |
|
|
library IEEE;
|
702 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
703 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
704 |
|
|
use IEEE.MATH_REAL.ALL;
|
705 |
|
|
|
706 |
|
|
library work;
|
707 |
|
|
use work.dds_pack.all;
|
708 |
|
|
use work.convert_pack.all;
|
709 |
|
|
|
710 |
|
|
entity spi_flash_sys_init is
|
711 |
|
|
generic(
|
712 |
|
|
SYS_CLK_RATE : real := 50000000.0;
|
713 |
|
|
FLASH_IDLE : natural := 2; -- Number of ms idle before RAM-mapped FLASH operation closeout
|
714 |
|
|
DECODE_BITS : natural := 8; -- Number of init address upper-bits decoded to select individual SPI devices.
|
715 |
|
|
DEF_R_0 : unsigned(31 downto 0) := str2u("00000001",32); -- low-level SPI Chip Select control
|
716 |
|
|
DEF_R_1 : unsigned(31 downto 0) := str2u("00000003",32); -- low-level SPI Command byte
|
717 |
|
|
DEF_R_2 : unsigned(31 downto 0) := str2u("007F0000",32); -- low-level SPI Address
|
718 |
|
|
DEF_R_3 : unsigned(31 downto 0) := str2u("007F0000",32); -- Init Address
|
719 |
|
|
DEF_R_4 : unsigned(31 downto 0) := str2u("00000100",32); -- Init Bytes
|
720 |
|
|
DEF_R_5 : unsigned(31 downto 0) := str2u("00000001",32) -- Init Settings
|
721 |
|
|
);
|
722 |
|
|
port (
|
723 |
|
|
-- System Clock and Clock Enable
|
724 |
|
|
sys_rst_n : in std_logic;
|
725 |
|
|
sys_clk : in std_logic;
|
726 |
|
|
sys_clk_en : in std_logic;
|
727 |
|
|
|
728 |
|
|
-- Bus interface
|
729 |
|
|
adr_i : in unsigned(3 downto 0);
|
730 |
|
|
sel_i : in std_logic;
|
731 |
|
|
we_i : in std_logic;
|
732 |
|
|
dat_i : in unsigned(31 downto 0);
|
733 |
|
|
dat_o : out unsigned(31 downto 0);
|
734 |
|
|
ack_o : out std_logic;
|
735 |
|
|
|
736 |
|
|
-- RAM mapped SPI FLASH access port
|
737 |
|
|
-- (fl_ack_o may take ~5ms during page program)
|
738 |
|
|
fl_adr_i : in unsigned(31 downto 0);
|
739 |
|
|
fl_sel_i : in std_logic;
|
740 |
|
|
fl_we_i : in std_logic;
|
741 |
|
|
fl_dat_i : in unsigned(7 downto 0);
|
742 |
|
|
fl_dat_o : out unsigned(7 downto 0);
|
743 |
|
|
fl_ack_o : out std_logic;
|
744 |
|
|
|
745 |
|
|
-- Init data output port
|
746 |
|
|
init_adr_o : out unsigned(31 downto 0);
|
747 |
|
|
init_dat_o : out unsigned(7 downto 0);
|
748 |
|
|
init_cyc_o : out std_logic;
|
749 |
|
|
init_ack_i : in std_logic;
|
750 |
|
|
init_fin_o : out std_logic; -- Stays high when init is finished
|
751 |
|
|
|
752 |
|
|
-- SPI interface
|
753 |
|
|
-- "hold" and "WP" are not implemented.
|
754 |
|
|
spi_adr_o : out unsigned(DECODE_BITS-1 downto 0);
|
755 |
|
|
spi_cs_o : out std_logic;
|
756 |
|
|
spi_sck_o : out std_logic;
|
757 |
|
|
spi_so_o : out std_logic;
|
758 |
|
|
spi_si_i : in std_logic
|
759 |
|
|
|
760 |
|
|
);
|
761 |
|
|
end spi_flash_sys_init;
|
762 |
|
|
|
763 |
|
|
architecture beh of spi_flash_sys_init is
|
764 |
|
|
|
765 |
|
|
-- Constants
|
766 |
|
|
constant DAT_SIZE : natural := 32;
|
767 |
|
|
constant IDLE_TB_FREQ : real := 1000.0; -- Timebase is millisecond resolution
|
768 |
|
|
constant IDLE_TB_ACC_BITS : natural := 24;
|
769 |
|
|
constant IDLE_TIMER_WIDTH : natural := timer_width(FLASH_IDLE);
|
770 |
|
|
|
771 |
|
|
constant SPI_ADR_BYTES : natural := 3; -- Increase for larger size devices
|
772 |
|
|
constant SPI_ACNT_WIDTH : natural := timer_width(SPI_ADR_BYTES);
|
773 |
|
|
|
774 |
|
|
constant SPI_CMD_PP : natural := 16#02#;
|
775 |
|
|
constant SPI_CMD_READ : natural := 16#03#;
|
776 |
|
|
constant SPI_CMD_RDSR : natural := 16#05#;
|
777 |
|
|
constant SPI_CMD_WREN : natural := 16#06#;
|
778 |
|
|
constant SPI_CMD_SE : natural := 16#D8#;
|
779 |
|
|
|
780 |
|
|
constant CS_HIGH_CYCLES : natural := 8; -- minimum # of sysclks spi_cs_o will be driven high.
|
781 |
|
|
constant CLK_COUNT_1BYTE : natural := 16;
|
782 |
|
|
constant CLK_COUNT_DESEL : natural := CLK_COUNT_1BYTE+CS_HIGH_CYCLES;
|
783 |
|
|
|
784 |
|
|
-- Internal signal declarations
|
785 |
|
|
signal reg_cs : std_logic;
|
786 |
|
|
signal reg_cmd : unsigned(7 downto 0);
|
787 |
|
|
signal reg_adr : unsigned(31 downto 0);
|
788 |
|
|
signal reg_ispi_adr : unsigned(31 downto 0);
|
789 |
|
|
signal adr_count : unsigned(SPI_ACNT_WIDTH-1 downto 0);
|
790 |
|
|
signal adr_word : unsigned(31 downto 0);
|
791 |
|
|
signal adr_byte : unsigned(7 downto 0);
|
792 |
|
|
signal sr : unsigned(7 downto 0);
|
793 |
|
|
signal clk_count : unsigned(4 downto 0);
|
794 |
|
|
signal spi_ack : std_logic;
|
795 |
|
|
signal reg_we : std_logic;
|
796 |
|
|
signal reg_rw : std_logic;
|
797 |
|
|
signal reg_chain : std_logic;
|
798 |
|
|
signal reg_erasing : std_logic;
|
799 |
|
|
signal reg_init_len : unsigned(31 downto 0);
|
800 |
|
|
signal reg_new_len : unsigned(31 downto 0);
|
801 |
|
|
signal idle_timer : unsigned(IDLE_TIMER_WIDTH-1 downto 0);
|
802 |
|
|
signal idle_tb_pulse : std_logic;
|
803 |
|
|
signal idle_tb_ftw : unsigned(IDLE_TB_ACC_BITS-1 downto 0);
|
804 |
|
|
signal idle_tb_hold : std_logic;
|
805 |
|
|
|
806 |
|
|
-- For the SPI state machine
|
807 |
|
|
type SPI_STATE_TYPE is (IDLE, SEND_CMD, SEND_ADR, SHIFT_ADR, SHIFT_BYTE,
|
808 |
|
|
GET_BYTE, GIVE_ACK);
|
809 |
|
|
signal spi_state : SPI_STATE_TYPE;
|
810 |
|
|
|
811 |
|
|
-- For the FLASH state machine
|
812 |
|
|
type FLASH_STATE_TYPE is (IDLE, R_WREN, R_CMD, R_ADR, R_DAT, R_WAIT,
|
813 |
|
|
R_STAT_1, R_STAT_2, INIT_CYCLE, INIT_CHAIN, INIT_RESTART);
|
814 |
|
|
signal fl_state : FLASH_STATE_TYPE;
|
815 |
|
|
signal fl_ack : std_logic;
|
816 |
|
|
|
817 |
|
|
|
818 |
|
|
-----------------------------------------------------------------------------
|
819 |
|
|
begin
|
820 |
|
|
|
821 |
|
|
-- Register read mux
|
822 |
|
|
with (adr_i) select
|
823 |
|
|
dat_o <=
|
824 |
|
|
to_unsigned(0,31) & reg_cs when "0000",
|
825 |
|
|
u_resize(reg_cmd,DAT_SIZE) when "0001",
|
826 |
|
|
reg_adr when "0010",
|
827 |
|
|
reg_ispi_adr when "0011",
|
828 |
|
|
u_resize(reg_init_len,DAT_SIZE) when "0100",
|
829 |
|
|
to_unsigned(0,29) & reg_erasing & reg_chain & reg_rw when "0101",
|
830 |
|
|
u_resize(sr,DAT_SIZE) when others;
|
831 |
|
|
|
832 |
|
|
-- Create acknowledge signals
|
833 |
|
|
spi_ack <= '1' when spi_state=GIVE_ACK else '0';
|
834 |
|
|
ack_o <= '1' when spi_ack='1' and sel_i='1' else '0';
|
835 |
|
|
fl_ack_o <= fl_ack;
|
836 |
|
|
|
837 |
|
|
-- Provide FLASH data output
|
838 |
|
|
fl_dat_o <= sr;
|
839 |
|
|
|
840 |
|
|
-- Provide initialization outputs
|
841 |
|
|
init_adr_o <= reg_ispi_adr;
|
842 |
|
|
init_cyc_o <= '1' when fl_state=INIT_CYCLE else '0';
|
843 |
|
|
|
844 |
|
|
-- Create SPI signals
|
845 |
|
|
spi_adr_o <= adr_word(adr_word'length-1 downto adr_word'length-DECODE_BITS);
|
846 |
|
|
spi_cs_o <= reg_cs when fl_state=IDLE else
|
847 |
|
|
'0' when clk_count<=CLK_COUNT_1BYTE else
|
848 |
|
|
'1';
|
849 |
|
|
spi_so_o <= sr(7);
|
850 |
|
|
spi_sck_o <= clk_count(0) when clk_count<CLK_COUNT_1BYTE else '0';
|
851 |
|
|
|
852 |
|
|
-- Select the correct address byte
|
853 |
|
|
adr_word <= reg_adr when fl_state=IDLE else reg_ispi_adr;
|
854 |
|
|
-- with (to_integer(adr_count)) select
|
855 |
|
|
-- adr_byte <=
|
856 |
|
|
-- (others=>'0') when 0,
|
857 |
|
|
-- adr_word(8*to_integer(adr_count)-1 downto 8*(to_integer(adr_count)-1)) when others;
|
858 |
|
|
with (to_integer(adr_count)) select
|
859 |
|
|
adr_byte <=
|
860 |
|
|
(others=>'0') when 0,
|
861 |
|
|
adr_word(7 downto 0) when 1,
|
862 |
|
|
adr_word(15 downto 8) when 2,
|
863 |
|
|
adr_word(23 downto 16) when 3,
|
864 |
|
|
adr_word(31 downto 24) when 4,
|
865 |
|
|
(others=>'0') when others;
|
866 |
|
|
|
867 |
|
|
-- Create timebase for idle timer
|
868 |
|
|
idle_tb_ftw <= to_unsigned(integer(IDLE_TB_FREQ*(2**real(IDLE_TB_ACC_BITS))/SYS_CLK_RATE),idle_tb_ftw'length);
|
869 |
|
|
idle_tb_hold <= '0' when (fl_state=IDLE or fl_state=R_WAIT or fl_state=INIT_CYCLE) else '1';
|
870 |
|
|
timer_0 : dds_squarewave_phase_load
|
871 |
|
|
generic map(
|
872 |
|
|
ACC_BITS => IDLE_TB_ACC_BITS
|
873 |
|
|
)
|
874 |
|
|
port map(
|
875 |
|
|
|
876 |
|
|
sys_rst_n => sys_rst_n,
|
877 |
|
|
sys_clk => sys_clk,
|
878 |
|
|
sys_clk_en => sys_clk_en,
|
879 |
|
|
|
880 |
|
|
-- Frequency setting
|
881 |
|
|
freq_i => idle_tb_ftw,
|
882 |
|
|
|
883 |
|
|
-- Synchronous load
|
884 |
|
|
phase_i => to_unsigned(2**(IDLE_TB_ACC_BITS-1),IDLE_TB_ACC_BITS),
|
885 |
|
|
phase_ld_i => idle_tb_hold,
|
886 |
|
|
|
887 |
|
|
-- Output
|
888 |
|
|
pulse_o => idle_tb_pulse,
|
889 |
|
|
squarewave_o => open
|
890 |
|
|
);
|
891 |
|
|
|
892 |
|
|
-- Handle state machines and writes to registers
|
893 |
|
|
reg_proc: process(sys_clk, sys_rst_n)
|
894 |
|
|
begin
|
895 |
|
|
if (sys_rst_n='0') then
|
896 |
|
|
reg_cs <= DEF_R_0(0);
|
897 |
|
|
reg_cmd <= DEF_R_1(reg_cmd'length-1 downto 0);
|
898 |
|
|
reg_adr <= DEF_R_2;
|
899 |
|
|
reg_ispi_adr <= DEF_R_3;
|
900 |
|
|
reg_rw <= DEF_R_5(0);
|
901 |
|
|
reg_chain <= DEF_R_5(1);
|
902 |
|
|
reg_init_len <= DEF_R_4(reg_init_len'length-1 downto 0);
|
903 |
|
|
reg_new_len <= (others=>'0');
|
904 |
|
|
sr <= (others=>'0');
|
905 |
|
|
adr_count <= to_unsigned(1,adr_count'length);
|
906 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
907 |
|
|
spi_state <= IDLE;
|
908 |
|
|
fl_state <= IDLE;
|
909 |
|
|
fl_ack <= '0';
|
910 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
911 |
|
|
init_dat_o <= (others=>'0');
|
912 |
|
|
reg_we <= '0';
|
913 |
|
|
elsif (sys_clk'event and sys_clk='1') then
|
914 |
|
|
if (sys_clk_en='1') then
|
915 |
|
|
-- Decrement the SPI clock counter
|
916 |
|
|
if (clk_count>0) then
|
917 |
|
|
clk_count <= clk_count-1;
|
918 |
|
|
-- Handle the SPI shift register
|
919 |
|
|
if (spi_state=GET_BYTE and clk_count(0)='0' and clk_count<CLK_COUNT_1BYTE) or
|
920 |
|
|
(spi_state/=GET_BYTE and clk_count(0)='1' and clk_count<CLK_COUNT_1BYTE) then
|
921 |
|
|
sr <= sr(6 downto 0) & spi_si_i;
|
922 |
|
|
end if;
|
923 |
|
|
end if;
|
924 |
|
|
-- Handle the FLASH idle timeout
|
925 |
|
|
if (idle_timer>0 and idle_tb_pulse='1') then
|
926 |
|
|
idle_timer <= idle_timer-1;
|
927 |
|
|
end if;
|
928 |
|
|
----------------------------------
|
929 |
|
|
-- Handle SPI state transitions --
|
930 |
|
|
----------------------------------
|
931 |
|
|
case (spi_state) is
|
932 |
|
|
|
933 |
|
|
when IDLE =>
|
934 |
|
|
null;
|
935 |
|
|
|
936 |
|
|
when SEND_CMD =>
|
937 |
|
|
sr <= reg_cmd;
|
938 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
939 |
|
|
spi_state <= SHIFT_BYTE;
|
940 |
|
|
|
941 |
|
|
-- adr_count must have already been set when going into this state,
|
942 |
|
|
-- to ensure that sr is loaded with the correct bytes
|
943 |
|
|
when SEND_ADR =>
|
944 |
|
|
sr <= adr_byte;
|
945 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
946 |
|
|
spi_state <= SHIFT_ADR;
|
947 |
|
|
|
948 |
|
|
when SHIFT_ADR =>
|
949 |
|
|
if (clk_count=0) then
|
950 |
|
|
if (adr_count=1) then
|
951 |
|
|
spi_state <= GIVE_ACK;
|
952 |
|
|
else
|
953 |
|
|
adr_count <= adr_count-1;
|
954 |
|
|
spi_state <= SEND_ADR;
|
955 |
|
|
end if;
|
956 |
|
|
end if;
|
957 |
|
|
|
958 |
|
|
when SHIFT_BYTE =>
|
959 |
|
|
if (clk_count=0) then
|
960 |
|
|
spi_state <= GIVE_ACK;
|
961 |
|
|
end if;
|
962 |
|
|
|
963 |
|
|
when GET_BYTE =>
|
964 |
|
|
if (clk_count=0) then
|
965 |
|
|
spi_state <= GIVE_ACK;
|
966 |
|
|
end if;
|
967 |
|
|
|
968 |
|
|
when GIVE_ACK =>
|
969 |
|
|
spi_state <= IDLE;
|
970 |
|
|
|
971 |
|
|
--when others =>
|
972 |
|
|
-- spi_state <= IDLE;
|
973 |
|
|
end case;
|
974 |
|
|
|
975 |
|
|
------------------------------------
|
976 |
|
|
-- Handle FLASH state transitions --
|
977 |
|
|
------------------------------------
|
978 |
|
|
-- Default Values
|
979 |
|
|
fl_ack <= '0';
|
980 |
|
|
case (fl_state) is
|
981 |
|
|
|
982 |
|
|
when IDLE =>
|
983 |
|
|
if (reg_rw='1' and spi_state=IDLE) then
|
984 |
|
|
if (fl_sel_i='1') then
|
985 |
|
|
-- Store local copy of requested address
|
986 |
|
|
-- All subsequenct accesses within the SPI command session will be sequential
|
987 |
|
|
-- The external address does not guarantee this, but the internal
|
988 |
|
|
-- one does.
|
989 |
|
|
reg_ispi_adr <= fl_adr_i;
|
990 |
|
|
-- Store write/read indication
|
991 |
|
|
reg_we <= fl_we_i;
|
992 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
993 |
|
|
if (fl_we_i='1') then
|
994 |
|
|
reg_cmd <= to_unsigned(SPI_CMD_PP,reg_cmd'length);
|
995 |
|
|
fl_state <= R_WREN;
|
996 |
|
|
sr <= to_unsigned(SPI_CMD_WREN,sr'length);
|
997 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
998 |
|
|
spi_state <= SHIFT_BYTE;
|
999 |
|
|
else
|
1000 |
|
|
reg_cmd <= to_unsigned(SPI_CMD_READ,reg_cmd'length);
|
1001 |
|
|
fl_state <= R_CMD;
|
1002 |
|
|
sr <= to_unsigned(SPI_CMD_READ,sr'length);
|
1003 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1004 |
|
|
spi_state <= SHIFT_BYTE;
|
1005 |
|
|
end if;
|
1006 |
|
|
end if;
|
1007 |
|
|
end if;
|
1008 |
|
|
-- If there is initialization to do, get it done.
|
1009 |
|
|
-- This has priority over other operations.
|
1010 |
|
|
if (reg_init_len>0) then
|
1011 |
|
|
reg_cmd <= to_unsigned(SPI_CMD_READ,reg_cmd'length);
|
1012 |
|
|
fl_state <= R_CMD;
|
1013 |
|
|
sr <= to_unsigned(SPI_CMD_READ,sr'length);
|
1014 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1015 |
|
|
spi_state <= SHIFT_BYTE;
|
1016 |
|
|
end if;
|
1017 |
|
|
|
1018 |
|
|
when R_WREN =>
|
1019 |
|
|
if (spi_ack='1') then
|
1020 |
|
|
sr <= reg_cmd;
|
1021 |
|
|
-- Deselect SPI device to execute SPI command
|
1022 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
1023 |
|
|
spi_state <= SHIFT_BYTE;
|
1024 |
|
|
fl_state <= R_CMD;
|
1025 |
|
|
end if;
|
1026 |
|
|
|
1027 |
|
|
when R_CMD =>
|
1028 |
|
|
if (spi_ack='1') then
|
1029 |
|
|
adr_count <= to_unsigned(SPI_ADR_BYTES,adr_count'length);
|
1030 |
|
|
spi_state <= SEND_ADR;
|
1031 |
|
|
fl_state <= R_ADR;
|
1032 |
|
|
end if;
|
1033 |
|
|
|
1034 |
|
|
when R_ADR =>
|
1035 |
|
|
if (spi_ack='1') then
|
1036 |
|
|
if (reg_cmd=SPI_CMD_SE) then
|
1037 |
|
|
sr <= to_unsigned(SPI_CMD_RDSR,sr'length);
|
1038 |
|
|
-- Deselect SPI device to execute SPI command
|
1039 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
1040 |
|
|
spi_state <= SHIFT_BYTE;
|
1041 |
|
|
fl_state <= R_STAT_1;
|
1042 |
|
|
else
|
1043 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1044 |
|
|
spi_state <= SHIFT_BYTE;
|
1045 |
|
|
fl_state <= R_DAT;
|
1046 |
|
|
sr <= fl_dat_i; -- Needed for writes, and does not affect reads.
|
1047 |
|
|
end if;
|
1048 |
|
|
end if;
|
1049 |
|
|
|
1050 |
|
|
when R_DAT =>
|
1051 |
|
|
if (reg_init_len>0) then
|
1052 |
|
|
-- Handle init case
|
1053 |
|
|
if (spi_ack='1') then
|
1054 |
|
|
if (reg_chain='1' and reg_init_len<=8) then
|
1055 |
|
|
fl_state <= INIT_CHAIN;
|
1056 |
|
|
else
|
1057 |
|
|
init_dat_o <= sr;
|
1058 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1059 |
|
|
fl_state <= INIT_CYCLE;
|
1060 |
|
|
end if;
|
1061 |
|
|
end if;
|
1062 |
|
|
else
|
1063 |
|
|
-- Handle memory mapped I/O case
|
1064 |
|
|
-- Await timeout, in case current cycle is not de-asserted in time.
|
1065 |
|
|
if (idle_timer=0) then
|
1066 |
|
|
if (reg_cmd=SPI_CMD_READ) then
|
1067 |
|
|
fl_state <= IDLE;
|
1068 |
|
|
else
|
1069 |
|
|
-- Deselect SPI device to execute SPI command
|
1070 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
1071 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1072 |
|
|
sr <= to_unsigned(SPI_CMD_RDSR,sr'length);
|
1073 |
|
|
spi_state <= SHIFT_BYTE;
|
1074 |
|
|
fl_state <= R_STAT_1;
|
1075 |
|
|
end if;
|
1076 |
|
|
end if;
|
1077 |
|
|
-- Acknowledge the memory mapped cycle
|
1078 |
|
|
if (spi_ack='1') then
|
1079 |
|
|
fl_ack <= '1';
|
1080 |
|
|
end if;
|
1081 |
|
|
-- Handle de-assertion of current cycle
|
1082 |
|
|
if (fl_sel_i='0') then
|
1083 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1084 |
|
|
fl_state <= R_WAIT;
|
1085 |
|
|
end if;
|
1086 |
|
|
end if;
|
1087 |
|
|
|
1088 |
|
|
-- This is a "waiting state" to see if the current SPI session is
|
1089 |
|
|
-- going to continue. It continues if another write is requested.
|
1090 |
|
|
-- within the allowed timeout window.
|
1091 |
|
|
when R_WAIT =>
|
1092 |
|
|
-- On timeout, terminate the SPI PP command.
|
1093 |
|
|
if (idle_timer=0) then
|
1094 |
|
|
if (reg_cmd=SPI_CMD_READ) then
|
1095 |
|
|
fl_state <= IDLE;
|
1096 |
|
|
else
|
1097 |
|
|
-- Deselect SPI device to execute SPI command
|
1098 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
1099 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1100 |
|
|
sr <= to_unsigned(SPI_CMD_RDSR,sr'length);
|
1101 |
|
|
spi_state <= SHIFT_BYTE;
|
1102 |
|
|
fl_state <= R_STAT_1;
|
1103 |
|
|
end if;
|
1104 |
|
|
end if;
|
1105 |
|
|
-- If another similar cycle is requested, continue
|
1106 |
|
|
if (fl_sel_i='1' and fl_we_i=reg_we) then
|
1107 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1108 |
|
|
sr <= fl_dat_i;
|
1109 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1110 |
|
|
spi_state <= SHIFT_BYTE;
|
1111 |
|
|
fl_state <= R_DAT;
|
1112 |
|
|
end if;
|
1113 |
|
|
-- If a different cycle is requested, terminate the SPI command
|
1114 |
|
|
if (fl_sel_i='1' and fl_we_i/=reg_we) then
|
1115 |
|
|
if (reg_cmd=SPI_CMD_READ) then
|
1116 |
|
|
fl_state <= IDLE;
|
1117 |
|
|
else
|
1118 |
|
|
-- Deselect SPI device to execute SPI command
|
1119 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
1120 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1121 |
|
|
sr <= to_unsigned(SPI_CMD_RDSR,sr'length);
|
1122 |
|
|
spi_state <= SHIFT_BYTE;
|
1123 |
|
|
fl_state <= R_STAT_1;
|
1124 |
|
|
end if;
|
1125 |
|
|
end if;
|
1126 |
|
|
|
1127 |
|
|
-- Timeout is disabled for sector erase.
|
1128 |
|
|
-- The erase register bit can be cleared to reset the state machine.
|
1129 |
|
|
-- (It can take a veeeerrrryy long time to erase a sector...)
|
1130 |
|
|
-- (Like up to a second!)
|
1131 |
|
|
when R_STAT_1 =>
|
1132 |
|
|
if (spi_ack='1') then
|
1133 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1134 |
|
|
spi_state <= SHIFT_BYTE;
|
1135 |
|
|
fl_state <= R_STAT_2;
|
1136 |
|
|
end if;
|
1137 |
|
|
|
1138 |
|
|
when R_STAT_2 =>
|
1139 |
|
|
if (idle_timer=0 and reg_cmd/=SPI_CMD_SE) then
|
1140 |
|
|
fl_state <= IDLE;
|
1141 |
|
|
elsif (spi_ack='1') then
|
1142 |
|
|
if (sr(0)='1') then -- If WIP is set, keep checking status.
|
1143 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1144 |
|
|
spi_state <= SHIFT_BYTE;
|
1145 |
|
|
else
|
1146 |
|
|
fl_state <= IDLE;
|
1147 |
|
|
end if;
|
1148 |
|
|
end if;
|
1149 |
|
|
|
1150 |
|
|
-- This state creates an init cycle
|
1151 |
|
|
when INIT_CYCLE =>
|
1152 |
|
|
-- Await timeout, in case current cycle is not acknowledged in time.
|
1153 |
|
|
if (idle_timer=0) then
|
1154 |
|
|
fl_state <= IDLE;
|
1155 |
|
|
end if;
|
1156 |
|
|
-- Await acknowledge of current cycle
|
1157 |
|
|
if (init_ack_i='1') then
|
1158 |
|
|
reg_ispi_adr <= reg_ispi_adr+1;
|
1159 |
|
|
reg_init_len <= reg_init_len-1;
|
1160 |
|
|
if (reg_init_len=1) then
|
1161 |
|
|
fl_state <= IDLE;
|
1162 |
|
|
else
|
1163 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1164 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1165 |
|
|
spi_state <= SHIFT_BYTE;
|
1166 |
|
|
fl_state <= R_DAT;
|
1167 |
|
|
end if;
|
1168 |
|
|
end if;
|
1169 |
|
|
|
1170 |
|
|
when INIT_CHAIN =>
|
1171 |
|
|
if (reg_init_len>4) then
|
1172 |
|
|
reg_ispi_adr(7 downto 0) <= sr;
|
1173 |
|
|
reg_ispi_adr(31 downto 8) <= reg_ispi_adr(23 downto 0);
|
1174 |
|
|
else
|
1175 |
|
|
reg_new_len(7 downto 0) <= sr;
|
1176 |
|
|
reg_new_len(31 downto 8) <= reg_new_len(23 downto 0);
|
1177 |
|
|
end if;
|
1178 |
|
|
reg_init_len <= reg_init_len-1;
|
1179 |
|
|
if (reg_init_len=1) then
|
1180 |
|
|
fl_state <= INIT_RESTART;
|
1181 |
|
|
else
|
1182 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1183 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1184 |
|
|
spi_state <= SHIFT_BYTE;
|
1185 |
|
|
fl_state <= R_DAT;
|
1186 |
|
|
end if;
|
1187 |
|
|
|
1188 |
|
|
when INIT_RESTART =>
|
1189 |
|
|
if (reg_new_len>0) then
|
1190 |
|
|
reg_init_len <= reg_new_len;
|
1191 |
|
|
-- Deselect SPI device to execute SPI command
|
1192 |
|
|
clk_count <= to_unsigned(CLK_COUNT_DESEL,clk_count'length);
|
1193 |
|
|
idle_timer <= to_unsigned(FLASH_IDLE,idle_timer'length);
|
1194 |
|
|
sr <= to_unsigned(SPI_CMD_RDSR,sr'length);
|
1195 |
|
|
spi_state <= SHIFT_BYTE;
|
1196 |
|
|
fl_state <= R_STAT_1;
|
1197 |
|
|
else
|
1198 |
|
|
fl_state <= IDLE;
|
1199 |
|
|
end if;
|
1200 |
|
|
|
1201 |
|
|
when others =>
|
1202 |
|
|
spi_state <= IDLE;
|
1203 |
|
|
end case;
|
1204 |
|
|
|
1205 |
|
|
-- Handle bus writes to registers
|
1206 |
|
|
if (spi_state=IDLE and fl_state=IDLE and sel_i='1' and we_i='1') then
|
1207 |
|
|
case (adr_i) is
|
1208 |
|
|
when "0000" =>
|
1209 |
|
|
reg_cs <= dat_i(0);
|
1210 |
|
|
spi_state <= GIVE_ACK;
|
1211 |
|
|
when "0001" =>
|
1212 |
|
|
reg_cmd <= dat_i(reg_cmd'length-1 downto 0);
|
1213 |
|
|
spi_state <= SEND_CMD;
|
1214 |
|
|
when "0010" =>
|
1215 |
|
|
reg_adr <= dat_i;
|
1216 |
|
|
adr_count <= to_unsigned(SPI_ADR_BYTES,adr_count'length);
|
1217 |
|
|
spi_state <= SEND_ADR;
|
1218 |
|
|
when "0011" =>
|
1219 |
|
|
reg_ispi_adr <= dat_i(reg_ispi_adr'length-1 downto 0);
|
1220 |
|
|
spi_state <= GIVE_ACK; -- A quick acknowledgment
|
1221 |
|
|
when "0100" =>
|
1222 |
|
|
reg_init_len <= dat_i(reg_init_len'length-1 downto 0);
|
1223 |
|
|
spi_state <= GIVE_ACK; -- A quick acknowledgment
|
1224 |
|
|
when "0101" =>
|
1225 |
|
|
reg_rw <= dat_i(0);
|
1226 |
|
|
reg_chain <= dat_i(1);
|
1227 |
|
|
if (dat_i(2)='1') then
|
1228 |
|
|
if (reg_erasing='0') then
|
1229 |
|
|
reg_cmd <= to_unsigned(SPI_CMD_SE,reg_cmd'length);
|
1230 |
|
|
fl_state <= R_WREN;
|
1231 |
|
|
sr <= to_unsigned(SPI_CMD_WREN,sr'length);
|
1232 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1233 |
|
|
spi_state <= SHIFT_BYTE;
|
1234 |
|
|
end if;
|
1235 |
|
|
else
|
1236 |
|
|
spi_state <= GIVE_ACK; -- A quick acknowledgment
|
1237 |
|
|
end if;
|
1238 |
|
|
if (dat_i(3)='1') then
|
1239 |
|
|
spi_state <= IDLE;
|
1240 |
|
|
fl_state <= IDLE;
|
1241 |
|
|
reg_init_len <= (others=>'0');
|
1242 |
|
|
end if;
|
1243 |
|
|
when others =>
|
1244 |
|
|
sr <= dat_i(sr'length-1 downto 0);
|
1245 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1246 |
|
|
spi_state <= SHIFT_BYTE;
|
1247 |
|
|
end case;
|
1248 |
|
|
end if;
|
1249 |
|
|
-- Handle SPI read cycle
|
1250 |
|
|
if (spi_state=IDLE and fl_state=IDLE and sel_i='1' and we_i='0') then
|
1251 |
|
|
case (adr_i) is
|
1252 |
|
|
when "0000" =>
|
1253 |
|
|
spi_state <= GIVE_ACK;
|
1254 |
|
|
when "0001" =>
|
1255 |
|
|
spi_state <= GIVE_ACK;
|
1256 |
|
|
when "0010" =>
|
1257 |
|
|
spi_state <= GIVE_ACK;
|
1258 |
|
|
when "0011" =>
|
1259 |
|
|
spi_state <= GIVE_ACK;
|
1260 |
|
|
when "0100" =>
|
1261 |
|
|
spi_state <= GIVE_ACK;
|
1262 |
|
|
when "0101" =>
|
1263 |
|
|
spi_state <= GIVE_ACK;
|
1264 |
|
|
when others =>
|
1265 |
|
|
clk_count <= to_unsigned(CLK_COUNT_1BYTE,clk_count'length);
|
1266 |
|
|
spi_state <= GET_BYTE;
|
1267 |
|
|
end case;
|
1268 |
|
|
end if;
|
1269 |
|
|
|
1270 |
|
|
end if; -- sys_clk_en
|
1271 |
|
|
end if; -- sys_clk
|
1272 |
|
|
end process;
|
1273 |
|
|
|
1274 |
|
|
-- Create signal that is high during sector erase activity
|
1275 |
|
|
reg_erasing <= '1' when (fl_state/=IDLE and reg_cmd=SPI_CMD_SE) else '0';
|
1276 |
|
|
|
1277 |
|
|
-- Create signal that is high whenever initialization is not active.
|
1278 |
|
|
init_fin_o <= '1' when reg_init_len=0 else '0';
|
1279 |
|
|
|
1280 |
|
|
end beh;
|
1281 |
|
|
|
1282 |
|
|
-------------------------------------------------------------------------------
|
1283 |
|
|
-- SPI Flash Simulator
|
1284 |
|
|
-------------------------------------------------------------------------------
|
1285 |
|
|
--
|
1286 |
|
|
-- Author: John Clayton
|
1287 |
|
|
-- Date : Aug. 7, 2013 Created this module starting with code copied from
|
1288 |
|
|
-- another module.
|
1289 |
|
|
-- Aug. 10, 2013 Added and simulated page programming and sector erase
|
1290 |
|
|
-- with concurrent status register reads. Only the
|
1291 |
|
|
-- WIP bit is implemented within the status register.
|
1292 |
|
|
--
|
1293 |
|
|
-- Description
|
1294 |
|
|
-------------------------------------------------------------------------------
|
1295 |
|
|
-- This module is a very simplistic SPI FLASH simulator. It was created with
|
1296 |
|
|
-- the intent of running a simulation, so that real data can be returned from
|
1297 |
|
|
-- this module to a device which is accessing a SPI FLASH device.
|
1298 |
|
|
--
|
1299 |
|
|
-- Because of its simple intent, this module does not implement all the
|
1300 |
|
|
-- functions of a typical SPI FLASH, but it does do reading and writing.
|
1301 |
|
|
-- It implements the "write enable latch" instruction, and it can be erased
|
1302 |
|
|
-- too.
|
1303 |
|
|
--
|
1304 |
|
|
-- The kind of device being simulated has 24 address bits, although the size
|
1305 |
|
|
-- of the simulated FLASH memory is much smaller. It will simply wrap around
|
1306 |
|
|
-- to the beginning of the array if the end is passed.
|
1307 |
|
|
--
|
1308 |
|
|
-- Because the unit is for simulation only, a separate clock domain is created
|
1309 |
|
|
-- for the spi_sclk_i input
|
1310 |
|
|
--
|
1311 |
|
|
-- The sys_rst_n input is an asynchronous reset.
|
1312 |
|
|
|
1313 |
|
|
library IEEE;
|
1314 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
1315 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
1316 |
|
|
use IEEE.MATH_REAL.ALL;
|
1317 |
|
|
|
1318 |
|
|
library work;
|
1319 |
|
|
use work.dds_pack.all;
|
1320 |
|
|
use work.convert_pack.all;
|
1321 |
|
|
use work.block_ram_pack.all;
|
1322 |
|
|
|
1323 |
|
|
entity spi_flash_simulator is
|
1324 |
|
|
generic(
|
1325 |
|
|
SYS_CLK_RATE : real := 50000000.0;
|
1326 |
|
|
FLASH_ADR_BITS : natural := 8; -- Flash memory size is based on this
|
1327 |
|
|
FLASH_INIT : string := ".\flash_sim_init.txt" -- Default RX packet digestion settings
|
1328 |
|
|
);
|
1329 |
|
|
port (
|
1330 |
|
|
-- System Clock and Clock Enable
|
1331 |
|
|
sys_rst_n : in std_logic;
|
1332 |
|
|
sys_clk : in std_logic;
|
1333 |
|
|
sys_clk_en : in std_logic;
|
1334 |
|
|
|
1335 |
|
|
-- SPI interface
|
1336 |
|
|
-- "hold" and "WP" are not implemented.
|
1337 |
|
|
spi_cs_i : in std_logic;
|
1338 |
|
|
spi_sck_i : in std_logic;
|
1339 |
|
|
spi_si_i : in std_logic;
|
1340 |
|
|
spi_so_o : out std_logic
|
1341 |
|
|
|
1342 |
|
|
);
|
1343 |
|
|
end spi_flash_simulator;
|
1344 |
|
|
|
1345 |
|
|
architecture beh of spi_flash_simulator is
|
1346 |
|
|
|
1347 |
|
|
-- Constants
|
1348 |
|
|
constant SPI_CMD_NOP : natural := 16#00#;
|
1349 |
|
|
constant SPI_CMD_PP : natural := 16#02#;
|
1350 |
|
|
constant SPI_CMD_READ : natural := 16#03#;
|
1351 |
|
|
constant SPI_CMD_RDSR : natural := 16#05#;
|
1352 |
|
|
constant SPI_CMD_WREN : natural := 16#06#;
|
1353 |
|
|
constant SPI_CMD_SE : natural := 16#D8#;
|
1354 |
|
|
|
1355 |
|
|
constant WIP_PP_TIMEOUT : natural := 12; -- 1.2 milliseconds
|
1356 |
|
|
--constant WIP_SE_TIMEOUT : natural := 12000; -- 1.2 seconds (realistic number)
|
1357 |
|
|
constant WIP_SE_TIMEOUT : natural := 24; -- 2.4 milliseconds (for faster simulation)
|
1358 |
|
|
constant WIP_TB_FREQ : real := 10000.0; -- Timebase is 100 microsecond resolution
|
1359 |
|
|
constant WIP_TB_ACC_BITS : natural := 24;
|
1360 |
|
|
constant WIP_TIMER_WIDTH : natural := timer_width(WIP_SE_TIMEOUT);
|
1361 |
|
|
constant SECTOR_BITS : natural := 16; -- Determines # of bytes to erase
|
1362 |
|
|
|
1363 |
|
|
-- Internal signal declarations
|
1364 |
|
|
signal reg_cmd : unsigned(7 downto 0);
|
1365 |
|
|
signal reg_adr : unsigned(23 downto 0);
|
1366 |
|
|
signal flash_adr : unsigned(FLASH_ADR_BITS-1 downto 0);
|
1367 |
|
|
signal array_adr : unsigned(FLASH_ADR_BITS-1 downto 0);
|
1368 |
|
|
signal flash_we : std_logic;
|
1369 |
|
|
signal flash_dat : unsigned(7 downto 0);
|
1370 |
|
|
signal sr : unsigned(7 downto 0);
|
1371 |
|
|
signal sr_full : std_logic;
|
1372 |
|
|
signal reg_wel : std_logic; -- Write Enable Latch bit
|
1373 |
|
|
signal reg_wip : std_logic; -- Write In Progress bit
|
1374 |
|
|
signal clk_count : unsigned(2 downto 0);
|
1375 |
|
|
signal clk_count_r1 : unsigned(2 downto 0);
|
1376 |
|
|
signal clk_count_r2 : unsigned(2 downto 0);
|
1377 |
|
|
signal wip_timer : unsigned(WIP_TIMER_WIDTH-1 downto 0);
|
1378 |
|
|
signal wip_tb_pulse : std_logic;
|
1379 |
|
|
signal wip_tb_ftw : unsigned(WIP_TB_ACC_BITS-1 downto 0);
|
1380 |
|
|
signal wip_tb_hold : std_logic;
|
1381 |
|
|
signal sector_adr : unsigned(SECTOR_BITS-1 downto 0);
|
1382 |
|
|
signal sector_erase : std_logic;
|
1383 |
|
|
signal erase_adr : unsigned(23 downto 0);
|
1384 |
|
|
signal array_dat_wr : unsigned(7 downto 0);
|
1385 |
|
|
|
1386 |
|
|
-- For the state machine
|
1387 |
|
|
type FSM_STATE_TYPE is (AWAIT_CMD, AWAIT_ADR_2, AWAIT_ADR_1, AWAIT_ADR_0,
|
1388 |
|
|
AWAIT_CS_HI, STORE_BYTE);
|
1389 |
|
|
signal fsm_state : FSM_STATE_TYPE;
|
1390 |
|
|
|
1391 |
|
|
|
1392 |
|
|
-----------------------------------------------------------------------------
|
1393 |
|
|
begin
|
1394 |
|
|
|
1395 |
|
|
-- Create SPI signals
|
1396 |
|
|
spi_so_o <= sr(7);
|
1397 |
|
|
|
1398 |
|
|
-- The shift register process
|
1399 |
|
|
-- Nothing is ever synchronously cleared, loaded or reset here.
|
1400 |
|
|
-- The shift register and counter simply "roll over" in a cyclical
|
1401 |
|
|
-- way, forever after the asynchronous reset.
|
1402 |
|
|
sr_proc: process(spi_sck_i, sys_rst_n)
|
1403 |
|
|
begin
|
1404 |
|
|
if (sys_rst_n='0') then
|
1405 |
|
|
sr <= (others=>'0');
|
1406 |
|
|
clk_count <= (others=>'0');
|
1407 |
|
|
elsif (spi_sck_i'event and spi_sck_i='1') then
|
1408 |
|
|
if (spi_cs_i='0') then
|
1409 |
|
|
sr <= sr(6 downto 0) & spi_si_i;
|
1410 |
|
|
clk_count <= clk_count+1;
|
1411 |
|
|
-- Here assign the shift register
|
1412 |
|
|
-- Action depends on command type
|
1413 |
|
|
case (to_integer(reg_cmd)) is
|
1414 |
|
|
when SPI_CMD_READ =>
|
1415 |
|
|
if (fsm_state=AWAIT_CS_HI and clk_count=0) then
|
1416 |
|
|
sr <= flash_dat;
|
1417 |
|
|
end if;
|
1418 |
|
|
when SPI_CMD_PP =>
|
1419 |
|
|
null;
|
1420 |
|
|
when SPI_CMD_SE =>
|
1421 |
|
|
null;
|
1422 |
|
|
when SPI_CMD_RDSR =>
|
1423 |
|
|
if (fsm_state=AWAIT_CS_HI and clk_count=0) then
|
1424 |
|
|
sr <= "0000000" & reg_wip;
|
1425 |
|
|
end if;
|
1426 |
|
|
when others =>
|
1427 |
|
|
null;
|
1428 |
|
|
end case;
|
1429 |
|
|
else
|
1430 |
|
|
clk_count <= (others=>'0');
|
1431 |
|
|
end if;
|
1432 |
|
|
end if; -- spi_sck_i
|
1433 |
|
|
end process;
|
1434 |
|
|
|
1435 |
|
|
-- Create timebase for WIP timer
|
1436 |
|
|
wip_tb_ftw <= to_unsigned(integer(WIP_TB_FREQ*(2**real(WIP_TB_ACC_BITS))/SYS_CLK_RATE),wip_tb_ftw'length);
|
1437 |
|
|
wip_tb_hold <= '0' when reg_wip='1' else '1';
|
1438 |
|
|
timer_0 : dds_squarewave_phase_load
|
1439 |
|
|
generic map(
|
1440 |
|
|
ACC_BITS => WIP_TB_ACC_BITS
|
1441 |
|
|
)
|
1442 |
|
|
port map(
|
1443 |
|
|
|
1444 |
|
|
sys_rst_n => sys_rst_n,
|
1445 |
|
|
sys_clk => sys_clk,
|
1446 |
|
|
sys_clk_en => sys_clk_en,
|
1447 |
|
|
|
1448 |
|
|
-- Frequency setting
|
1449 |
|
|
freq_i => wip_tb_ftw,
|
1450 |
|
|
|
1451 |
|
|
-- Synchronous load
|
1452 |
|
|
phase_i => to_unsigned(2**(WIP_TB_ACC_BITS-1),WIP_TB_ACC_BITS),
|
1453 |
|
|
phase_ld_i => wip_tb_hold,
|
1454 |
|
|
|
1455 |
|
|
-- Output
|
1456 |
|
|
pulse_o => wip_tb_pulse,
|
1457 |
|
|
squarewave_o => open
|
1458 |
|
|
);
|
1459 |
|
|
reg_wip <= '1' when (wip_timer>0) else '0';
|
1460 |
|
|
|
1461 |
|
|
-- Create signal which indicates when the shift register is done shifting a byte
|
1462 |
|
|
sr_full <= '1' when (clk_count_r1=0 and clk_count_r2=7) else '0';
|
1463 |
|
|
-- Since the simulated FLASH memory array may be much smaller than the address,
|
1464 |
|
|
-- select the salient part for use in addressing the array.
|
1465 |
|
|
flash_adr <= u_resize(reg_adr,flash_adr'length);
|
1466 |
|
|
|
1467 |
|
|
-- The main process
|
1468 |
|
|
main_proc: process(sys_clk, sys_rst_n)
|
1469 |
|
|
begin
|
1470 |
|
|
if (sys_rst_n='0') then
|
1471 |
|
|
reg_cmd <= to_unsigned(SPI_CMD_NOP,reg_cmd'length);
|
1472 |
|
|
reg_adr <= (others=>'0');
|
1473 |
|
|
reg_wel <= '0';
|
1474 |
|
|
fsm_state <= AWAIT_CMD;
|
1475 |
|
|
wip_timer <= to_unsigned(0,wip_timer'length);
|
1476 |
|
|
clk_count_r1 <= (others=>'0');
|
1477 |
|
|
clk_count_r2 <= (others=>'0');
|
1478 |
|
|
sector_adr <= (others=>'0');
|
1479 |
|
|
sector_erase <= '0';
|
1480 |
|
|
elsif (sys_clk'event and sys_clk='1') then
|
1481 |
|
|
if (sys_clk_en='1') then
|
1482 |
|
|
-- default values
|
1483 |
|
|
|
1484 |
|
|
-- Synchronize and capture the clk_count value, in order to
|
1485 |
|
|
-- detect changes to it.
|
1486 |
|
|
clk_count_r1 <= clk_count;
|
1487 |
|
|
clk_count_r2 <= clk_count_r1;
|
1488 |
|
|
|
1489 |
|
|
-- Handle WIP timer count down
|
1490 |
|
|
if (wip_tb_pulse='1' and wip_timer>0) then
|
1491 |
|
|
wip_timer <= wip_timer-1;
|
1492 |
|
|
end if;
|
1493 |
|
|
|
1494 |
|
|
-- Handle actual sector erase array storage operations
|
1495 |
|
|
if (sector_erase='1') then
|
1496 |
|
|
sector_adr <= sector_adr+1;
|
1497 |
|
|
if (sector_adr=(2**sector_adr'length)-1) then
|
1498 |
|
|
sector_erase <= '0';
|
1499 |
|
|
end if;
|
1500 |
|
|
end if;
|
1501 |
|
|
|
1502 |
|
|
-- Handle state transitions
|
1503 |
|
|
case (fsm_state) is
|
1504 |
|
|
|
1505 |
|
|
when AWAIT_CMD =>
|
1506 |
|
|
if (sr_full='1' and spi_cs_i='0') then
|
1507 |
|
|
if (reg_wip='0') then
|
1508 |
|
|
reg_cmd <= sr;
|
1509 |
|
|
if (sr=SPI_CMD_WREN) then
|
1510 |
|
|
reg_wel <= '1';
|
1511 |
|
|
fsm_state <= AWAIT_CS_HI;
|
1512 |
|
|
else
|
1513 |
|
|
fsm_state <= AWAIT_ADR_2;
|
1514 |
|
|
end if;
|
1515 |
|
|
else
|
1516 |
|
|
fsm_state <= AWAIT_CS_HI;
|
1517 |
|
|
-- Only RDSR is allowed when there is a write in progress (WIP)
|
1518 |
|
|
if (sr=SPI_CMD_RDSR) then
|
1519 |
|
|
reg_cmd <= sr;
|
1520 |
|
|
else
|
1521 |
|
|
reg_cmd <= to_unsigned(SPI_CMD_NOP,reg_cmd'length);
|
1522 |
|
|
end if;
|
1523 |
|
|
end if;
|
1524 |
|
|
end if;
|
1525 |
|
|
|
1526 |
|
|
when AWAIT_ADR_2 =>
|
1527 |
|
|
if (sr_full='1') then
|
1528 |
|
|
reg_adr(23 downto 16) <= sr;
|
1529 |
|
|
fsm_state <= AWAIT_ADR_1;
|
1530 |
|
|
end if;
|
1531 |
|
|
|
1532 |
|
|
when AWAIT_ADR_1 =>
|
1533 |
|
|
if (sr_full='1') then
|
1534 |
|
|
reg_adr(15 downto 8) <= sr;
|
1535 |
|
|
fsm_state <= AWAIT_ADR_0;
|
1536 |
|
|
end if;
|
1537 |
|
|
|
1538 |
|
|
when AWAIT_ADR_0 =>
|
1539 |
|
|
if (sr_full='1') then
|
1540 |
|
|
reg_adr(7 downto 0) <= sr;
|
1541 |
|
|
fsm_state <= AWAIT_CS_HI;
|
1542 |
|
|
end if;
|
1543 |
|
|
|
1544 |
|
|
when AWAIT_CS_HI =>
|
1545 |
|
|
if (sr_full='1') then
|
1546 |
|
|
-- Action depends on command type
|
1547 |
|
|
case (to_integer(reg_cmd)) is
|
1548 |
|
|
when SPI_CMD_READ =>
|
1549 |
|
|
reg_adr <= reg_adr+1;
|
1550 |
|
|
when SPI_CMD_PP =>
|
1551 |
|
|
if (reg_wel='1') then
|
1552 |
|
|
fsm_state <= STORE_BYTE;
|
1553 |
|
|
end if;
|
1554 |
|
|
when SPI_CMD_SE =>
|
1555 |
|
|
null;
|
1556 |
|
|
when SPI_CMD_RDSR =>
|
1557 |
|
|
null;
|
1558 |
|
|
when others =>
|
1559 |
|
|
null;
|
1560 |
|
|
end case;
|
1561 |
|
|
end if;
|
1562 |
|
|
if (spi_cs_i='1') then
|
1563 |
|
|
fsm_state <= AWAIT_CMD;
|
1564 |
|
|
if (reg_cmd/=SPI_CMD_WREN) then
|
1565 |
|
|
reg_wel <= '0';
|
1566 |
|
|
end if;
|
1567 |
|
|
if (reg_cmd=SPI_CMD_PP) then
|
1568 |
|
|
wip_timer <= to_unsigned(WIP_PP_TIMEOUT,wip_timer'length);
|
1569 |
|
|
end if;
|
1570 |
|
|
if (reg_cmd=SPI_CMD_SE) then
|
1571 |
|
|
wip_timer <= to_unsigned(WIP_SE_TIMEOUT,wip_timer'length);
|
1572 |
|
|
sector_erase <= '1';
|
1573 |
|
|
end if;
|
1574 |
|
|
end if;
|
1575 |
|
|
|
1576 |
|
|
-- Being in this state asserts the flash_we signal
|
1577 |
|
|
when STORE_BYTE =>
|
1578 |
|
|
reg_adr <= reg_adr+1;
|
1579 |
|
|
fsm_state <= AWAIT_CS_HI;
|
1580 |
|
|
|
1581 |
|
|
--when others =>
|
1582 |
|
|
-- fsm_state <= IDLE;
|
1583 |
|
|
end case;
|
1584 |
|
|
|
1585 |
|
|
end if; -- sys_clk_en
|
1586 |
|
|
end if; -- sys_clk
|
1587 |
|
|
end process;
|
1588 |
|
|
|
1589 |
|
|
-- This BRAM contains the simulated FLASH contents
|
1590 |
|
|
flash_ram : block_ram_dp_writethrough_hexfile_init
|
1591 |
|
|
generic map(
|
1592 |
|
|
init_file => FLASH_INIT,
|
1593 |
|
|
fil_width => 8,
|
1594 |
|
|
adr_width => FLASH_ADR_BITS,
|
1595 |
|
|
dat_width => 8
|
1596 |
|
|
)
|
1597 |
|
|
port map (
|
1598 |
|
|
clk_a => sys_clk,
|
1599 |
|
|
clk_b => sys_clk,
|
1600 |
|
|
|
1601 |
|
|
adr_a_i => array_adr,
|
1602 |
|
|
adr_b_i => to_unsigned(0,FLASH_ADR_BITS),
|
1603 |
|
|
|
1604 |
|
|
we_a_i => flash_we,
|
1605 |
|
|
en_a_i => '1',
|
1606 |
|
|
dat_a_i => array_dat_wr,
|
1607 |
|
|
dat_a_o => flash_dat,
|
1608 |
|
|
|
1609 |
|
|
we_b_i => '0',
|
1610 |
|
|
en_b_i => '0',
|
1611 |
|
|
dat_b_i => to_unsigned(0,8),
|
1612 |
|
|
dat_b_o => open
|
1613 |
|
|
);
|
1614 |
|
|
flash_we <= '1' when (fsm_state=STORE_BYTE or sector_erase='1') else '0';
|
1615 |
|
|
array_adr <= flash_adr when sector_erase='0' else u_resize(erase_adr,array_adr'length);
|
1616 |
|
|
erase_adr <= reg_adr(reg_adr'length-1 downto SECTOR_BITS) & sector_adr;
|
1617 |
|
|
array_dat_wr <= sr when sector_erase='0' else str2u("FF",8);
|
1618 |
|
|
|
1619 |
|
|
end beh;
|
1620 |
|
|
|