OpenCores
URL https://opencores.org/ocsvn/wrimm/wrimm/trunk

Subversion Repositories wrimm

[/] [wrimm/] [trunk/] [Wrimm.vhd] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 barryw
--Latest version of all project files available at http://opencores.org/project,wrimm
2
--See License.txt for license details
3
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
4
--See wrimm subversion project for version history
5
 
6
library ieee;
7 4 barryw
  use ieee.std_logic_1164.all;
8
  use ieee.numeric_std.all;
9 3 barryw
library wrimm;
10 4 barryw
  use wrimm.WrimmPackage.all;
11 3 barryw
 
12 4 barryw
entity Wrimm is
13
  --generic (
14
  --  MasterParams      : WbMasterDefType;
15
  --  SlaveParams       : WbSlaveDefType;
16
  --  StatusParams      : StatusFieldDefType;
17
  --  SettingParams     : SettingFieldDefType;
18
  --  TriggerParams     : TriggerFieldDefType);
19
  port (
20
    WbClk             : in  std_logic;
21
    WbRst             : out std_logic;
22 3 barryw
 
23 4 barryw
    WbMasterIn        : in  WbMasterOutArray; --Signals from Masters
24
    WbMasterOut       : out WbSlaveOutArray;  --Signals to Masters
25
 
26
    --WbSlaveIn         : out WbMasterOutArray;
27
    --WbSlaveOut        : in  WbSlaveOutArray;
28
 
29
    StatusRegs        : in  StatusArrayType;
30
 
31
    SettingRegs       : out SettingArrayType;
32
    SettingRsts       : in  SettingArrayBitType;
33
 
34
    Triggers          : out TriggerArrayType;
35
    TriggerClr        : in  TriggerArrayType;
36
 
37
    rstZ              : in  std_logic);                         --Asynchronous reset
38
end entity Wrimm;
39
 
40
architecture behavior of Wrimm is
41
  signal  wbStrobe                : std_logic;    --Internal Wishbone signals
42
  signal  validAddress            : std_logic;
43
  signal  wbAddr                  : WbAddrType;
44
  signal  wbSData,wbMData         : WbDataType;
45
  signal  wbWrEn,wbCyc            : std_logic;
46
  signal  wbAck,wbRty,wbErr       : std_logic;
47
  --signal  wbMDataTag              : std_logic_vector(0 to 1);
48
  --signal  wbCycType               : std_logic_vector(0 to 2);
49
 
50
  signal  iSettingRegs            : SettingArrayType;
51
  signal  iTriggers               : TriggerArrayType;
52
  signal  statusEnable            : StatusArrayBitType;
53
  signal  settingEnable           : SettingArrayBitType;
54
  signal  triggerEnable           : TriggerArrayType;
55
  signal  grant                   : WbMasterGrantType;
56
 
57 3 barryw
begin
58 4 barryw
  SettingRegs <= iSettingRegs;
59
  Triggers    <= iTriggers;
60 3 barryw
 
61
--=============================================================================
62
-------------------------------------------------------------------------------
63 4 barryw
--  Master Round Robin Arbitration
64 3 barryw
-------------------------------------------------------------------------------
65 4 barryw
  procArb: process(WbClk,rstZ) is --Round robin arbitration (descending)
66
    variable vGrant : WbMasterGrantType;
67
  begin
68
    if (rstZ='0') then
69
      vGrant(vGrant'range) := (Others=>'0');
70
      vGrant(vGrant'left) := '1';
71
    elsif rising_edge(WbClk) then
72
      loopGrant: for i in WbMasterType loop
73
        if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant
74
          loopNewGrantA: for j in i to WbMasterType'right loop --last master with cyc=1 will be selected
75
            if WbMasterIn(j).Cyc='1' then
76
              vGrant    := (Others=>'0');
77
              vGrant(j) := '1';
78
            end if;
79
          end loop loopNewGrantA;
80
          if i/=WbMasterType'left then
81
            loopNewGrantB: for j in WbMasterType'left to WbMasterType'pred(i) loop
82
              if WbMasterIn(j).Cyc='1' then
83
                vGrant    := (Others=>'0');
84
                vGrant(j) := '1';
85
              end if;
86
            end loop loopNewGrantB;   --grant only moves after new requester
87
          end if;
88
        end if;
89
      end loop loopGrant;
90
      grant <= vGrant;
91
    end if; --Clk
92
  end process procArb;
93 3 barryw
--=============================================================================
94
-------------------------------------------------------------------------------
95 4 barryw
--  Master Multiplexers
96 3 barryw
-------------------------------------------------------------------------------
97 4 barryw
  procWbMasterIn: process(grant,WbMasterIn) is
98
    variable vSlaveOut    : WbMasterOutType;
99
  begin
100
    loopGrantInMux: for i in WbMasterType loop
101
      vSlaveOut := WbMasterIn(i);
102
      exit when grant(i)='1';
103
    end loop loopGrantInMux;
104
    wbStrobe    <= vSlaveOut.Strobe;
105
    wbWrEn      <= vSlaveOut.WrEn;
106
    wbAddr      <= vSlaveOut.Addr;
107
    wbMData     <= vSlaveOut.Data;
108
    --wbMDataTag  <= vSlaveOut.DataTag;
109
    wbCyc       <= vSlaveOut.Cyc;
110
    --wbCycType   <= vSlaveOut.CycType;
111
  end process procWbMasterIn;
112
  procWbMasterOut: process(grant,wbSData,wbAck,wbErr,wbRty) is
113
  begin
114
    loopGrantOutMux: for i in grant'range loop
115
      WbMasterOut(i).Ack  <= grant(i) and wbAck;
116
      WbMasterOut(i).Err  <= grant(i) and wbErr;
117
      WbMasterOut(i).Rty  <= grant(i) and wbRty;
118
      WbMasterOut(i).Data <= wbSData; --Data out can always be active.
119
    end loop loopGrantOutMux;
120
  end process procWbMasterOut;
121
 
122
  wbAck <= wbStrobe and validAddress;
123
  wbErr <= wbStrobe and not(validAddress);
124
  wbRty <= '0';
125
  WbRst <= '0';
126 3 barryw
--=============================================================================
127
-------------------------------------------------------------------------------
128 4 barryw
--  Address Decode, Asynchronous
129 3 barryw
-------------------------------------------------------------------------------
130 4 barryw
  procAddrDecode: process(wbAddr) is
131
    variable vValidAddress : std_logic;
132
  begin
133
      vValidAddress := '0';
134
      loopStatusEn: for f in StatusFieldType loop
135
        if StatusParams(f).Address=wbAddr then
136
          statusEnable(f) <= '1';
137
          vValidAddress := '1';
138
        else
139
          statusEnable(f) <= '0';
140
        end if;
141
      end loop loopStatusEn;
142
      loopSettingEn: for f in SettingFieldType loop
143
        if SettingParams(f).Address=wbAddr then
144
          settingEnable(f)  <= '1';
145
          vValidAddress := '1';
146
        else
147
          settingEnable(f)  <= '0';
148
        end if;
149
      end loop loopSettingEn;
150
      loopTriggerEn: for f in TriggerFieldType loop
151
        if TriggerParams(f).Address=wbAddr then
152
          triggerEnable(f)  <= '1';
153
          vValidAddress := '1';
154
        else
155
          triggerEnable(f)  <= '0';
156
        end if;
157
      end loop loopTriggerEn;
158
      validAddress  <= vValidAddress;
159
  end process procAddrDecode;
160 3 barryw
--=============================================================================
161
-------------------------------------------------------------------------------
162 4 barryw
--  Read
163 3 barryw
-------------------------------------------------------------------------------
164 4 barryw
  procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is
165
    variable vWbSData : WbDataType;
166
  begin
167
    vWbSData  := (Others=>'0');
168
    loopStatusRegs : for f in StatusFieldType loop
169
      if statusEnable(f)='1' then
170
        vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1);
171
      end if; --Address
172
    end loop loopStatusRegs;
173
    loopSettingRegs : for f in SettingFieldType loop
174
      if settingEnable(f)='1' then
175
        vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1);
176
      end if; --Address
177
    end loop loopSettingRegs;
178
    loopTriggerRegs : for f in TriggerFieldType loop
179
      if triggerEnable(f)='1' then
180
        vWbSData(TriggerParams(f).BitLoc) := iTriggers(f);
181
      end if; --Address
182
    end loop loopTriggerRegs;
183
    wbSData <= vWbSData;
184
  end process procRegRead;
185 3 barryw
--=============================================================================
186
-------------------------------------------------------------------------------
187 4 barryw
--  Write, Reset, Clear
188 3 barryw
-------------------------------------------------------------------------------
189 4 barryw
  procRegWrite: process(WbClk,rstZ) is
190
  begin
191
    if (rstZ='0') then
192
      loopSettingRegDefault : for f in SettingFieldType loop
193
        iSettingRegs(f) <= SettingParams(f).Default;
194
      end loop loopSettingRegDefault;
195
      loopTriggerRegDefault : for f in TriggerFieldType loop
196
        iTriggers(f)  <= '0';
197
      end loop loopTriggerRegDefault;
198
    elsif rising_edge(WbClk) then
199
      loopSettingRegWr : for f in SettingFieldType loop
200
        if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
201
          iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1));
202
        end if;
203
      end loop loopSettingRegWr;
204
      loopSettingRegRst : for f in SettingFieldType loop
205
        if SettingRsts(f)='1' then
206
          iSettingRegs(f) <= SettingParams(f).Default;
207
        end if;
208
      end loop loopSettingRegRst;
209
      loopTriggerRegWr : for f in TriggerFieldType loop
210
        if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
211
          iTriggers(f)    <= wbMData(TriggerParams(f).BitLoc);
212
        elsif TriggerClr(f)='1' then
213
          iTriggers(f)    <= '0';
214
        end if; --Address or clear
215
      end loop loopTriggerRegWr;
216
    end if; --Clk
217
  end process procRegWrite;
218
 
219 3 barryw
end architecture behavior;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.