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[/] [wrimm/] [trunk/] [Wrimm.vhd] - Blame information for rev 8

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1 8 barryw
--Propery of Tecphos Inc.  See WrimmLicense.txt for license details
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--Latest version of all Wrimm project files available at http://opencores.org/project,wrimm
3 3 barryw
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
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--See wrimm subversion project for version history
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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10 6 barryw
  use work.WrimmPackage.all;
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12 4 barryw
entity Wrimm is
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  port (
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    WbClk             : in  std_logic;
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    WbRst             : out std_logic;
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    WbMasterIn        : in  WbMasterOutArray; --Signals from Masters
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    WbMasterOut       : out WbSlaveOutArray;  --Signals to Masters
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    --WbSlaveIn         : out WbMasterOutArray;
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    --WbSlaveOut        : in  WbSlaveOutArray;
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    StatusRegs        : in  StatusArrayType;
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    SettingRegs       : out SettingArrayType;
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    SettingRsts       : in  SettingArrayBitType;
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    Triggers          : out TriggerArrayType;
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    TriggerClr        : in  TriggerArrayType;
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    rstZ              : in  std_logic);                         --Asynchronous reset
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end entity Wrimm;
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architecture behavior of Wrimm is
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  signal  wbStrobe                : std_logic;    --Internal Wishbone signals
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  signal  validAddress            : std_logic;
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  signal  wbAddr                  : WbAddrType;
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  signal  wbSData,wbMData         : WbDataType;
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  signal  wbWrEn,wbCyc            : std_logic;
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  signal  wbAck,wbRty,wbErr       : std_logic;
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  --signal  wbMDataTag              : std_logic_vector(0 to 1);
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  --signal  wbCycType               : std_logic_vector(0 to 2);
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  signal  iSettingRegs            : SettingArrayType;
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  signal  iTriggers               : TriggerArrayType;
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  signal  statusEnable            : StatusArrayBitType;
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  signal  settingEnable           : SettingArrayBitType;
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  signal  triggerEnable           : TriggerArrayType;
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  signal  grant                   : WbMasterGrantType;
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begin
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  SettingRegs <= iSettingRegs;
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  Triggers    <= iTriggers;
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--=============================================================================
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-------------------------------------------------------------------------------
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--  Master Round Robin Arbitration
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-------------------------------------------------------------------------------
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  procArb: process(WbClk,rstZ) is --Round robin arbitration (descending)
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    variable vGrant : WbMasterGrantType;
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  begin
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    if (rstZ='0') then
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      vGrant                                                            := (Others=>'0');
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      vGrant(vGrant'left)       := '1';
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    elsif rising_edge(WbClk) then
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      loopGrant: for i in WbMasterType loop
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        if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant
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          loopNewGrantA: for j in i to WbMasterType'right loop --last master with cyc=1 will be selected
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            if WbMasterIn(j).Cyc='1' then
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              vGrant    := (Others=>'0');
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              vGrant(j) := '1';
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            end if;
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          end loop loopNewGrantA;
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          if i/=WbMasterType'left then
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            loopNewGrantB: for j in WbMasterType'left to WbMasterType'pred(i) loop
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              if WbMasterIn(j).Cyc='1' then
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                vGrant    := (Others=>'0');
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                vGrant(j) := '1';
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              end if;
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            end loop loopNewGrantB;   --grant only moves after new requester
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          end if;
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        end if;
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      end loop loopGrant;
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    end if; --Clk
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    grant <= vGrant;
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  end process procArb;
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--=============================================================================
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-------------------------------------------------------------------------------
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--  Master Multiplexers
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-------------------------------------------------------------------------------
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  procWbMasterIn: process(grant,WbMasterIn) is
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    variable vSlaveOut    : WbMasterOutType;
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  begin
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    loopGrantInMux: for i in WbMasterType loop
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      vSlaveOut := WbMasterIn(i);
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      exit when grant(i)='1';
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    end loop loopGrantInMux;
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    wbStrobe    <= vSlaveOut.Strobe;
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    wbWrEn      <= vSlaveOut.WrEn;
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    wbAddr      <= vSlaveOut.Addr;
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    wbMData     <= vSlaveOut.Data;
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    --wbMDataTag  <= vSlaveOut.DataTag;
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    wbCyc       <= vSlaveOut.Cyc;
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    --wbCycType   <= vSlaveOut.CycType;
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  end process procWbMasterIn;
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  procWbMasterOut: process(grant,wbSData,wbAck,wbErr,wbRty) is
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  begin
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    loopGrantOutMux: for i in grant'range loop
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      WbMasterOut(i).Ack  <= grant(i) and wbAck;
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      WbMasterOut(i).Err  <= grant(i) and wbErr;
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      WbMasterOut(i).Rty  <= grant(i) and wbRty;
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      WbMasterOut(i).Data <= wbSData; --Data out can always be active.
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    end loop loopGrantOutMux;
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  end process procWbMasterOut;
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  wbAck <= wbStrobe and validAddress;
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  wbErr <= wbStrobe and not(validAddress);
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  wbRty <= '0';
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  WbRst <= '0';
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--=============================================================================
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-------------------------------------------------------------------------------
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--  Address Decode, Asynchronous
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-------------------------------------------------------------------------------
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  procAddrDecode: process(wbAddr) is
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    variable vValidAddress : std_logic;
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  begin
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      vValidAddress := '0';
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      loopStatusEn: for f in StatusFieldType loop
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        if StatusParams(f).Address=wbAddr then
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          statusEnable(f) <= '1';
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          vValidAddress := '1';
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        else
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          statusEnable(f) <= '0';
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        end if;
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      end loop loopStatusEn;
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      loopSettingEn: for f in SettingFieldType loop
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        if SettingParams(f).Address=wbAddr then
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          settingEnable(f)  <= '1';
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          vValidAddress := '1';
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        else
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          settingEnable(f)  <= '0';
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        end if;
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      end loop loopSettingEn;
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      loopTriggerEn: for f in TriggerFieldType loop
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        if TriggerParams(f).Address=wbAddr then
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          triggerEnable(f)  <= '1';
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          vValidAddress := '1';
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        else
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          triggerEnable(f)  <= '0';
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        end if;
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      end loop loopTriggerEn;
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      validAddress  <= vValidAddress;
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  end process procAddrDecode;
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--=============================================================================
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-------------------------------------------------------------------------------
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--  Read
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-------------------------------------------------------------------------------
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  procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is
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    variable vWbSData : WbDataType;
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  begin
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    vWbSData  := (Others=>'0');
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    loopStatusRegs : for f in StatusFieldType loop
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      if statusEnable(f)='1' then
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        vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1);
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      end if; --Address
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    end loop loopStatusRegs;
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    loopSettingRegs : for f in SettingFieldType loop
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      if settingEnable(f)='1' then
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        vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1);
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      end if; --Address
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    end loop loopSettingRegs;
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    loopTriggerRegs : for f in TriggerFieldType loop
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      if triggerEnable(f)='1' then
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        vWbSData(TriggerParams(f).BitLoc) := iTriggers(f);
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      end if; --Address
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    end loop loopTriggerRegs;
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    wbSData <= vWbSData;
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  end process procRegRead;
179 3 barryw
--=============================================================================
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-------------------------------------------------------------------------------
181 4 barryw
--  Write, Reset, Clear
182 3 barryw
-------------------------------------------------------------------------------
183 4 barryw
  procRegWrite: process(WbClk,rstZ) is
184
  begin
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    if (rstZ='0') then
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      loopSettingRegDefault : for f in SettingFieldType loop
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        iSettingRegs(f) <= SettingParams(f).Default;
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      end loop loopSettingRegDefault;
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      loopTriggerRegDefault : for f in TriggerFieldType loop
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        iTriggers(f)  <= '0';
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      end loop loopTriggerRegDefault;
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    elsif rising_edge(WbClk) then
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      loopSettingRegWr : for f in SettingFieldType loop
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        if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
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          iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1));
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        end if;
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      end loop loopSettingRegWr;
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      loopSettingRegRst : for f in SettingFieldType loop
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        if SettingRsts(f)='1' then
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          iSettingRegs(f) <= SettingParams(f).Default;
201
        end if;
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      end loop loopSettingRegRst;
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      loopTriggerRegWr : for f in TriggerFieldType loop
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        if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
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          iTriggers(f)    <= wbMData(TriggerParams(f).BitLoc);
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        elsif TriggerClr(f)='1' then
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          iTriggers(f)    <= '0';
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        end if; --Address or clear
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      end loop loopTriggerRegWr;
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    end if; --Clk
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  end process procRegWrite;
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213 3 barryw
end architecture behavior;

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