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[/] [wrimm/] [trunk/] [WrimmTestBench.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 5 barryw 
--Propery of Tecphos Inc.  See License.txt for license details
2 
--Latest version of all project files available at http://opencores.org/project,wrimm
3 
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
4 
--See wrimm subversion project for version history
5 
 
6 
library ieee;
7 
  use ieee.NUMERIC_STD.all;
8 8 barryw 
  use ieee.std_logic_1164.all;
9 
  use std.textio.all;
10 6 barryw 
 
11 
  use work.WrimmPackage.all;
12 5 barryw 
 
13 8 barryw 
entity WrimmTestBench is
14 
end WrimmTestBench;
15 
 
16 
architecture TbArch of WrimmTestBench is
17 5 barryw 
 
18 8 barryw 
  component Wrimm is
19 
    port (
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      WbClk             : in  std_logic;
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      WbRst             : out std_logic;
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      WbMasterIn        : in  WbMasterOutArray; --Signals from Masters
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      WbMasterOut       : out WbSlaveOutArray;  --Signals to Masters
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      --WbSlaveIn         : out WbMasterOutArray;
25 
      --WbSlaveOut        : in  WbSlaveOutArray;
26 
      StatusRegs        : in  StatusArrayType;
27 
      SettingRegs       : out SettingArrayType;
28 
      SettingRsts       : in  SettingArrayBitType;
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      Triggers          : out TriggerArrayType;
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      TriggerClr        : in  TriggerArrayType;
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      rstZ              : in  std_logic);        --Asynchronous reset
32 
  end component Wrimm;
33 
 
34 
  signal wbMastersOut           : WbSlaveOutArray;
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  signal wbMastersIn            : WbMasterOutArray;
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  signal statusRegs             : StatusArrayType;
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  signal settingRegs            : SettingArrayType;
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  signal settingRsts            : SettingArrayBitType;
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  signal triggers               : TriggerArrayType;
40 
  signal triggerClrs            : TriggerArrayType;
41 
 
42 
  signal rstZ                   : std_logic;
43 
  signal WishboneClock          : std_logic;
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  signal WishBoneReset          : std_logic;
45 5 barryw 
 
46 
  constant clkPeriod          : time := 0.01 us; --100 MHz
47 
 
48 8 barryw 
begin
49 
  procClk: process
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  begin
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    if WishBoneClock='1' then
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      WishBoneClock <= '0';
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    else
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      WishBoneClock <= '1';
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    end if;
56 
    wait for clkPeriod/2;
57 
  end process procClk;
58 
 
59 
  procRstZ: process
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  begin
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    rstZ  <= '0';
62 
    wait for 10 ns;
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    rstZ  <= '1';
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    wait;
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  end process procRstZ;
66 
 
67 
  instWrimm: Wrimm
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  port map(
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    WbClk             => WishboneClock,
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    WbRst             => WishboneReset,
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    WbMasterIn        => wbMastersIn,
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    WbMasterOut       => wbMastersOut,
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    --WbSlaveIn       => ,
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    --WbSlaveOut      => ,
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    StatusRegs        => statusRegs,
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    SettingRegs       => settingRegs,
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    SettingRsts       => settingRsts,
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    Triggers          => triggers,
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    TriggerClr        => triggerClrs,
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    rstZ              => rstZ);
81 
 
82 
  procStatusStim: process(WishboneClock) is
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          variable statusCount : unsigned (0 to WbDataBits-1) := (Others=>'0');
84 
        begin
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                if rising_edge(WishboneClock) then
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                        loopStatusAssign: for i in StatusFieldType loop
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                                statusRegs(i) <= std_logic_vector(statusCount);
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                                statusCount     := statusCount + 1;     --actual values don't matter, just generating unique values.
89 
                        end loop loopStatusAssign;
90 
                end if; --Clk
91 
        end process procStatusStim;
92 
 
93 
        procStatusVerify: process(WishboneClock) is
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                variable L : line;
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        begin
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                if rising_edge(WishBoneClock) then
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                        loopMasters: for i in WbMasterType loop
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                                if wbMastersOut(i).Ack='1' and wbMastersIn(i).WrEn='0' then --valid Ack to Read request
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                                        loopStatusRegs: for j in StatusFieldType loop
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                                                        if StatusParams(j).Address=wbMastersIn(i).Addr then             --correct address
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                                                                report "Evaluating Status Read" severity NOTE;
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                                                                assert (statusRegs(j)=wbMastersOut(i).data) report "Invalid Status Register Read" severity Warning;
103 
                                                        end if;
104 
                                        end loop loopStatusRegs;
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                                end if; -- valid Ack
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                        end loop loopMasters;
107 
                end if; --Clk
108 
        end process procStatusVerify;
109 
 
110 
        procSettingResets: process(WishboneClock) is
111 
                variable resetVector    : unsigned(0 to settingRsts'length-1) := (Others=>'0');
112 
                variable resetCount             : integer := 0;
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                variable resetIndex             : integer := 0;
114 
        begin
115 
                if rising_edge(WishboneClock) then
116 
                        if resetCount=20 then
117 
                                resetCount      := 0;
118 
                                resetVector := resetVector+1;
119 
                                resetIndex      := 0;
120 
                                loopSetRsts: for i in SettingFieldType loop
121 
                                        settingRsts(i)  <= resetVector(resetIndex);
122 
                                        resetIndex := resetIndex + 1;
123 
                                end loop loopSetRsts;
124 
                        else
125 
                                resetCount      := resetCount + 1;
126 
                                settingRsts     <= (Others=>'0');
127 
                        end if;
128 
                end if; --Clk
129 
        end process procSettingResets;
130 
 
131 
        procSettingMonitor: process(WishboneClock,rstZ) is
132 
                variable settingTBRegs  : SettingArrayType;
133 
        begin
134 
                if (rstZ='0') then
135 
                        loopSettingRstZ: for i in SettingFieldType loop
136 
                                settingTBRegs(i) := SettingParams(i).Default;
137 
                        end loop loopSettingRstZ;
138 
                elsif rising_edge(WishboneClock) then
139 
                        loopSettingRegsCheck : for k in SettingFieldType loop
140 
                                assert (settingTBRegs(k)=settingRegs(k))        report "Setting Reg Mismatch" severity Warning;
141 
                        end loop loopSettingRegsCheck;
142 
                        loopMasters: for i in WbMasterType loop                                                                                                 --valid Ack
143 
                                if wbMastersOut(i).Ack='1' then
144 
                                        if wbMastersIn(i).WrEn='1' then                                                                                                                 -- Write request
145 
                                                loopSettingWriteRegs: for j in SettingFieldType loop
146 
                                                        if SettingParams(j).Address=wbMastersIn(i).Addr then            --valid setting address
147 
                                                                report "Writing Setting Reg";
148 
                                                                settingTBRegs(j) := wbMastersIn(i).data;
149 
                                                        end if; --Address match
150 
                                                end loop loopSettingWriteRegs;
151 
                                        else                                                                                                                                                                                                                            -- Read request
152 
                                                loopSettingReadRegs: for j in SettingFieldType loop
153 
                                                        if SettingParams(j).Address=wbMastersIn(i).Addr then            --valid setting address
154 
                                                                report "Reading Setting Reg";
155 
                                                                assert (wbMastersOut(i).data=settingTBRegs(j)) report "Setting Read Mismatch" severity Warning;
156 
                                                        end if; --Address match
157 
                                                end loop loopSettingReadRegs;
158 
                                        end if; --WrEn
159 
                                end if; --Ack to write
160 
                        end loop loopMasters;
161 
                        loopSettingResets: for i in SettingFieldType loop
162 
                                if settingRsts(i)='1' then
163 
                                        settingTBRegs(i) := SettingParams(i).Default;
164 
                                end if;
165 
                        end loop loopSettingResets;
166 
                end if; --Clk
167 
        end process procSettingMonitor;
168 5 barryw 
 
169 8 barryw 
  procMasterStim: process(WishboneClock,rstZ) is
170 
    variable rCount             : unsigned(0 to WbAddrBits) := (Others=>'0');
171 
    variable rData              : unsigned(0 to WbDataBits-1) := (Others=>'0');
172 
    variable burstCount : integer := 5;
173 
    variable idleCount  : integer := 4;
174 
  begin
175 
    if rising_edge(WishboneClock) then
176 
                        rData                           := rData + 1;
177 
      if WbMastersOut(Q).Ack='1' or WbMastersOut(Q).Rty='1' or WbMastersOut(Q).Err='1' then
178 
        rCount                  := rCount + 1;
179 
              burstCount        := burstcount - 1;
180 
              if burstCount=0 then
181 
                      idleCount := 3;
182 
                    end if;
183 
      elsif idleCount=0 then
184 
        if burstCount=0 then
185 
          burstCount := 4;
186 
        end if;
187 
      else
188 
        idleCount := idleCount - 1;
189 
      end if;
190 
 
191 
                        wbMastersIn(Q).Data <= std_logic_vector(rData);
192 
            wbMastersIn(Q).Addr <= std_logic_vector(rCount(1 to WbAddrBits));
193 
            wbMastersIn(Q).WrEn <= rCount(0);    --read then write
194 
            if burstCount=0 then
195 
                                wbMastersIn(Q).Strobe <= '0';
196 
                          wbMastersIn(Q).Cyc            <= '0';
197 
                        else
198 
                                wbMastersIn(Q).Strobe <= '1';
199 
                                wbMastersIn(Q).Cyc              <= '1';
200 
                  end if;
201 
    end if; --Clk
202 
  end process procMasterStim;
203 5 barryw 
 
204 8 barryw 
end TbArch;

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