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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [ip_repo/] [axi_mdio/] [component.xml] - Blame information for rev 4

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Line No. Rev Author Line
1 4 DFC
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  dfcdesign.cz
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  dfc
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  mdio_master_top
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  1.1
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      S_AXI
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            AWADDR
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            S_AXI_AWADDR
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            AWPROT
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            S_AXI_AWPROT
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            AWVALID
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            S_AXI_AWVALID
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            AWREADY
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            S_AXI_AWREADY
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            WDATA
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            S_AXI_WDATA
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            WSTRB
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            S_AXI_WSTRB
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            WVALID
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            S_AXI_WVALID
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            WREADY
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            S_AXI_WREADY
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            BRESP
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            S_AXI_BRESP
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            BVALID
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            S_AXI_BVALID
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            BREADY
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            S_AXI_BREADY
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            ARADDR
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            S_AXI_ARADDR
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            ARPROT
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            S_AXI_ARPROT
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            ARVALID
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            S_AXI_ARVALID
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            ARREADY
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            S_AXI_ARREADY
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            RDATA
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            S_AXI_RDATA
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            RRESP
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            S_AXI_RRESP
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            RVALID
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            S_AXI_RVALID
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            RREADY
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            S_AXI_RREADY
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      mdio
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            MDIO_T
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            MDIO_OE
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            MDIO_O
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            MDIO_O
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            MDC
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            MDC
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            MDIO_I
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            MDIO_I
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      S_AXI_ARESETN
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            RST
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            S_AXI_ARESETN
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          POLARITY
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          ACTIVE_LOW
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      S_AXI_ACLK
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            CLK
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            S_AXI_ACLK
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          ASSOCIATED_RESET
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          S_AXI_ARESETN
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          ASSOCIATED_BUSIF
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          S_AXI
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      S_AXI
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        reg0
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        0
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        128
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        32
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        register
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        xilinx_xpgui
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        UI Layout
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        :vivado.xilinx.com:xgui.ui
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          xilinx_xpgui_view_fileset
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            viewChecksum
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            cd2c022c
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        xilinx_anylanguagesynthesis
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        Synthesis
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        :vivado.xilinx.com:synthesis
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        mdio_master_top
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          xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset
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          xilinx_anylanguagesynthesis_view_fileset
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            viewChecksum
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            8ce304eb
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        xilinx_anylanguagebehavioralsimulation
307 
        Simulation
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        :vivado.xilinx.com:simulation
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        mdio_master_top
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          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset
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          xilinx_anylanguagebehavioralsimulation_view_fileset
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            viewChecksum
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            36c8b3bc
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        S_AXI_ACLK
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          in
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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        S_AXI_ARESETN
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          in
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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        S_AXI_AWADDR
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          in
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            6
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            0
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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        S_AXI_AWPROT
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          in
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            2
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            0
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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        S_AXI_AWVALID
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          in
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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        S_AXI_AWREADY
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          out
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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        S_AXI_WDATA
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          in
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            31
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            0
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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        S_AXI_WSTRB
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          in
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            3
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            0
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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        S_AXI_WVALID
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          in
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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        S_AXI_WREADY
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          out
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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        S_AXI_BRESP
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          out
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            1
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            0
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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        S_AXI_BVALID
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          out
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
512
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        S_AXI_BREADY
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          in
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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        S_AXI_ARADDR
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          in
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            6
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            0
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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546
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            0
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        S_AXI_ARPROT
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          in
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            2
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            0
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560
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              std_logic_vector
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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            0
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572
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        S_AXI_ARVALID
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          in
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              std_logic
579 
              xilinx_anylanguagesynthesis
580 
              xilinx_anylanguagebehavioralsimulation
581
582
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            0
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        S_AXI_ARREADY
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          out
592
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              std_logic
595 
              xilinx_anylanguagesynthesis
596 
              xilinx_anylanguagebehavioralsimulation
597
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        S_AXI_RDATA
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          out
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            31
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            0
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              std_logic_vector
612 
              xilinx_anylanguagesynthesis
613 
              xilinx_anylanguagebehavioralsimulation
614
615
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617
618
619 
        S_AXI_RRESP
620
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          out
622
623 
            1
624 
            0
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              std_logic_vector
629 
              xilinx_anylanguagesynthesis
630 
              xilinx_anylanguagebehavioralsimulation
631
632
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        S_AXI_RVALID
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          out
639
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              std_logic
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              xilinx_anylanguagesynthesis
643 
              xilinx_anylanguagebehavioralsimulation
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        S_AXI_RREADY
650
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          in
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              std_logic
655 
              xilinx_anylanguagesynthesis
656 
              xilinx_anylanguagebehavioralsimulation
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            0
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664
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        MDC
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          out
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              std_logic
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              xilinx_anylanguagesynthesis
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              xilinx_anylanguagebehavioralsimulation
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675
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        MDIO_I
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          in
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              std_logic
684 
              xilinx_anylanguagesynthesis
685 
              xilinx_anylanguagebehavioralsimulation
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        MDIO_O
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          out
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              std_logic
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              xilinx_anylanguagesynthesis
698 
              xilinx_anylanguagebehavioralsimulation
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        MDIO_OE
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          out
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              std_logic
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              xilinx_anylanguagesynthesis
711 
              xilinx_anylanguagebehavioralsimulation
712
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719 
        g_add_synchronizers
720 
        G Add Synchronizers
721 
        true
722
723
724 
        C_S_AXI_DATA_WIDTH
725 
        C S Axi Data Width
726 
        32
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729 
        C_S_AXI_ADDR_WIDTH
730 
        C S Axi Addr Width
731 
        7
732
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734 
        g_include_cmd_fifo
735 
        G Include Cmd Fifo
736 
        true
737
738
739
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      choice_list_9d8b0d81
743 
      ACTIVE_HIGH
744 
      ACTIVE_LOW
745
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      xilinx_xpgui_view_fileset
750
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        xgui/mdio_master_top_v1_1.tcl
752 
        tclSource
753 
        CHECKSUM_d31de3e7
754 
        XGUI_VERSION_2
755
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      xilinx_anylanguagesynthesis_view_fileset
759
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        src/axi_mdio_master.xdc
761 
        xdc
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764 
        src/cmd_fifo/cmd_fifo.xci
765 
        xci
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        src/mdio_c.vhd
769 
        vhdlSource
770
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        src/axi_mdio_master_top.vhd
773 
        vhdlSource
774 
        CHECKSUM_4bbb4d9b
775
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      xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset
779
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787
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      xilinx_anylanguagebehavioralsimulation_view_fileset
789
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        src/cmd_fifo/cmd_fifo.xci
791 
        xci
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793
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        src/mdio_c.vhd
795 
        vhdlSource
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        USED_IN_ipstatic
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        src/axi_mdio_master_top.vhd
800 
        vhdlSource
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        USED_IN_ipstatic
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      xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset
806
807
808
809
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811
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813
814
815 
  Clause 45 MDIO master on AXI-lite
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      C_S_AXI_ADDR_WIDTH
819 
      C S Axi Addr Width
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      7
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822
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      C_S_AXI_DATA_WIDTH
824 
      C S Axi Data Width
825 
      32
826
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      Component_Name
829 
      mdio_master_top_v1_0
830
831
832 
      g_add_synchronizers
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      Add synchronizers
834 
      true
835
836
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      g_include_cmd_fifo
838 
      Include 18 level command FIFO
839 
      true
840
841
842
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        zynq
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        kintex7
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        kintex7l
848 
        qkintex7
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        qkintex7l
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        artix7
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        artix7l
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        aartix7
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        qartix7
854 
        qzynq
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        azynq
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        /UserIP
859
860 
      AXI_MDIO_MASTER
861 
      DFC Design, s.r.o.
862 
      http://www.dfcdesign.cz
863 
      6
864
865 
        dfcdesign.cz:dfc:mdio_master_top:1.0
866
867 
      2017-03-28T10:42:59Z
868
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        C:/projects/saab/high_speed_camera/firmware/ip_repo_dev/axi_mdio/trunk
870 
        C:/projects/saab/high_speed_camera/firmware/ip_repo_dev/axi_mdio/trunk
871 
        C:/projects/saab/high_speed_camera/firmware/ip_repo_dev/axi_mdio/trunk
872 
        c:/projects/saab/high_speed_camera/firmware/ip_repo_dev/axi_mdio/trunk
873 
        c:/projects/saab/high_speed_camera/firmware/ip_repo_dev/axi_mdio/trunk
874
875
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877 
      2016.4
878
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