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1 4 DFC
--
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-- crc32_gen.vhd: 32-bit CRC module processing generic number of bits in parallel
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-- Copyright (C) 2011 CESNET
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-- Author(s): Lukas Kekely <xkekel00@stud.fit.vutbr.cz> 
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in
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--    the documentation and/or other materials provided with the
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--    distribution.
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-- 3. Neither the name of the Company nor the names of its contributors
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--    may be used to endorse or promote products derived from this
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--    software without specific prior written permission.
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--
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-- This software is provided ``as is'', and any express or implied
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-- warranties, including, but not limited to, the implied warranties of
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-- merchantability and fitness for a particular purpose are disclaimed.
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-- In no event shall the company or contributors be liable for any
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-- direct, indirect, incidental, special, exemplary, or consequential
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-- damages (including, but not limited to, procurement of substitute
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-- goods or services; loss of use, data, or profits; or business
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-- interruption) however caused and on any theory of liability, whether
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-- in contract, strict liability, or tort (including negligence or
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-- otherwise) arising in any way out of the use of this software, even
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-- if advised of the possibility of such damage.
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--
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-- $Id$
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--
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-- TODO:
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--
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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use WORK.math_pack.all;
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entity crc32_gen is
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   generic(
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      DATA_WIDTH : integer := 64;
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      REG_BITMAP : integer := 0
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   );
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   port(
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      DI    : in std_logic_vector(DATA_WIDTH-1 downto 0);
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      DI_DV : in std_logic;
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      EOP   : in std_logic;
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      MASK  : in std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
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      CLK   : in std_logic;
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      RESET : in std_logic;
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      CRC   : out std_logic_vector(31 downto 0);
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      DO_DV : out std_logic
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   );
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end entity crc32_gen;
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architecture crc32_gen_arch of crc32_gen is
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   constant MW    : integer := log2(DATA_WIDTH/8);
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   signal crc_reg: std_logic_vector(DATA_WIDTH-1 downto 0);
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   signal crc_reg_input: std_logic_vector(DATA_WIDTH-1 downto 0);
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   signal tctl, deop : std_logic;
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   signal reg_low, reg_low_data, crctab_do, crctab_tree_do : std_logic_vector(31 downto 0);
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   signal mx_di, do_reg : std_logic_vector(31 downto 0);
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   signal reg_mask : std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
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   signal reg_di : std_logic_vector(DATA_WIDTH-1 downto 0);
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   signal tree_vld    : std_logic;
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begin
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   assert DATA_WIDTH >= 32 and DATA_WIDTH mod 8 = 0 report "CRC32: Wrong DATA_WIDTH set! DATA_WIDTH must be multiple of 8 and greater or equal to 32." severity error;
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   crc32_gen_tab_instance: entity work.crc32_fast_tab
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      generic map(
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         DATA_WIDTH => DATA_WIDTH
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      )
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      port map(
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         DI   => crc_reg,
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         DO   => crctab_do
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      );
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   crc32_gen_tab_tree_instance: entity work.crc32_gen_tab_tree
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      generic map(
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         DATA_WIDTH => DATA_WIDTH,
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         REG_BITMAP => REG_BITMAP
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      )
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      port map(
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         CLK   => CLK,
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         DI    => crc_reg,
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         DI_DV => deop,
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         MASK  => reg_mask,
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         DO    => crctab_tree_do,
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         DO_DV => tree_vld
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      );
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   crc32_gen_fsm_instance: entity work.crc32_gen_fsm
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   port map(
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      CLK   => CLK,
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      RESET => RESET,
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      DI_DV => DI_DV,
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      EOP   => EOP,
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      TCTL  => tctl
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   );
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   reg_di_input_long_gen  : if (DATA_WIDTH > 32)  generate
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      reg_di <= DI(DATA_WIDTH-1 downto 32) & mx_di;
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   end generate;
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   reg_di_input_short_gen : if (DATA_WIDTH <= 32) generate
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      reg_di <= mx_di(DATA_WIDTH-1 downto 0);
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   end generate;
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   crc_reg_proc: process(CLK, RESET)
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   begin
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      if RESET = '1' then
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         crc_reg <= (others => '0');
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      elsif CLK'event AND clk = '1' then
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         if DI_DV = '1' then
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            crc_reg <= crc_reg_input;
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         end if;
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      end if;
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   end process;
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   crc_di_input_long_gen  : if (DATA_WIDTH > 32)  generate
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      crc_reg_input <= reg_di(DATA_WIDTH-1 downto 32) & reg_low;
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   end generate;
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   crc_di_input_short_gen : if (DATA_WIDTH <= 32) generate
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      crc_reg_input <= reg_low(DATA_WIDTH-1 downto 0);
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   end generate;
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   process(CLK, RESET)
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   begin
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      if RESET = '1' then
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         deop <= '0';
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      elsif CLK = '1' AND CLK'event then
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         deop <= EOP and DI_DV;
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      end if;
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   end process;
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   process(CLK, RESET)
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   begin
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      if RESET = '1' then
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         DO_DV <= '0';
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      elsif CLK = '1' AND CLK'event then
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         DO_DV <= tree_vld;
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      end if;
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   end process;
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   process(CLK, RESET)
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   begin
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      if RESET = '1' then
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         do_reg <= (others => '0');
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      elsif CLK = '1' AND CLK'event then
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         do_reg <= crctab_tree_do;
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      end if;
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   end process;
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   -- register reg_mask -------------------------------------------------
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   reg_maskp: process(RESET, CLK)
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   begin
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      if (RESET = '1') then
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         reg_mask <= (others => '0');
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      elsif (CLK'event AND CLK = '1') then
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         reg_mask <= MASK;
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      end if;
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   end process;
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   -- mx_di multiplexor - handles special situation when MASK > DATA_WIDTH/8 - 4
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   mx_di <=     X"00" & DI(23 downto 0) when MASK = conv_std_logic_vector(DATA_WIDTH/8-3,MW) else
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              X"0000" & DI(15 downto 0) when MASK = conv_std_logic_vector(DATA_WIDTH/8-2,MW) else
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            X"000000" & DI( 7 downto 0) when MASK = conv_std_logic_vector(DATA_WIDTH/8-1,MW) else
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            DI(31 downto 0);
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   reg_low_data <= crctab_do XOR reg_di(31 downto 0) when (tctl = '0') else
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                   NOT reg_di(31 downto 0);
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   reg_low <= reg_low_data;
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   CRC <= NOT (do_reg(7 downto 0) & do_reg(15 downto 8) & do_reg(23 downto 16)
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               & do_reg(31 downto 24));
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end architecture;

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