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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [ip_repo/] [udp_ip_10g/] [src/] [hdl/] [srl_pkg.vhd] - Blame information for rev 4

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1 4 DFC
-------------------------------------------------------------------------------
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--
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-- (C) Copyright 2013 DFC Design, s.r.o., Brno, Czech Republic
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-- Author: Marek Kvas (m.kvas@dfcdesign.cz)
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--
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-------------------------------------------------------------------------------
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-- This file is part of UDP/IPv4 for 10 G Ethernet core.
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-- 
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-- UDP/IPv4 for 10 G Ethernet core is free software: you can 
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-- redistribute it and/or modify it under the terms of 
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-- the GNU Lesser General Public License as published by the Free 
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-- Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- 
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-- UDP/IPv4 for 10 G Ethernet core is distributed in the hope that 
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-- it will be useful, but WITHOUT ANY WARRANTY; without even 
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-- the implied warranty of MERCHANTABILITY or FITNESS FOR A 
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-- PARTICULAR PURPOSE.  See the GNU Lesser General Public License 
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-- for more details.
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-- 
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-- You should have received a copy of the GNU Lesser General Public 
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-- License along with UDP/IPv4 for 10 G Ethernet core.  If not, 
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-- see <http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------------
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--
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-- First block of the receiver chain. It has XGMII as an input.
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-- Output is raw 64 bit data guaranteed to be aligned on the frame start and 
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-- stripped of preamble and CRC, valid signal covering frame data,
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-- and byte enable signal that shall be used in case data amount is not
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-- 8 byte aligned. Another signal indicates either CRC error or line
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-- signalized error, in which case frame should be discarded.
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--
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-- Byte enable signal is guaranteed to be all ones for whole frame except
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-- for the last word, in case packet length is not 8 byte integer divisible.
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--
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-- This can work under assumption that minimum IPG in incoming stream is
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-- 4 bytes. This means when T is on L0-L4, S cannot be on L5-L7 of the same
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-- cycle and when T is on L5-L7 S cannot be on L0-L3 of the next cycle. Under
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-- this condition DV is always at leased one cycle deasserted between
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-- frames.
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--
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--
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package srl_pkg is
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   component ssrl_bus is
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   generic (
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      g_width     : positive;
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      g_delay     : positive
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           );
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   port (
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      CLK         : in  std_logic;
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      DATA_IN     : in  std_logic_vector(g_width - 1 downto 0);
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      DATA_OUT    : out std_logic_vector(g_width - 1 downto 0)
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        );
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   end component;
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   component ssrl is
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   generic (
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      g_delay     : positive
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           );
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   port (
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      CLK         : in  std_logic;
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      DATA_IN     : in  std_logic;
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      DATA_OUT    : out std_logic
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   );
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   end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ssrl_bus is
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   generic (
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      g_width     : positive;
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      g_delay     : positive
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           );
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   port (
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      CLK         : in  std_logic;
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      DATA_IN     : in  std_logic_vector(g_width - 1 downto 0);
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      DATA_OUT    : out std_logic_vector(g_width - 1 downto 0)
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        );
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end entity;
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architecture synthesis of ssrl_bus is
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   type array_slv is array (g_width-1 downto 0) of
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                        std_logic_vector(g_delay-1 downto 0);
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   signal shift_reg : array_slv;
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begin
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   shift_proc: process (CLK)
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   begin
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      if rising_edge(CLK) then
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         for i in 0 to g_width-1 loop
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             shift_reg(i) <= shift_reg(i)(g_delay-2 downto 0) & DATA_IN(i);
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         end loop;
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      end if;
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   end process;
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   output_proc : process (shift_reg)
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   begin
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      for i in 0 to g_width-1 loop
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         DATA_OUT(i) <= shift_reg(i)(g_delay-1);
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      end loop;
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   end process;
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end architecture;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.srl_pkg.all;
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entity ssrl is
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   generic (
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      g_delay     : positive
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           );
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   port (
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      CLK         : in  std_logic;
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      DATA_IN     : in  std_logic;
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      DATA_OUT    : out std_logic
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   );
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end entity;
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architecture synthesis of ssrl is
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begin
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   ssrl_bus_inst : ssrl_bus
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   generic map (
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      g_width     => 1,
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      g_delay     => g_delay
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           )
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   port map (
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      CLK         => CLK,
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      DATA_IN(0)     => DATA_IN,
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      DATA_OUT(0)    => DATA_OUT
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        );
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end architecture;
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