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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [ip_repo/] [udp_ip_10g/] [src/] [hdl/] [udp_ip_10g.vhd] - Blame information for rev 4

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1 4 DFC
-------------------------------------------------------------------------------
2
--
3
-- (C) Copyright 2017 DFC Design, s.r.o., Brno, Czech Republic
4
-- Author: Marek Kvas (m.kvas@dfcdesign.cz)
5
--
6
-------------------------------------------------------------------------------
7
-- This file is part of UDP/IPv4 for 10 G Ethernet core.
8
-- 
9
-- UDP/IPv4 for 10 G Ethernet core is free software: you can 
10
-- redistribute it and/or modify it under the terms of 
11
-- the GNU Lesser General Public License as published by the Free 
12
-- Software Foundation, either version 3 of the License, or
13
-- (at your option) any later version.
14
-- 
15
-- UDP/IPv4 for 10 G Ethernet core is distributed in the hope that 
16
-- it will be useful, but WITHOUT ANY WARRANTY; without even 
17
-- the implied warranty of MERCHANTABILITY or FITNESS FOR A 
18
-- PARTICULAR PURPOSE.  See the GNU Lesser General Public License 
19
-- for more details.
20
-- 
21
-- You should have received a copy of the GNU Lesser General Public 
22
-- License along with UDP/IPv4 for 10 G Ethernet core.  If not, 
23
-- see <http://www.gnu.org/licenses/>.
24
-------------------------------------------------------------------------------
25
--
26
-- This wrapper forms complete UDP/IP stack with both RX and TX capability.
27
-- Both RX and TX interfaces are buffered using FIFOs.
28
--
29
-- The core is aimed to be connected to 64 bit XGMII interface of Xilinx RXAUI
30
-- core or equivalent.
31
--
32
-- All ports (both RX and TX) are synchronous to single clock - CLK. It is
33
-- supposed to run at 156.25 MHz regardless of link speed. 
34
-- Because XGMII doesn't adjust frequency to link speed and there is no flow 
35
-- control mechanism embedded in XGMII protocol, UDP/IP core must be informed
36
-- what link speed is currently used through LINK_SPEED port. Available values
37
-- are as follows:
38
-- "000" - 10  Gbps
39
-- "001" - 5   Gbps
40
-- "010" - 2.5 Gbps
41
-- "011" - 1   Gbps
42
-- "100" - 100 Mbps
43
-- "101" - 10  Mbps
44
--
45
-- Speed is adjusted by insertion of inter-frame gaps. If real link speed is
46
-- higher than core is set to, no data are lost or corrupted, but speed of TX
47
-- is suboptimal. If real link speed is smaller than core is set to, some
48
-- packets may not be sent at all, or can be sent incomplete. Reception is
49
-- not dependent on this setting and will work regardless link speed.
50
--
51
-- Each path (rx and tx) contains two FIFOs. One for data and one for tags
52
-- that describe what is stored in data FIFO. Data FIFOs have both 
53
-- width 72 bits - 64 bit data + 8 bit byte enables. Tag FIFOs differ.
54
-- TX tag fifo is 16 bits wide, RX tag fifo 34 bits wide.
55
-- In both paths whole datagram must be stored in FIFO before it is transmitted
56
-- to network(tx) or provided to user(rx).
57
-- Depth of each FIFO can be set by user. Data FIFO must be at least deep
58
-- enough to contain one the largest packet that can appear on network.
59
-- In most cases MTU is either 1500 or 9000 bytes. So 1500/8 = 187 and
60
-- 9000/8 = 1125 are minimal depths for data FIFOs.
61
-- Depth of tag fifos depends on maximum number of datagrams that are expected
62
-- to be buffered in data FIFO at once. For tx tag fifo one word is used for
63
-- each buffered packet. For rx three words of tag FIFO are used per each
64
-- buffered packets.
65
-- User can also select technology used to implelent FIFOs. Type can be
66
-- either selected automatically by Vivado tools ("auto") or it can be
67
-- implemented in block RAMs ("block") or as distributed memory in LUTs
68
-- ("distributed"). FIFOs are instances of Xilinx Parametrized Macros.
69
-- Each project that uses this macros must have XPM libraries enabled.
70
-- This can be done with tcl command:
71
-- set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
72
--
73
-------------------------------------------------------------------------------
74
 
75
library ieee;
76
use ieee.std_logic_1164.all;
77
use ieee.numeric_std.all;
78
 
79
-----
80
-- These are Xilinx parametrized macro libraries. It is used to 
81
-- Instantiate FIFOs without the need to create sub-IP
82
-- They also support setting depth and type in generics
83
--
84
-- If new project is created and these macros should be used TCL command
85
-- set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
86
-- must be used to enable their usage.
87
----------------------
88
Library xpm;
89
use xpm.vcomponents.all;
90
 
91
library work;
92
use work.frame_pkg.all;
93
 
94
 
95
entity udp_ip_10g is
96
   generic (
97
      g_tx_dfifo_depth  : integer := 2048; -- 72 bit data width (8 data bytes)
98
      g_tx_tfifo_depth  : integer := 128;  -- 16 bit data width
99
      g_rx_dfifo_depth  : integer := 2048; -- 72 bit data width (8 data bytes)
100
      g_rx_tfifo_depth  : integer := 128;  -- 34 bit data width
101
      g_tx_dfifo_type   : string  := "block"; -- auto, block, distributed
102
      g_tx_tfifo_type   : string  := "block";
103
      g_rx_dfifo_type   : string  := "block";
104
      g_rx_tfifo_type   : string  := "block"
105
           );
106
   port (
107
      RST               : in  std_logic;
108
      CLK               : in  std_logic;
109
 
110
      -- General control signals
111
      LINK_SPEED        : in  std_logic_vector(2 downto 0);
112
 
113
 
114
      -- Host information user interface
115
      HOST_MAC          : in  std_logic_vector(47 downto 0);
116
      HOST_IP           : in  std_logic_vector(31 downto 0);
117
      HOST_IP_NETMASK   : in  std_logic_vector(31 downto 0);
118
 
119
      -- TX user interface
120
      TX_DST_MAC        : in  std_logic_vector(47 downto 0);
121
      TX_DST_IP         : in  std_logic_vector(31 downto 0);
122
      TX_SRC_UDP        : in  std_logic_vector(15 downto 0);
123
      TX_DST_UDP        : in  std_logic_vector(15 downto 0);
124
 
125
      TX_FRAME_VALID    : in  std_logic;
126
      TX_FRAME_RDY      : out std_logic;
127
      TX_FRAME_LAST     : in  std_logic;
128
      TX_FRAME_BE       : in  std_logic_vector(7 downto 0);
129
      TX_FRAME_DATA     : in  std_logic_vector(63 downto 0);
130
 
131
      -- RX user interface
132
      RX_SRC_MAC        : out std_logic_vector(47 downto 0);
133
      RX_SRC_IP         : out std_logic_vector(31 downto 0);
134
      RX_SRC_UDP        : out std_logic_vector(15 downto 0);
135
      RX_DST_UDP        : out std_logic_vector(15 downto 0);
136
 
137
      RX_FRAME_VALID    : out std_logic;
138
      RX_FRAME_RDY      : in  std_logic;
139
      RX_FRAME_LAST     : out std_logic;
140
      RX_FRAME_BE       : out std_logic_vector(7 downto 0);
141
      RX_FRAME_DATA     : out std_logic_vector(63 downto 0);
142
      RX_FRAME_LENGTH   : out std_logic_vector(15 downto 0);
143
 
144
      -- XGMII interface
145
      XGMII_TXC         : out std_logic_vector(7 downto 0);
146
      XGMII_TXD         : out std_logic_vector(63 downto 0);
147
      XGMII_RXC         : in  std_logic_vector(7 downto 0);
148
      XGMII_RXD         : in  std_logic_vector(63 downto 0)
149
 
150
 
151
        );
152
end entity;
153
 
154
 
155
architecture synthesis of udp_ip_10g is
156
 
157
   signal rst_cnt             : integer range 0 to 15 := 0;
158
   signal rst_internal        : std_logic := '1';
159
 
160
-----------------------------------------------------------------------------
161
-- TX Path internal connection signals
162
-----------------------------------------------------------------------------
163
 
164
   signal txi_wr_dfifo_data   : txi_dfifo_data_type;
165
   signal txi_wr_dfifo_wr_en  : std_logic;
166
   signal txi_wr_dfifo_full   : std_logic;
167
 
168
   signal txi_wr_tfifo_data   : txi_tfifo_data_type;
169
   signal txi_wr_tfifo_wr_en  : std_logic;
170
   signal txi_wr_tfifo_full   : std_logic;
171
 
172
   signal txi_rd_dfifo_data   : txi_dfifo_data_type;
173
   signal txi_rd_dfifo_rd_en  : std_logic;
174
   signal txi_rd_dfifo_empty  : std_logic;
175
 
176
   signal txi_rd_tfifo_data   : txi_tfifo_data_type;
177
   signal txi_rd_tfifo_rd_en  : std_logic;
178
   signal txi_rd_tfifo_empty  : std_logic;
179
 
180
 
181
   signal fg_tx_en            : std_logic;
182
   signal fg_busy             : std_logic;
183
   signal fg_idle_ifg         : std_logic;
184
   signal fg_busy_throttled   : std_logic;
185
   signal fg_data_ren         : std_logic;
186
   signal fg_data_in          : std_logic_vector(63 downto 0);
187
   signal fg_data_len         : std_logic_vector(15 downto 0);
188
   signal fg_dst_mac          : std_logic_vector(47 downto 0);
189
   signal fg_dst_ip           : std_logic_vector(31 downto 0);
190
   signal fg_src_port         : std_logic_vector(15 downto 0);
191
   signal fg_dst_port         : std_logic_vector(15 downto 0);
192
 
193
-----------------------------------------------------------------------------
194
-- RX Path internal connection signals
195
-----------------------------------------------------------------------------
196
 
197
 
198
   signal frx_wr_dfifo_data   : fp_dfifo_data_type;
199
   signal frx_wr_dfifo_wr_en  : std_logic;
200
   signal frx_wr_dfifo_full   : std_logic := '0';
201
 
202
   signal frx_wr_tfifo_data   : fp_tfifo_data_type;
203
   signal frx_wr_tfifo_wr_en  : std_logic;
204
   signal frx_wr_tfifo_full   : std_logic := '0';
205
 
206
   signal frx_rd_dfifo_data   : fp_dfifo_data_type;
207
   signal frx_rd_dfifo_rd_en  : std_logic;
208
   signal frx_rd_dfifo_empty  : std_logic;
209
   signal frx_rd_tfifo_data   : fp_tfifo_data_type;
210
   signal frx_rd_tfifo_rd_en  : std_logic;
211
   signal frx_rd_tfifo_empty  : std_logic;
212
 
213
   signal fr_rx_data          : std_logic_vector(63 downto 0);
214
   signal fr_rx_dv            : std_logic;
215
   signal fr_rx_be            : std_logic_vector(7 downto 0);
216
   signal fr_rx_err           : std_logic;
217
   signal fr_rx_err_valid     : std_logic;
218
 
219
 
220
begin
221
 
222
   -- Reset should take at least 16 cycles to flush pipeline
223
   rst_proc : process (CLK)
224
   begin
225
      if rising_edge(CLK) then
226
         if RST = '1' then
227
            rst_cnt <= 0;
228
            rst_internal <= '1';
229
         elsif rst_cnt < 15 then
230
            rst_cnt <= rst_cnt + 1;
231
            rst_internal <= '1';
232
         else
233
            rst_internal <= '0';
234
         end if;
235
      end if;
236
   end process;
237
 
238
-----------------------------------------------------------------------------
239
-- TX Path
240
-----------------------------------------------------------------------------
241
 
242
   frame_tx_if_inst : entity work.frame_tx_if
243
   port map(
244
      CLK            => CLK,
245
      RST            => rst_internal,
246
 
247
      DST_MAC        => TX_DST_MAC,
248
      DST_IP         => TX_DST_IP,
249
      SRC_UDP        => TX_SRC_UDP,
250
      DST_UDP        => TX_DST_UDP,
251
 
252
      FRAME_VALID    => TX_FRAME_VALID,
253
      FRAME_RDY      => TX_FRAME_RDY,
254
      FRAME_LAST     => TX_FRAME_LAST,
255
      FRAME_BE       => TX_FRAME_BE,
256
      FRAME_DATA     => TX_FRAME_DATA,
257
 
258
      -- Tag and data fifos
259
      DFIFO_DATA     => txi_wr_dfifo_data,
260
      DFIFO_WR_EN    => txi_wr_dfifo_wr_en,
261
      DFIFO_FULL     => txi_wr_dfifo_full,
262
 
263
      TFIFO_DATA     => txi_wr_tfifo_data,
264
      TFIFO_WR_EN    => txi_wr_tfifo_wr_en,
265
      TFIFO_FULL     => txi_wr_tfifo_full
266
        );
267
 
268
   txi_dfifo_inst : xpm_fifo_sync
269
   generic map (
270
      FIFO_MEMORY_TYPE           => g_tx_dfifo_type,
271
      ECC_MODE                   => "no_ecc",
272
      FIFO_WRITE_DEPTH           => g_tx_dfifo_depth,
273
      WRITE_DATA_WIDTH           => txi_dfifo_data_type'length,
274
      WR_DATA_COUNT_WIDTH        => 1,
275
      PROG_FULL_THRESH           => 10,
276
      FULL_RESET_VALUE           => 0,
277
      READ_MODE                  => "fwft",
278
      FIFO_READ_LATENCY          => 0,
279
      READ_DATA_WIDTH            => txi_dfifo_data_type'length,
280
      RD_DATA_COUNT_WIDTH        => 1,
281
      PROG_EMPTY_THRESH          => 10,
282
      DOUT_RESET_VALUE           => "0",
283
      WAKEUP_TIME                => 0
284
   )
285
   port map (
286
      rst                        => rst_internal,
287
      wr_clk                     => CLK,
288
      wr_en                      => txi_wr_dfifo_wr_en,
289
      din                        => txi_wr_dfifo_data,
290
      full                       => txi_wr_dfifo_full,
291
      overflow                   => open,
292
      wr_rst_busy                => open,
293
      rd_en                      => txi_rd_dfifo_rd_en,
294
      dout                       => txi_rd_dfifo_data,
295
      empty                      => txi_rd_dfifo_empty,
296
      underflow                  => open,
297
      rd_rst_busy                => open,
298
      prog_full                  => open,
299
      wr_data_count              => open,
300
      prog_empty                 => open,
301
      rd_data_count              => open,
302
      sleep                      => '0',
303
      injectsbiterr              => '0',
304
      injectdbiterr              => '0',
305
      sbiterr                    => open,
306
      dbiterr                    => open
307
   );
308
 
309
   txi_tfifo_inst : xpm_fifo_sync
310
   generic map (
311
      FIFO_MEMORY_TYPE           => g_tx_tfifo_type,
312
      ECC_MODE                   => "no_ecc",
313
      FIFO_WRITE_DEPTH           => g_tx_tfifo_depth,
314
      WRITE_DATA_WIDTH           => txi_wr_tfifo_data'length,
315
      WR_DATA_COUNT_WIDTH        => 1,
316
      PROG_FULL_THRESH           => 10,
317
      FULL_RESET_VALUE           => 0,
318
      READ_MODE                  => "fwft",
319
      FIFO_READ_LATENCY          => 0,
320
      READ_DATA_WIDTH            => txi_wr_tfifo_data'length,
321
      RD_DATA_COUNT_WIDTH        => 1,
322
      PROG_EMPTY_THRESH          => 10,
323
      DOUT_RESET_VALUE           => "0",
324
      WAKEUP_TIME                => 0
325
   )
326
   port map (
327
      rst                        => rst_internal,
328
      wr_clk                     => CLK,
329
      wr_en                      => txi_wr_tfifo_wr_en,
330
      din                        => txi_wr_tfifo_data,
331
      full                       => txi_wr_tfifo_full,
332
      overflow                   => open,
333
      wr_rst_busy                => open,
334
      rd_en                      => txi_rd_tfifo_rd_en,
335
      dout                       => txi_rd_tfifo_data,
336
      empty                      => txi_rd_tfifo_empty,
337
      underflow                  => open,
338
      rd_rst_busy                => open,
339
      prog_full                  => open,
340
      wr_data_count              => open,
341
      prog_empty                 => open,
342
      rd_data_count              => open,
343
      sleep                      => '0',
344
      injectsbiterr              => '0',
345
      injectdbiterr              => '0',
346
      sbiterr                    => open,
347
      dbiterr                    => open
348
    );
349
 
350
 
351
   frame_gen_fifo_if_inst : entity work.frame_gen_fifo_if
352
   port map (
353
      CLK            => clk,
354
 
355
      DST_MAC        => fg_dst_mac,
356
      DST_IP         => fg_dst_ip,
357
      SRC_UDP        => fg_src_port,
358
      DST_UDP        => fg_dst_port,
359
 
360
      -- Frame generator if
361
      FG_TX_EN       => fg_tx_en,
362
      FG_BUSY        => fg_busy_throttled,
363
      FG_DATA_REN    => fg_data_ren,
364
      FG_DATA_IN     => fg_data_in,
365
      FG_DATA_LEN    => fg_data_len,
366
 
367
      -- Tag and data fifos
368
      DFIFO_DATA     => txi_rd_dfifo_data,
369
      DFIFO_RD_EN    => txi_rd_dfifo_rd_en,
370
      DFIFO_EMPTY    => txi_rd_dfifo_empty,
371
 
372
      TFIFO_DATA     => txi_rd_tfifo_data,
373
      TFIFO_RD_EN    => txi_rd_tfifo_rd_en,
374
      TFIFO_EMPTY    => txi_rd_tfifo_empty
375
 
376
        );
377
 
378
   frame_throttle_inst : entity work.frame_throttle
379
   port map (
380
      CLK            => clk,
381
      LINK_SPEED     => LINK_SPEED,
382
 
383
      FG_BUSY        => fg_busy,
384
      FG_IDLE_IFG    => fg_idle_ifg,
385
      BUSY_THROTTLED => fg_busy_throttled
386
   );
387
 
388
 
389
   -- Frame generator
390
   frame_gen_inst : entity work.frame_gen
391
   port map (
392
      RESET       => rst_internal,
393
      TX_EN       => fg_tx_en,
394
      BUSY        => fg_busy,
395
      IDLE_IFG    => fg_idle_ifg,
396
      DATA_REN    => fg_data_ren,
397
      DATA_IN     => fg_data_in,
398
      DATA_LEN    => fg_data_len,
399
      SRC_MAC     => HOST_MAC,
400
      DST_MAC     => fg_dst_mac,
401
      SRC_IP      => HOST_IP,
402
      DST_IP      => fg_dst_ip,
403
      SRC_PORT    => fg_src_port,
404
      DST_PORT    => fg_dst_port,
405
      TX_CLK      => clk,
406
      TXD         => XGMII_TXD,
407
      TXC         => XGMII_TXC
408
   );
409
-----------------------------------------------------------------------------
410
-- RX Path
411
-----------------------------------------------------------------------------
412
 
413
     -- Frame receiver
414
   frame_receiver_inst : entity work.frame_receiver
415
   port map (
416
      RST               => rst_internal,
417
 
418
      -- XGMII RX input interface
419
      XGMII_RXCLK       => CLK,
420
      XGMII_RXD         => XGMII_RXD,
421
      XGMII_RXC         => XGMII_RXC,
422
 
423
       -- Output interface
424
      RX_DATA           => fr_rx_data,
425
      RX_DV             => fr_rx_dv,
426
      RX_BE             => fr_rx_be,
427
      RX_ERR            => fr_rx_err,
428
      RX_ERR_VALID      => fr_rx_err_valid
429
        );
430
 
431
    -- Frame process
432
   frame_process_inst : entity work.frame_process
433
   port map (
434
      RST               => rst_internal,
435
      CLK               => CLK,
436
 
437
      -- Interface towards frame receiver
438
      RX_DATA           => fr_rx_data,
439
      RX_DV             => fr_rx_dv,
440
      RX_BE             => fr_rx_be,
441
      RX_ERR            => fr_rx_err,
442
      RX_ERR_VALID      => fr_rx_err_valid,
443
 
444
      DFIFO_DATA        => frx_wr_dfifo_data,
445
      DFIFO_WR_EN       => frx_wr_dfifo_wr_en,
446
      DFIFO_FULL        => frx_wr_dfifo_full,
447
 
448
      TFIFO_DATA        => frx_wr_tfifo_data,
449
      TFIFO_WR_EN       => frx_wr_tfifo_wr_en,
450
      TFIFO_FULL        => frx_wr_tfifo_full,
451
 
452
      MAC_ADDR          => HOST_MAC,
453
      IP_ADDR           => HOST_IP,
454
      IP_NET_MASK       => HOST_IP_NETMASK
455
        );
456
 
457
   rx_dfifo_inst : xpm_fifo_sync
458
   generic map (
459
      FIFO_MEMORY_TYPE           => g_rx_dfifo_type,
460
      ECC_MODE                   => "no_ecc",
461
      FIFO_WRITE_DEPTH           => g_rx_dfifo_depth,
462
      WRITE_DATA_WIDTH           => fp_dfifo_data_type'length,
463
      WR_DATA_COUNT_WIDTH        => 1,
464
      PROG_FULL_THRESH           => 10,
465
      FULL_RESET_VALUE           => 0,
466
      READ_MODE                  => "fwft",
467
      FIFO_READ_LATENCY          => 0,
468
      READ_DATA_WIDTH            => fp_dfifo_data_type'length,
469
      RD_DATA_COUNT_WIDTH        => 1,
470
      PROG_EMPTY_THRESH          => 10,
471
      DOUT_RESET_VALUE           => "0",
472
      WAKEUP_TIME                => 0
473
   )
474
   port map (
475
      rst                        => rst_internal,
476
      wr_clk                     => CLK,
477
      wr_en                      => frx_wr_dfifo_wr_en,
478
      din                        => frx_wr_dfifo_data,
479
      full                       => frx_wr_dfifo_full,
480
      overflow                   => open,
481
      wr_rst_busy                => open,
482
      rd_en                      => frx_rd_dfifo_rd_en,
483
      dout                       => frx_rd_dfifo_data,
484
      empty                      => frx_rd_dfifo_empty,
485
      underflow                  => open,
486
      rd_rst_busy                => open,
487
      prog_full                  => open,
488
      wr_data_count              => open,
489
      prog_empty                 => open,
490
      rd_data_count              => open,
491
      sleep                      => '0',
492
      injectsbiterr              => '0',
493
      injectdbiterr              => '0',
494
      sbiterr                    => open,
495
      dbiterr                    => open
496
   );
497
 
498
   rx_tfifo_inst : xpm_fifo_sync
499
   generic map (
500
      FIFO_MEMORY_TYPE           => g_rx_tfifo_type,
501
      ECC_MODE                   => "no_ecc",
502
      FIFO_WRITE_DEPTH           => g_rx_tfifo_depth,
503
      WRITE_DATA_WIDTH           => frx_wr_tfifo_data'length,
504
      WR_DATA_COUNT_WIDTH        => 1,
505
      PROG_FULL_THRESH           => 10,
506
      FULL_RESET_VALUE           => 0,
507
      READ_MODE                  => "fwft",
508
      FIFO_READ_LATENCY          => 0,
509
      READ_DATA_WIDTH            => frx_wr_tfifo_data'length,
510
      RD_DATA_COUNT_WIDTH        => 1,
511
      PROG_EMPTY_THRESH          => 10,
512
      DOUT_RESET_VALUE           => "0",
513
      WAKEUP_TIME                => 0
514
   )
515
   port map (
516
      rst                        => rst_internal,
517
      wr_clk                     => CLK,
518
      wr_en                      => frx_wr_tfifo_wr_en,
519
      din                        => frx_wr_tfifo_data,
520
      full                       => frx_wr_tfifo_full,
521
      overflow                   => open,
522
      wr_rst_busy                => open,
523
      rd_en                      => frx_rd_tfifo_rd_en,
524
      dout                       => frx_rd_tfifo_data,
525
      empty                      => frx_rd_tfifo_empty,
526
      underflow                  => open,
527
      rd_rst_busy                => open,
528
      prog_full                  => open,
529
      wr_data_count              => open,
530
      prog_empty                 => open,
531
      rd_data_count              => open,
532
      sleep                      => '0',
533
      injectsbiterr              => '0',
534
      injectdbiterr              => '0',
535
      sbiterr                    => open,
536
      dbiterr                    => open
537
    );
538
 
539
   frame_rx_if_inst : entity work.frame_rx_if
540
   port map (
541
      RST            => rst_internal,
542
      CLK            => clk,
543
 
544
      FRAME_VALID    => RX_FRAME_VALID,
545
      FRAME_RD_EN    => RX_FRAME_RDY,
546
      FRAME_LENGTH   => RX_FRAME_LENGTH,
547
      FRAME_LAST     => RX_FRAME_LAST,
548
      FRAME_BE       => RX_FRAME_BE,
549
      FRAME_DATA     => RX_FRAME_DATA,
550
      SRC_MAC        => RX_SRC_MAC,
551
      SRC_IP         => RX_SRC_IP,
552
      SRC_UDP        => RX_SRC_UDP,
553
      DST_UDP        => RX_DST_UDP,
554
 
555
 
556
      -- Tag and data fifos
557
      DFIFO_DATA     => frx_rd_dfifo_data,
558
      DFIFO_RD_EN    => frx_rd_dfifo_rd_en,
559
      DFIFO_EMPTY    => frx_rd_dfifo_empty,
560
 
561
      TFIFO_DATA     => frx_rd_tfifo_data,
562
      TFIFO_RD_EN    => frx_rd_tfifo_rd_en,
563
      TFIFO_EMPTY    => frx_rd_tfifo_empty
564
        );
565
 
566
 
567
end architecture;
568
 
569
 
570
 
571
 
572
 
573
 
574
 

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