OpenCores
URL https://opencores.org/ocsvn/xenie/xenie/trunk

Subversion Repositories xenie

[/] [xenie/] [trunk/] [examples/] [Eth_example/] [mb_fw/] [drivers/] [iic_v3_4/] [examples/] [xiic_eeprom_example.c] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 DFC
/******************************************************************************
2
*
3
* Copyright (C) 2006 - 2014 Xilinx, Inc.  All rights reserved.
4
*
5
* Permission is hereby granted, free of charge, to any person obtaining a copy
6
* of this software and associated documentation files (the "Software"), to deal
7
* in the Software without restriction, including without limitation the rights
8
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9
* copies of the Software, and to permit persons to whom the Software is
10
* furnished to do so, subject to the following conditions:
11
*
12
* The above copyright notice and this permission notice shall be included in
13
* all copies or substantial portions of the Software.
14
*
15
* Use of the Software is limited solely to applications:
16
* (a) running on a Xilinx device, or
17
* (b) that interact with a Xilinx device through a bus or interconnect.
18
*
19
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25
* SOFTWARE.
26
*
27
* Except as contained in this notice, the name of the Xilinx shall not be used
28
* in advertising or otherwise to promote the sale, use or other dealings in
29
* this Software without prior written authorization from Xilinx.
30
*
31
******************************************************************************/
32
/*****************************************************************************/
33
/**
34
* @file xiic_eeprom_example.c
35
*
36
* This file consists of a Interrupt mode design example which uses the Xilinx
37
* IIC device and XIic driver to exercise the EEPROM. The XIic driver uses the
38
* complete FIFO functionality to transmit/receive data.
39
*
40
* This example writes/reads from the lower 256 bytes of the IIC EEPROMS. Please
41
* refer to the datasheets of the IIC EEPROM's for details about the internal
42
* addressing and page size of these devices.
43
*
44
* The XIic_MasterSend() API is used to transmit the data and
45
* XIic_MasterRecv() API is used to receive the data.
46
*
47
* This example is tested on ML300/ML310/ML410/ML403/ML501/ML507/ML510/ML605/
48
* SP601, SP605, KC705 , ZC702 and ZC706  Xilinx boards.
49
*
50
* The ML310/ML510/ML410 boards have a on-board 64 Kb serial IIC EEPROM
51
* (Microchip 24LC64A). The WP pin of the IIC EEPROM is hardwired to ground on
52
* this board.
53
*
54
* The ML300 board has an on-board 32 Kb serial IIC EEPROM(Microchip 24LC32A).
55
* The WP pin of the IIC EEPROM has to be connected to ground for this example.
56
* The WP is connected to pin Y3 of the FPGA.
57
*
58
* The ML403 board has an on-board 4 Kb serial IIC EEPROM(Microchip 24LC04A).
59
* The WP pin of the IIC EEPROM is hardwired to ground on this board.
60
*
61
* The ML501/ML505/ML507/ML605/SP601/SP605/KC705/ZC702/ZC706 boards have an
62
* on-board 8 Kb serial IIC EEPROM(STM M24C08). The WP pin of the IIC EEPROM is
63
* hardwired to ground on these boards.
64
*
65
* The AddressType for ML300/ML310/ML410/ML510 boards should be u16 as the
66
* address pointer in the on board EEPROM is 2 bytes.
67
*
68
* The AddressType for ML403/ML501/ML505/ML507/ML605/SP601/SP605/KC705/ZC702/
69
* ZC706 boards should be u8 as the address pointer for the on board EEPROM
70
* is 1 byte.
71
*
72
* The 7 bit IIC Slave address of the IIC EEPROM on the ML300/ML310/ML403/ML410/
73
* ML501/ML505/ML507/ML510 boards is 0x50.
74
* The 7 bit IIC Slave address of the IIC EEPROM on the ML605/SP601/SP605/KC705
75
* /ZC702/ZC706 boards is 0x54.
76
* Refer to the User Guide's of the respective boards for further information
77
* about the IIC slave address of IIC EEPROM's.
78
*
79
* The define EEPROM_ADDRESS in this file needs to be changed depending on
80
* the board on which this example is to be run. This is the IIC address of the
81
* EEPROM.
82
*
83
* The define IIC_MUX_ADDRESS in this file needs to be changed depending on
84
* the board on which this example is to be run. This is the IIC address of the
85
* the MUX.
86
*
87
* The define IIC_MUX_ENABLE should be defined so that the IIC Mux initialization
88
* is done for the boards on the which the EEPROM is connected to an IIC Mux.
89
* The boards with a MUX are a KC705/ZC702/ZC706.
90
*
91
* The define IIC_EEPROM_CHANNEL needs to be changed depending on the Channel
92
* number of EEPROM for IIC Mux. On KC705 it is 0x08 and ZC702 is 0x04. Please
93
* refer the User Guide's of the respective boards for further information
94
* about the Channel number to use EEPROM.
95
*
96
* This code assumes that no Operating System is being used.
97
*
98
*
99
* @note
100
*
101
* None.
102
*
103
* <pre>
104
* MODIFICATION HISTORY:
105
*
106
* Ver   Who  Date        Changes
107
* ----- ---- -------- ---------------------------------------------------------
108
* 1.00a mta  02/24/06 Created.
109
* 1.00a mta  04/05/07 Added support for microblaze.
110
* 2.00a ktn  11/17/09 Updated to use the HAL APIs and replaced call to
111
*                     XIic_Initialize API with XIic_LookupConfig and
112
*                     XIic_CfgInitialize.
113
* 2.01a ktn  03/17/10 Updated the information about the EEPROM's used on
114
*                     ML605/SP601/SP605 boards. Updated the example so that it
115
*                     can be used to access the entire IIC EEPROM for devices
116
*                     like M24C04/M24C08 that use LSB bits of the IIC device
117
*                     select code (IIC slave address) to specify the higher
118
*                     address bits of the EEPROM internal address.
119
* 2.02a bss  01/30/13 Updated for using the GIC in case of Zynq
120
* 2.06a bss  02/14/13 Added MuxInit API to support Zynq and KC705 boards and
121
*                     modified to use ScuGic in case of Zynq CR# 683509
122
*
123
* </pre>
124
*
125
******************************************************************************/
126
 
127
/***************************** Include Files *********************************/
128
 
129
#include "xparameters.h"
130
#include "xiic.h"
131
#include "xil_exception.h"
132
 
133
#ifdef XPAR_INTC_0_DEVICE_ID
134
 #include "xintc.h"
135
#else
136
 #include "xscugic.h"
137
#endif
138
 
139
/************************** Constant Definitions *****************************/
140
 
141
/*
142
 * The following constants map to the XPAR parameters created in the
143
 * xparameters.h file. They are defined here such that a user can easily
144
 * change all the needed parameters in one place.
145
 */
146
#define IIC_DEVICE_ID   XPAR_IIC_0_DEVICE_ID
147
 
148
 
149
 
150
#ifdef XPAR_INTC_0_DEVICE_ID
151
 #define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
152
 #define IIC_INTR_ID    XPAR_INTC_0_IIC_0_VEC_ID
153
 #define INTC                   XIntc
154
 #define INTC_HANDLER   XIntc_InterruptHandler
155
#else
156
 #define INTC_DEVICE_ID         XPAR_SCUGIC_SINGLE_DEVICE_ID
157
 #define IIC_INTR_ID            XPAR_FABRIC_IIC_0_VEC_ID
158
 #define INTC                           XScuGic
159
 #define INTC_HANDLER           XScuGic_InterruptHandler
160
#endif
161
 
162
 
163
/*
164
 * The following constant defines the address of the IIC Slave device on the
165
 * IIC bus. Note that since the address is only 7 bits, this constant is the
166
 * address divided by 2.
167
 * The 7 bit IIC Slave address of the IIC EEPROM on the ML300/ML310/ML403/ML410/
168
 * ML501/ML505/ML507/ML510 boards is 0x50. The 7 bit IIC Slave address of the
169
 * IIC EEPROM on the ML605/SP601/SP605/KC705/ZC702/ZC706 boards is 0x54.
170
 * Please refer the User Guide's of the respective boards for further
171
 * information about the IIC slave address of IIC EEPROM's.
172
 */
173
#define EEPROM_ADDRESS          0x54    /* 0xA0 as an 8 bit number. */
174
 
175
 
176
/*
177
 * The IIC_MUX_ADDRESS defines the address of the IIC MUX device on the
178
 * IIC bus. Note that since the address is only 7 bits, this constant is the
179
 * address divided by 2.
180
 * The IIC Slaves on the KC705/ZC702/ZC706 boards are connected to an
181
 * IIC MUX.
182
 * IIC_EEPROM_CHANNEL is the Channel number of EEPROM for IIC Mux. On KC705 it
183
 * is 0x08 and ZC702 is 0x04.Please refer the User Guide's of the respective
184
 * boards for further information about the Channel number to use EEPROM.
185
 */
186
#define IIC_MUX_ADDRESS                 0x74
187
#define IIC_EEPROM_CHANNEL              0x08
188
 
189
/*
190
 * This define should be uncommented if there is IIC MUX on the board to which
191
 * this EEPROM is connected. The boards that have IIC MUX are KC705/ZC702/ZC706.
192
 */
193
/* #define IIC_MUX_ENABLE */
194
 
195
/*
196
 * The page size determines how much data should be written at a time.
197
 * The ML310/ML300 board supports a page size of 32 and 16.
198
 * The write function should be called with this as a maximum byte count.
199
 */
200
#define PAGE_SIZE   16
201
 
202
/*
203
 * The Starting address in the IIC EEPROM on which this test is performed.
204
 */
205
#define EEPROM_TEST_START_ADDRESS   128
206
 
207
/**************************** Type Definitions *******************************/
208
 
209
/*
210
 * The AddressType for ML300/ML310/ML410/ML510 boards should be u16 as the address
211
 * pointer in the on board EEPROM is 2 bytes.
212
 * The AddressType for ML403/ML501/ML505/ML507/ML605/SP601/SP605/KC705/ZC702
213
 * /ZC706 boards should be u8 as the address pointer in the on board EEPROM is
214
 * 1 bytes.
215
 */
216
typedef u8 AddressType;
217
 
218
/***************** Macros (Inline Functions) Definitions *********************/
219
 
220
/************************** Function Prototypes ******************************/
221
 
222
int IicEepromExample();
223
 
224
int EepromWriteData(u16 ByteCount);
225
 
226
int EepromReadData(u8 *BufferPtr, u16 ByteCount);
227
 
228
static int SetupInterruptSystem(XIic *IicInstPtr);
229
 
230
static void SendHandler(XIic *InstancePtr);
231
 
232
static void ReceiveHandler(XIic *InstancePtr);
233
 
234
static void StatusHandler(XIic *InstancePtr, int Event);
235
 
236
#ifdef IIC_MUX_ENABLE
237
static int MuxInit(void);
238
#endif
239
/************************** Variable Definitions *****************************/
240
 
241
XIic IicInstance;       /* The instance of the IIC device. */
242
INTC Intc;      /* The instance of the Interrupt Controller Driver */
243
 
244
/*
245
 * Write buffer for writing a page.
246
 */
247
u8 WriteBuffer[sizeof(AddressType) + PAGE_SIZE];
248
 
249
u8 ReadBuffer[PAGE_SIZE];       /* Read buffer for reading a page. */
250
 
251
volatile u8 TransmitComplete;   /* Flag to check completion of Transmission */
252
volatile u8 ReceiveComplete;    /* Flag to check completion of Reception */
253
 
254
u8 EepromIicAddr;               /* Variable for storing Eeprom IIC address */
255
 
256
/************************** Function Definitions *****************************/
257
 
258
/*****************************************************************************/
259
/**
260
* Main function to call the High level EEPROM example.
261
*
262
* @param        None.
263
*
264
* @return       XST_SUCCESS if successful else XST_FAILURE.
265
*
266
* @note         None.
267
*
268
******************************************************************************/
269
int main(void)
270
{
271
        int Status;
272
 
273
        /*
274
         * Run the EEPROM example.
275
         */
276
        Status = IicEepromExample();
277
        if (Status != XST_SUCCESS) {
278
                return XST_FAILURE;
279
        }
280
        return XST_SUCCESS;
281
}
282
 
283
/*****************************************************************************/
284
/**
285
* This function writes, reads, and verifies the data to the IIC EEPROM. It
286
* does the write as a single page write, performs a buffered read.
287
*
288
* @param        None.
289
*
290
* @return       XST_SUCCESS if successful else XST_FAILURE.
291
*
292
* @note         None.
293
*
294
******************************************************************************/
295
int IicEepromExample()
296
{
297
        u32 Index;
298
        int Status;
299
        XIic_Config *ConfigPtr; /* Pointer to configuration data */
300
        AddressType Address = EEPROM_TEST_START_ADDRESS;
301
        EepromIicAddr = EEPROM_ADDRESS;
302
 
303
        /*
304
         * Initialize the IIC driver so that it is ready to use.
305
         */
306
        ConfigPtr = XIic_LookupConfig(IIC_DEVICE_ID);
307
        if (ConfigPtr == NULL) {
308
                return XST_FAILURE;
309
        }
310
 
311
        Status = XIic_CfgInitialize(&IicInstance, ConfigPtr,
312
                        ConfigPtr->BaseAddress);
313
        if (Status != XST_SUCCESS) {
314
                return XST_FAILURE;
315
        }
316
 
317
        /*
318
         * Setup the Interrupt System.
319
         */
320
        Status = SetupInterruptSystem(&IicInstance);
321
        if (Status != XST_SUCCESS) {
322
                return XST_FAILURE;
323
        }
324
 
325
        /*
326
         * Set the Handlers for transmit and reception.
327
         */
328
        XIic_SetSendHandler(&IicInstance, &IicInstance,
329
                                (XIic_Handler) SendHandler);
330
        XIic_SetRecvHandler(&IicInstance, &IicInstance,
331
                                (XIic_Handler) ReceiveHandler);
332
        XIic_SetStatusHandler(&IicInstance, &IicInstance,
333
                                  (XIic_StatusHandler) StatusHandler);
334
 
335
 
336
#ifdef IIC_MUX_ENABLE
337
        /*
338
         * Initialize the IIC MUX on the boards on which the EEPROM
339
         * are connected through the MUX.
340
         */
341
        Status =  MuxInit();
342
        if (Status != XST_SUCCESS) {
343
                return XST_FAILURE;
344
        }
345
 
346
#endif
347
 
348
        /*
349
         * Initialize the data to write and the read buffer.
350
         */
351
        if (sizeof(Address) == 1) {
352
                WriteBuffer[0] = (u8) (EEPROM_TEST_START_ADDRESS);
353
                EepromIicAddr |= (EEPROM_TEST_START_ADDRESS >> 8) & 0x7;
354
        } else {
355
                WriteBuffer[0] = (u8) (EEPROM_TEST_START_ADDRESS >> 8);
356
                WriteBuffer[1] = (u8) (EEPROM_TEST_START_ADDRESS);
357
                ReadBuffer[Index] = 0;
358
        }
359
 
360
        for (Index = 0; Index < PAGE_SIZE; Index++) {
361
                WriteBuffer[sizeof(Address) + Index] = 0xFF;
362
                ReadBuffer[Index] = 0;
363
        }
364
 
365
        /*
366
         * Set the Slave address.
367
         */
368
        Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE,
369
                                 EepromIicAddr);
370
        if (Status != XST_SUCCESS) {
371
                return XST_FAILURE;
372
        }
373
 
374
 
375
        /*
376
         * Write to the EEPROM.
377
         */
378
        Status = EepromWriteData(sizeof(Address) + PAGE_SIZE);
379
        if (Status != XST_SUCCESS) {
380
                return XST_FAILURE;
381
        }
382
 
383
        /*
384
         * Read from the EEPROM.
385
         */
386
        Status = EepromReadData(ReadBuffer, PAGE_SIZE);
387
        if (Status != XST_SUCCESS) {
388
                return XST_FAILURE;
389
        }
390
 
391
        /*
392
         * Verify the data read against the data written.
393
         */
394
        for (Index = 0; Index < PAGE_SIZE; Index++) {
395
                if (ReadBuffer[Index] != WriteBuffer[Index + sizeof(Address)]) {
396
                        return XST_FAILURE;
397
                }
398
 
399
                ReadBuffer[Index] = 0;
400
        }
401
 
402
        /*
403
         * Initialize the data to write and the read buffer.
404
         */
405
        if (sizeof(Address) == 1) {
406
                WriteBuffer[0] = (u8) (EEPROM_TEST_START_ADDRESS);
407
        } else {
408
                WriteBuffer[0] = (u8) (EEPROM_TEST_START_ADDRESS >> 8);
409
                WriteBuffer[1] = (u8) (EEPROM_TEST_START_ADDRESS);
410
                ReadBuffer[Index] = 0;
411
        }
412
 
413
        for (Index = 0; Index < PAGE_SIZE; Index++) {
414
                WriteBuffer[sizeof(Address) + Index] = Index;
415
                ReadBuffer[Index] = 0;
416
        }
417
 
418
        /*
419
         * Write to the EEPROM.
420
         */
421
        Status = EepromWriteData(sizeof(Address) + PAGE_SIZE);
422
        if (Status != XST_SUCCESS) {
423
                return XST_FAILURE;
424
        }
425
 
426
        /*
427
         * Read from the EEPROM.
428
         */
429
        Status = EepromReadData(ReadBuffer, PAGE_SIZE);
430
        if (Status != XST_SUCCESS) {
431
                return XST_FAILURE;
432
        }
433
 
434
        /*
435
         * Verify the data read against the data written.
436
         */
437
        for (Index = 0; Index < PAGE_SIZE; Index++) {
438
                if (ReadBuffer[Index] != WriteBuffer[Index + sizeof(Address)]) {
439
                        return XST_FAILURE;
440
                }
441
 
442
                ReadBuffer[Index] = 0;
443
        }
444
 
445
        return XST_SUCCESS;
446
}
447
 
448
/*****************************************************************************/
449
/**
450
* This function writes a buffer of data to the IIC serial EEPROM.
451
*
452
* @param        ByteCount contains the number of bytes in the buffer to be
453
*               written.
454
*
455
* @return       XST_SUCCESS if successful else XST_FAILURE.
456
*
457
* @note         The Byte count should not exceed the page size of the EEPROM as
458
*               noted by the constant PAGE_SIZE.
459
*
460
******************************************************************************/
461
int EepromWriteData(u16 ByteCount)
462
{
463
        int Status;
464
 
465
        /*
466
         * Set the defaults.
467
         */
468
        TransmitComplete = 1;
469
        IicInstance.Stats.TxErrors = 0;
470
 
471
        /*
472
         * Start the IIC device.
473
         */
474
        Status = XIic_Start(&IicInstance);
475
        if (Status != XST_SUCCESS) {
476
                return XST_FAILURE;
477
        }
478
 
479
        /*
480
         * Send the Data.
481
         */
482
        Status = XIic_MasterSend(&IicInstance, WriteBuffer, ByteCount);
483
        if (Status != XST_SUCCESS) {
484
                return XST_FAILURE;
485
        }
486
 
487
        /*
488
         * Wait till the transmission is completed.
489
         */
490
        while ((TransmitComplete) || (XIic_IsIicBusy(&IicInstance) == TRUE)) {
491
                /*
492
                 * This condition is required to be checked in the case where we
493
                 * are writing two consecutive buffers of data to the EEPROM.
494
                 * The EEPROM takes about 2 milliseconds time to update the data
495
                 * internally after a STOP has been sent on the bus.
496
                 * A NACK will be generated in the case of a second write before
497
                 * the EEPROM updates the data internally resulting in a
498
                 * Transmission Error.
499
                 */
500
                if (IicInstance.Stats.TxErrors != 0) {
501
 
502
 
503
                        /*
504
                         * Enable the IIC device.
505
                         */
506
                        Status = XIic_Start(&IicInstance);
507
                        if (Status != XST_SUCCESS) {
508
                                return XST_FAILURE;
509
                        }
510
 
511
 
512
                        if (!XIic_IsIicBusy(&IicInstance)) {
513
                                /*
514
                                 * Send the Data.
515
                                 */
516
                                Status = XIic_MasterSend(&IicInstance,
517
                                                         WriteBuffer,
518
                                                         ByteCount);
519
                                if (Status == XST_SUCCESS) {
520
                                        IicInstance.Stats.TxErrors = 0;
521
                                }
522
                                else {
523
                                }
524
                        }
525
                }
526
        }
527
 
528
        /*
529
         * Stop the IIC device.
530
         */
531
        Status = XIic_Stop(&IicInstance);
532
        if (Status != XST_SUCCESS) {
533
                return XST_FAILURE;
534
        }
535
 
536
        return XST_SUCCESS;
537
}
538
 
539
/*****************************************************************************/
540
/**
541
* This function reads data from the IIC serial EEPROM into a specified buffer.
542
*
543
* @param        BufferPtr contains the address of the data buffer to be filled.
544
* @param        ByteCount contains the number of bytes in the buffer to be read.
545
*
546
* @return       XST_SUCCESS if successful else XST_FAILURE.
547
*
548
* @note         None.
549
*
550
******************************************************************************/
551
int EepromReadData(u8 *BufferPtr, u16 ByteCount)
552
{
553
        int Status;
554
        AddressType Address = EEPROM_TEST_START_ADDRESS;
555
 
556
        /*
557
         * Set the Defaults.
558
         */
559
        ReceiveComplete = 1;
560
 
561
        /*
562
         * Position the Pointer in EEPROM.
563
         */
564
        if (sizeof(Address) == 1) {
565
                WriteBuffer[0] = (u8) (EEPROM_TEST_START_ADDRESS);
566
        }
567
        else {
568
                WriteBuffer[0] = (u8) (EEPROM_TEST_START_ADDRESS >> 8);
569
                WriteBuffer[1] = (u8) (EEPROM_TEST_START_ADDRESS);
570
        }
571
 
572
        Status = EepromWriteData(sizeof(Address));
573
        if (Status != XST_SUCCESS) {
574
                return XST_FAILURE;
575
        }
576
 
577
        /*
578
         * Start the IIC device.
579
         */
580
        Status = XIic_Start(&IicInstance);
581
        if (Status != XST_SUCCESS) {
582
                return XST_FAILURE;
583
        }
584
 
585
        /*
586
         * Receive the Data.
587
         */
588
        Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
589
        if (Status != XST_SUCCESS) {
590
                return XST_FAILURE;
591
        }
592
 
593
        /*
594
         * Wait till all the data is received.
595
         */
596
        while ((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance) == TRUE)) {
597
 
598
        }
599
 
600
        /*
601
         * Stop the IIC device.
602
         */
603
        Status = XIic_Stop(&IicInstance);
604
        if (Status != XST_SUCCESS) {
605
                return XST_FAILURE;
606
        }
607
 
608
        return XST_SUCCESS;
609
}
610
 
611
/*****************************************************************************/
612
/**
613
* This function setups the interrupt system so interrupts can occur for the
614
* IIC device. The function is application-specific since the actual system may
615
* or may not have an interrupt controller. The IIC device could be directly
616
* connected to a processor without an interrupt controller. The user should
617
* modify this function to fit the application.
618
*
619
* @param        IicInstPtr contains a pointer to the instance of the IIC device
620
*               which is going to be connected to the interrupt controller.
621
*
622
* @return       XST_SUCCESS if successful else XST_FAILURE.
623
*
624
* @note         None.
625
*
626
******************************************************************************/
627
static int SetupInterruptSystem(XIic *IicInstPtr)
628
{
629
        int Status;
630
 
631
#ifdef XPAR_INTC_0_DEVICE_ID
632
 
633
        /*
634
         * Initialize the interrupt controller driver so that it's ready to use.
635
         */
636
        Status = XIntc_Initialize(&Intc, INTC_DEVICE_ID);
637
 
638
        if (Status != XST_SUCCESS) {
639
                return XST_FAILURE;
640
        }
641
 
642
        /*
643
         * Connect the device driver handler that will be called when an
644
         * interrupt for the device occurs, the handler defined above performs
645
         * the specific interrupt processing for the device.
646
         */
647
        Status = XIntc_Connect(&Intc, IIC_INTR_ID,
648
                                   (XInterruptHandler) XIic_InterruptHandler,
649
                                   IicInstPtr);
650
        if (Status != XST_SUCCESS) {
651
                return XST_FAILURE;
652
        }
653
 
654
        /*
655
         * Start the interrupt controller so interrupts are enabled for all
656
         * devices that cause interrupts.
657
         */
658
        Status = XIntc_Start(&Intc, XIN_REAL_MODE);
659
        if (Status != XST_SUCCESS) {
660
                return XST_FAILURE;
661
        }
662
 
663
        /*
664
         * Enable the interrupts for the IIC device.
665
         */
666
        XIntc_Enable(&Intc, IIC_INTR_ID);
667
 
668
#else
669
 
670
        XScuGic_Config *IntcConfig;
671
 
672
        /*
673
         * Initialize the interrupt controller driver so that it is ready to
674
         * use.
675
         */
676
        IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
677
        if (NULL == IntcConfig) {
678
                return XST_FAILURE;
679
        }
680
 
681
        Status = XScuGic_CfgInitialize(&Intc, IntcConfig,
682
                                        IntcConfig->CpuBaseAddress);
683
        if (Status != XST_SUCCESS) {
684
                return XST_FAILURE;
685
        }
686
 
687
        XScuGic_SetPriorityTriggerType(&Intc, IIC_INTR_ID,
688
                                        0xA0, 0x3);
689
 
690
        /*
691
         * Connect the interrupt handler that will be called when an
692
         * interrupt occurs for the device.
693
         */
694
        Status = XScuGic_Connect(&Intc, IIC_INTR_ID,
695
                                 (Xil_InterruptHandler)XIic_InterruptHandler,
696
                                 IicInstPtr);
697
        if (Status != XST_SUCCESS) {
698
                return Status;
699
        }
700
 
701
        /*
702
         * Enable the interrupt for the IIC device.
703
         */
704
        XScuGic_Enable(&Intc, IIC_INTR_ID);
705
 
706
#endif
707
 
708
        /*
709
         * Initialize the exception table and register the interrupt
710
         * controller handler with the exception table
711
         */
712
        Xil_ExceptionInit();
713
 
714
        Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
715
                         (Xil_ExceptionHandler)INTC_HANDLER, &Intc);
716
 
717
        /* Enable non-critical exceptions */
718
        Xil_ExceptionEnable();
719
 
720
 
721
 
722
        return XST_SUCCESS;
723
}
724
 
725
/*****************************************************************************/
726
/**
727
* This Send handler is called asynchronously from an interrupt
728
* context and indicates that data in the specified buffer has been sent.
729
*
730
* @param        InstancePtr is not used, but contains a pointer to the IIC
731
*               device driver instance which the handler is being called for.
732
*
733
* @return       None.
734
*
735
* @note         None.
736
*
737
******************************************************************************/
738
static void SendHandler(XIic *InstancePtr)
739
{
740
        TransmitComplete = 0;
741
}
742
 
743
/*****************************************************************************/
744
/**
745
* This Receive handler is called asynchronously from an interrupt
746
* context and indicates that data in the specified buffer has been Received.
747
*
748
* @param        InstancePtr is not used, but contains a pointer to the IIC
749
*               device driver instance which the handler is being called for.
750
*
751
* @return       None.
752
*
753
* @note         None.
754
*
755
******************************************************************************/
756
static void ReceiveHandler(XIic *InstancePtr)
757
{
758
        ReceiveComplete = 0;
759
}
760
 
761
/*****************************************************************************/
762
/**
763
* This Status handler is called asynchronously from an interrupt
764
* context and indicates the events that have occurred.
765
*
766
* @param        InstancePtr is a pointer to the IIC driver instance for which
767
*               the handler is being called for.
768
* @param        Event indicates the condition that has occurred.
769
*
770
* @return       None.
771
*
772
* @note         None.
773
*
774
******************************************************************************/
775
static void StatusHandler(XIic *InstancePtr, int Event)
776
{
777
 
778
}
779
 
780
#ifdef IIC_MUX_ENABLE
781
/*****************************************************************************/
782
/**
783
* This function initializes the IIC MUX to select EEPROM.
784
*
785
* @param        None.
786
*
787
* @return       XST_SUCCESS if pass, otherwise XST_FAILURE.
788
*
789
* @note         None.
790
*
791
****************************************************************************/
792
int MuxInit(void)
793
{
794
 
795
        int Status;
796
        /*
797
         * Set the Slave address to the IIC MUC - PCA9543A.
798
         */
799
        Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE,
800
                                 IIC_MUX_ADDRESS);
801
        if (Status != XST_SUCCESS) {
802
                return XST_FAILURE;
803
        }
804
 
805
 
806
        /*
807
         * Enabling all the channels
808
         */
809
        WriteBuffer[0] = IIC_EEPROM_CHANNEL;
810
 
811
        Status = EepromWriteData(1);
812
        if (Status != XST_SUCCESS) {
813
                return XST_FAILURE;
814
        }
815
 
816
        return XST_SUCCESS;
817
}
818
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.