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/******************************************************************************
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*
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* Copyright (C) 2006 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiic_dyn_master.c
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* @addtogroup iic_v3_1
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* @{
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*
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* Contains master functions for the XIic component in Dynamic controller mode.
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* This file is necessary to send or receive as a master on the IIC bus.
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*
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*
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- ------- -----------------------------------------------------------
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* 1.03a mta 04/10/06 Created.
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* 1.13a wgr 03/22/07 Converted to new coding style.
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* 2.00a ktn 10/22/09 Converted all register accesses to 32 bit access.
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* Updated to use the HAL APIs/macros. The macros
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* XIic_mDynSend7BitAddress and XIic_mDynSendStop have
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* been removed from this file as they were already
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* defined in a header file.
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* Some of the macros have been renamed to remove _m from
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* the name and Some of the macros have been renamed to be
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* consistent, see the xiic_l.h file for further information.
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*
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xiic.h"
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#include "xiic_i.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/******************************************************************************
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*
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* This macro includes dynamic master code such that dynamic master operations,
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* sending and receiving data, may be used. This function hooks the dynamic
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* master processing to the driver such that events are handled properly and
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* allows dynamic master processing to be optional. It must be called before any
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* functions which are contained in this file are called, such as after the
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* driver is initialized.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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#define XIIC_DYN_MASTER_INCLUDE \
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{ \
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XIic_RecvMasterFuncPtr = DynRecvMasterData; \
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XIic_SendMasterFuncPtr = DynSendMasterData; \
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}
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/************************** Function Prototypes ******************************/
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static void DynRecvMasterData(XIic *InstancePtr);
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static void DynSendMasterData(XIic *InstancePtr);
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static int IsBusBusy(XIic *InstancePtr);
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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* This function sends data as a Dynamic master on the IIC bus. If the bus is
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* busy, it will indicate so and then enable an interrupt such that the status
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* handler will be called when the bus is no longer busy. The slave address is
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* sent by using XIic_DynSend7BitAddress().
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*
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* @param InstancePtr points to the Iic instance to be worked on.
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* @param TxMsgPtr points to the data to be transmitted.
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* @param ByteCount is the number of message bytes to be sent.
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*
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* @return XST_SUCCESS if successful else XST_FAILURE.
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*
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* @note None.
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*
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******************************************************************************/
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int XIic_DynMasterSend(XIic *InstancePtr, u8 *TxMsgPtr, u8 ByteCount)
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{
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u32 CntlReg;
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XIic_IntrGlobalDisable(InstancePtr->BaseAddress);
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/*
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* Ensure that the Dynamic master processing has been included such that
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* events will be properly handled.
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*/
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XIIC_DYN_MASTER_INCLUDE;
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InstancePtr->IsDynamic = TRUE;
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/*
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* If the busy is busy, then exit the critical region and wait for the
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* bus not to be busy. The function enables the BusNotBusy interrupt.
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*/
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if (IsBusBusy(InstancePtr)) {
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XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
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return XST_FAILURE;
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}
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/*
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* If it is already a master on the bus (repeated start), the direction
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* was set to Tx which is throttling bus. The control register needs to
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* be set before putting data into the FIFO.
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*/
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CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
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if (CntlReg & XIIC_CR_MSMS_MASK) {
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CntlReg &= ~XIIC_CR_NO_ACK_MASK;
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CntlReg |= XIIC_CR_DIR_IS_TX_MASK;
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
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CntlReg);
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InstancePtr->Stats.RepeatedStarts++;
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}
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/*
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* Save message state.
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*/
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InstancePtr->SendByteCount = ByteCount;
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InstancePtr->SendBufferPtr = TxMsgPtr;
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/*
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* Send the Seven Bit address. Only 7 bit addressing is supported in
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* Dynamic mode.
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*/
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XIic_DynSend7BitAddress(InstancePtr->BaseAddress,
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InstancePtr->AddrOfSlave,
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XIIC_WRITE_OPERATION);
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/*
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* Set the transmit address state to indicate the address has been sent
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* for communication with event driven processing.
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*/
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InstancePtr->TxAddrMode = XIIC_TX_ADDR_SENT;
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/*
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* Fill the Tx FIFO.
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*/
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if (InstancePtr->SendByteCount > 1) {
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XIic_TransmitFifoFill(InstancePtr, XIIC_MASTER_ROLE);
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}
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/*
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* After filling fifo, if data yet to send > 1, enable Tx � empty
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* interrupt.
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*/
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if (InstancePtr->SendByteCount > 1) {
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XIic_ClearEnableIntr(InstancePtr->BaseAddress,
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XIIC_INTR_TX_HALF_MASK);
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}
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/*
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* Clear any pending Tx empty, Tx Error and then enable them.
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*/
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XIic_ClearEnableIntr(InstancePtr->BaseAddress,
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XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_TX_EMPTY_MASK);
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/*
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* Enable the Interrupts.
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*/
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XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
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return XST_SUCCESS;
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}
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/******************************************************************************
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*
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* When the IIC Tx FIFO/register goes empty, this routine is called by the
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* interrupt service routine to fill the transmit FIFO with data to be sent.
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*
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* This function also is called by the Tx � empty interrupt as the data handling
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* is identical when you don't assume the FIFO is empty but use the Tx_FIFO_OCY
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* register to indicate the available free FIFO bytes.
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*
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* @param InstancePtr is a pointer to the XIic instance to be worked on.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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static void DynSendMasterData(XIic *InstancePtr)
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{
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u32 CntlReg;
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/*
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* In between 1st and last byte of message, fill the FIFO with more data
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* to send, disable the 1/2 empty interrupt based upon data left to
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* send.
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*/
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if (InstancePtr->SendByteCount > 1) {
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XIic_TransmitFifoFill(InstancePtr, XIIC_MASTER_ROLE);
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if (InstancePtr->SendByteCount < 2) {
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XIic_DisableIntr(InstancePtr->BaseAddress,
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XIIC_INTR_TX_HALF_MASK);
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}
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}
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/*
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* If there is only one byte left to send, processing differs between
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* repeated start and normal messages.
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*/
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else if (InstancePtr->SendByteCount == 1) {
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/*
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* When using repeated start, another interrupt is expected
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* after the last byte has been sent, so the message is not
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* done yet.
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*/
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if (InstancePtr->Options & XII_REPEATED_START_OPTION) {
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XIic_WriteSendByte(InstancePtr);
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} else {
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XIic_DynSendStop(InstancePtr->BaseAddress,
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*InstancePtr->SendBufferPtr);
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/*
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* Wait for bus to not be busy before declaring message
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* has been sent for the no repeated start operation.
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* The callback will be called from the BusNotBusy part
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* of the Interrupt handler to ensure that the message
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* is completely sent. Disable the Tx interrupts and
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* enable the BNB interrupt.
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*/
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InstancePtr->BNBOnly = FALSE;
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XIic_DisableIntr(InstancePtr->BaseAddress,
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XIIC_TX_INTERRUPTS);
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XIic_EnableIntr(InstancePtr->BaseAddress,
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XIIC_INTR_BNB_MASK);
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}
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} else {
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if (InstancePtr->Options & XII_REPEATED_START_OPTION) {
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/*
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* The message being sent has completed. When using
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* repeated start with no more bytes to send repeated
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* start needs to be set in the control register so
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* that the bus will still be held by this master.
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*/
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CntlReg = XIic_ReadReg(InstancePtr->BaseAddress,
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XIIC_CR_REG_OFFSET);
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CntlReg |= XIIC_CR_REPEATED_START_MASK;
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XIic_WriteReg(InstancePtr->BaseAddress,
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XIIC_CR_REG_OFFSET, CntlReg);
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/*
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* If the message that was being sent has finished,
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* disable all transmit interrupts and call the callback
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* that was setup to indicate the message was sent,
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* with 0 bytes remaining.
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*/
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XIic_DisableIntr(InstancePtr->BaseAddress,
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XIIC_TX_INTERRUPTS);
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InstancePtr->SendHandler(InstancePtr->SendCallBackRef,
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0);
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}
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}
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return;
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}
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/*****************************************************************************/
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/**
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* This function receives data as a master from a slave device on the IIC bus.
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* If the bus is busy, it will indicate so and then enable an interrupt such
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* that the status handler will be called when the bus is no longer busy. The
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* slave address which has been set with the XIic_SetAddress() function is the
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* address from which data is received. Receiving data on the bus performs a
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* read operation.
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*
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* @param InstancePtr is a pointer to the Iic instance to be worked on.
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* @param RxMsgPtr is a pointer to the data to be transmitted.
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* @param ByteCount is the number of message bytes to be sent.
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*
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* @return - XST_SUCCESS indicates the message reception processes has been
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* initiated.
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* - XST_IIC_BUS_BUSY indicates the bus was in use and that the
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* BusNotBusy interrupt is enabled which will update the
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* EventStatus when the bus is no longer busy.
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* - XST_IIC_GENERAL_CALL_ADDRESS indicates the slave address is
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* set to the general call address. This is not allowed for Master
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* receive mode.
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*
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* @note The receive FIFO threshold is a zero based count such that 1
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* must be subtracted from the desired count to get the correct
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* value. When receiving data it is also necessary to not receive
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* the last byte with the prior bytes because the acknowledge must
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* be setup before the last byte is received.
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*
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******************************************************************************/
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| 329 |
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int XIic_DynMasterRecv(XIic *InstancePtr, u8 *RxMsgPtr, u8 ByteCount)
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| 330 |
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{
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| 331 |
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u32 CntlReg;
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| 332 |
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u32 RxFifoOccy;
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| 333 |
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|
| 334 |
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/*
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| 335 |
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* If the slave address is zero (general call) the master can't perform
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| 336 |
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* receive operations, indicate an error.
|
| 337 |
|
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*/
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| 338 |
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if (InstancePtr->AddrOfSlave == 0) {
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| 339 |
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return XST_IIC_GENERAL_CALL_ADDRESS;
|
| 340 |
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}
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| 341 |
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| 342 |
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/*
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| 343 |
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* Disable the Interrupts.
|
| 344 |
|
|
*/
|
| 345 |
|
|
XIic_IntrGlobalDisable(InstancePtr->BaseAddress);
|
| 346 |
|
|
|
| 347 |
|
|
/*
|
| 348 |
|
|
* Ensure that the master processing has been included such that events
|
| 349 |
|
|
* will be properly handled.
|
| 350 |
|
|
*/
|
| 351 |
|
|
XIIC_DYN_MASTER_INCLUDE;
|
| 352 |
|
|
InstancePtr->IsDynamic = TRUE;
|
| 353 |
|
|
|
| 354 |
|
|
/*
|
| 355 |
|
|
* If the busy is busy, then exit the critical region and wait for the
|
| 356 |
|
|
* bus to not be busy, the function enables the bus not busy interrupt.
|
| 357 |
|
|
*/
|
| 358 |
|
|
if (IsBusBusy(InstancePtr)) {
|
| 359 |
|
|
XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
|
| 360 |
|
|
|
| 361 |
|
|
return XST_IIC_BUS_BUSY;
|
| 362 |
|
|
}
|
| 363 |
|
|
|
| 364 |
|
|
/*
|
| 365 |
|
|
* Save message state for event driven processing.
|
| 366 |
|
|
*/
|
| 367 |
|
|
InstancePtr->RecvByteCount = ByteCount;
|
| 368 |
|
|
InstancePtr->RecvBufferPtr = RxMsgPtr;
|
| 369 |
|
|
|
| 370 |
|
|
/*
|
| 371 |
|
|
* Clear and enable Rx full interrupt.
|
| 372 |
|
|
*/
|
| 373 |
|
|
XIic_ClearEnableIntr(InstancePtr->BaseAddress, XIIC_INTR_RX_FULL_MASK);
|
| 374 |
|
|
|
| 375 |
|
|
/*
|
| 376 |
|
|
* If already a master on the bus, the direction was set by Rx Interrupt
|
| 377 |
|
|
* routine to Tx which is throttling bus because during Rxing, Tx reg is
|
| 378 |
|
|
* empty = throttle. CR needs setting before putting data or the address
|
| 379 |
|
|
* written will go out as Tx instead of receive. Start Master Rx by
|
| 380 |
|
|
* setting CR Bits MSMS to Master and msg direction.
|
| 381 |
|
|
*/
|
| 382 |
|
|
CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
|
| 383 |
|
|
if (CntlReg & XIIC_CR_MSMS_MASK) {
|
| 384 |
|
|
/*
|
| 385 |
|
|
* Set the Repeated Start bit in CR.
|
| 386 |
|
|
*/
|
| 387 |
|
|
CntlReg |= XIIC_CR_REPEATED_START_MASK;
|
| 388 |
|
|
XIic_SetControlRegister(InstancePtr, CntlReg, ByteCount);
|
| 389 |
|
|
|
| 390 |
|
|
/*
|
| 391 |
|
|
* Increment stats counts.
|
| 392 |
|
|
*/
|
| 393 |
|
|
InstancePtr->Stats.RepeatedStarts++;
|
| 394 |
|
|
XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
|
| 395 |
|
|
CntlReg);
|
| 396 |
|
|
}
|
| 397 |
|
|
|
| 398 |
|
|
/*
|
| 399 |
|
|
* Set receive FIFO occupancy depth which must be done prior to writing
|
| 400 |
|
|
* the address in the FIFO because the transmitter will immediately
|
| 401 |
|
|
* start when in repeated start mode followed by the receiver such
|
| 402 |
|
|
* that the number of bytes to receive should be set 1st.
|
| 403 |
|
|
*/
|
| 404 |
|
|
if (ByteCount == 1) {
|
| 405 |
|
|
RxFifoOccy = 0;
|
| 406 |
|
|
}
|
| 407 |
|
|
else {
|
| 408 |
|
|
if (ByteCount <= IIC_RX_FIFO_DEPTH) {
|
| 409 |
|
|
RxFifoOccy = ByteCount - 2;
|
| 410 |
|
|
} else {
|
| 411 |
|
|
RxFifoOccy = IIC_RX_FIFO_DEPTH - 1;
|
| 412 |
|
|
}
|
| 413 |
|
|
}
|
| 414 |
|
|
|
| 415 |
|
|
XIic_WriteReg(InstancePtr->BaseAddress, XIIC_RFD_REG_OFFSET,
|
| 416 |
|
|
RxFifoOccy);
|
| 417 |
|
|
|
| 418 |
|
|
/*
|
| 419 |
|
|
* Send the Seven Bit address. Only 7 bit addressing is supported in
|
| 420 |
|
|
* Dynamic mode and mark that the address has been sent.
|
| 421 |
|
|
*/
|
| 422 |
|
|
XIic_DynSend7BitAddress(InstancePtr->BaseAddress,
|
| 423 |
|
|
InstancePtr->AddrOfSlave, XIIC_READ_OPERATION);
|
| 424 |
|
|
InstancePtr->TxAddrMode = XIIC_TX_ADDR_SENT;
|
| 425 |
|
|
|
| 426 |
|
|
/*
|
| 427 |
|
|
* Send the bytecount to be received and set the stop bit.
|
| 428 |
|
|
*/
|
| 429 |
|
|
XIic_DynSendStop(InstancePtr->BaseAddress, ByteCount);
|
| 430 |
|
|
|
| 431 |
|
|
/*
|
| 432 |
|
|
* Tx error is enabled incase the address has no device to answer
|
| 433 |
|
|
* with Ack. When only one byte of data, must set NO ACK before address
|
| 434 |
|
|
* goes out therefore Tx error must not be enabled as it will go off
|
| 435 |
|
|
* immediately and the Rx full interrupt will be checked. If full, then
|
| 436 |
|
|
* the one byte was received and the Tx error will be disabled without
|
| 437 |
|
|
* sending an error callback msg.
|
| 438 |
|
|
*/
|
| 439 |
|
|
XIic_ClearEnableIntr(InstancePtr->BaseAddress,
|
| 440 |
|
|
XIIC_INTR_TX_ERROR_MASK);
|
| 441 |
|
|
|
| 442 |
|
|
/*
|
| 443 |
|
|
* Enable the Interrupts.
|
| 444 |
|
|
*/
|
| 445 |
|
|
XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
|
| 446 |
|
|
|
| 447 |
|
|
return XST_SUCCESS;
|
| 448 |
|
|
}
|
| 449 |
|
|
|
| 450 |
|
|
/*****************************************************************************/
|
| 451 |
|
|
/**
|
| 452 |
|
|
*
|
| 453 |
|
|
* This function is called when the receive register is full. The number
|
| 454 |
|
|
* of bytes received to cause the interrupt is adjustable using the Receive FIFO
|
| 455 |
|
|
* Depth register. The number of bytes in the register is read in the Receive
|
| 456 |
|
|
* FIFO occupancy register. Both these registers are zero based values (0-15)
|
| 457 |
|
|
* such that a value of zero indicates 1 byte.
|
| 458 |
|
|
*
|
| 459 |
|
|
* For a Master Receiver to properly signal the end of a message, the data must
|
| 460 |
|
|
* be read in up to the message length - 1, where control register bits will be
|
| 461 |
|
|
* set for bus controls to occur on reading of the last byte.
|
| 462 |
|
|
*
|
| 463 |
|
|
* @param InstancePtr is a pointer to the XIic instance to be worked on.
|
| 464 |
|
|
*
|
| 465 |
|
|
* @return None.
|
| 466 |
|
|
*
|
| 467 |
|
|
* @note None.
|
| 468 |
|
|
*
|
| 469 |
|
|
******************************************************************************/
|
| 470 |
|
|
static void DynRecvMasterData(XIic *InstancePtr)
|
| 471 |
|
|
{
|
| 472 |
|
|
u8 LoopCnt;
|
| 473 |
|
|
u8 BytesInFifo;
|
| 474 |
|
|
u8 BytesToRead;
|
| 475 |
|
|
u32 CntlReg;
|
| 476 |
|
|
|
| 477 |
|
|
/*
|
| 478 |
|
|
* Device is a master receiving, get the contents of the control
|
| 479 |
|
|
* register and determine the number of bytes in fifo to be read out.
|
| 480 |
|
|
*/
|
| 481 |
|
|
CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
|
| 482 |
|
|
BytesInFifo = (u8) XIic_ReadReg(InstancePtr->BaseAddress,
|
| 483 |
|
|
XIIC_RFO_REG_OFFSET) + 1;
|
| 484 |
|
|
|
| 485 |
|
|
/*
|
| 486 |
|
|
* If data in FIFO holds all data to be retrieved - 1, set NOACK and
|
| 487 |
|
|
* disable the Tx error.
|
| 488 |
|
|
*/
|
| 489 |
|
|
if ((InstancePtr->RecvByteCount - BytesInFifo) == 1) {
|
| 490 |
|
|
/*
|
| 491 |
|
|
* Disable Tx error interrupt to prevent interrupt as this
|
| 492 |
|
|
* device will cause it when it set NO ACK next.
|
| 493 |
|
|
*/
|
| 494 |
|
|
XIic_DisableIntr(InstancePtr->BaseAddress,
|
| 495 |
|
|
XIIC_INTR_TX_ERROR_MASK);
|
| 496 |
|
|
XIic_ClearIntr(InstancePtr->BaseAddress,
|
| 497 |
|
|
XIIC_INTR_TX_ERROR_MASK);
|
| 498 |
|
|
|
| 499 |
|
|
/*
|
| 500 |
|
|
* Read one byte to clear a place for the last byte to be read
|
| 501 |
|
|
* which will set the NO ACK.
|
| 502 |
|
|
*/
|
| 503 |
|
|
XIic_ReadRecvByte(InstancePtr);
|
| 504 |
|
|
}
|
| 505 |
|
|
|
| 506 |
|
|
/*
|
| 507 |
|
|
* If data in FIFO is all the data to be received then get the data and
|
| 508 |
|
|
* also leave the device in a good state for the next transaction.
|
| 509 |
|
|
*/
|
| 510 |
|
|
else if ((InstancePtr->RecvByteCount - BytesInFifo) == 0) {
|
| 511 |
|
|
if (InstancePtr->Options & XII_REPEATED_START_OPTION) {
|
| 512 |
|
|
CntlReg |= XIIC_CR_REPEATED_START_MASK;
|
| 513 |
|
|
XIic_WriteReg(InstancePtr->BaseAddress,
|
| 514 |
|
|
XIIC_CR_REG_OFFSET,
|
| 515 |
|
|
CntlReg);
|
| 516 |
|
|
}
|
| 517 |
|
|
|
| 518 |
|
|
/*
|
| 519 |
|
|
* Read data from the FIFO then set zero based FIFO read depth
|
| 520 |
|
|
* for a byte.
|
| 521 |
|
|
*/
|
| 522 |
|
|
for (LoopCnt = 0; LoopCnt < BytesInFifo; LoopCnt++) {
|
| 523 |
|
|
XIic_ReadRecvByte(InstancePtr);
|
| 524 |
|
|
}
|
| 525 |
|
|
|
| 526 |
|
|
XIic_WriteReg(InstancePtr->BaseAddress,
|
| 527 |
|
|
XIIC_RFD_REG_OFFSET, 0);
|
| 528 |
|
|
|
| 529 |
|
|
/*
|
| 530 |
|
|
* Disable Rx full interrupt and write the control reg with ACK
|
| 531 |
|
|
* allowing next byte sent to be acknowledged automatically.
|
| 532 |
|
|
*/
|
| 533 |
|
|
XIic_DisableIntr(InstancePtr->BaseAddress,
|
| 534 |
|
|
XIIC_INTR_RX_FULL_MASK);
|
| 535 |
|
|
|
| 536 |
|
|
/*
|
| 537 |
|
|
* Send notification of msg Rx complete in RecvHandler callback.
|
| 538 |
|
|
*/
|
| 539 |
|
|
InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef, 0);
|
| 540 |
|
|
}
|
| 541 |
|
|
else {
|
| 542 |
|
|
/*
|
| 543 |
|
|
* Fifo data not at n-1, read all but the last byte of data
|
| 544 |
|
|
* from the slave, if more than a FIFO full yet to receive
|
| 545 |
|
|
* read a FIFO full.
|
| 546 |
|
|
*/
|
| 547 |
|
|
BytesToRead = InstancePtr->RecvByteCount - BytesInFifo - 1;
|
| 548 |
|
|
if (BytesToRead > IIC_RX_FIFO_DEPTH) {
|
| 549 |
|
|
BytesToRead = IIC_RX_FIFO_DEPTH;
|
| 550 |
|
|
}
|
| 551 |
|
|
|
| 552 |
|
|
/*
|
| 553 |
|
|
* Read in data from the FIFO.
|
| 554 |
|
|
*/
|
| 555 |
|
|
for (LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) {
|
| 556 |
|
|
XIic_ReadRecvByte(InstancePtr);
|
| 557 |
|
|
}
|
| 558 |
|
|
}
|
| 559 |
|
|
}
|
| 560 |
|
|
|
| 561 |
|
|
/******************************************************************************
|
| 562 |
|
|
*
|
| 563 |
|
|
* This function checks to see if the IIC bus is busy. If so, it will enable
|
| 564 |
|
|
* the bus not busy interrupt such that the driver is notified when the bus
|
| 565 |
|
|
* is no longer busy.
|
| 566 |
|
|
*
|
| 567 |
|
|
* @param InstancePtr points to the Iic instance to be worked on.
|
| 568 |
|
|
*
|
| 569 |
|
|
* @return FALSE if the IIC bus is not busy else TRUE.
|
| 570 |
|
|
*
|
| 571 |
|
|
* @note The BusNotBusy interrupt is enabled which will update the
|
| 572 |
|
|
* EventStatus when the bus is no longer busy.
|
| 573 |
|
|
*
|
| 574 |
|
|
******************************************************************************/
|
| 575 |
|
|
static int IsBusBusy(XIic *InstancePtr)
|
| 576 |
|
|
{
|
| 577 |
|
|
u32 CntlReg;
|
| 578 |
|
|
u32 StatusReg;
|
| 579 |
|
|
|
| 580 |
|
|
CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
|
| 581 |
|
|
StatusReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_SR_REG_OFFSET);
|
| 582 |
|
|
|
| 583 |
|
|
/*
|
| 584 |
|
|
* If this device is already master of the bus as when using the
|
| 585 |
|
|
* repeated start and the bus is busy setup to wait for it to not
|
| 586 |
|
|
* be busy.
|
| 587 |
|
|
*/
|
| 588 |
|
|
if (((CntlReg & XIIC_CR_MSMS_MASK) == 0) && /* Not master */
|
| 589 |
|
|
(StatusReg & XIIC_SR_BUS_BUSY_MASK)) { /* Is busy */
|
| 590 |
|
|
/*
|
| 591 |
|
|
* The bus is busy, clear pending BNB interrupt incase
|
| 592 |
|
|
* previously set and then enable BusNotBusy interrupt.
|
| 593 |
|
|
*/
|
| 594 |
|
|
InstancePtr->BNBOnly = TRUE;
|
| 595 |
|
|
XIic_ClearEnableIntr(InstancePtr->BaseAddress,
|
| 596 |
|
|
XIIC_INTR_BNB_MASK);
|
| 597 |
|
|
InstancePtr->Stats.BusBusy++;
|
| 598 |
|
|
|
| 599 |
|
|
return TRUE;
|
| 600 |
|
|
}
|
| 601 |
|
|
|
| 602 |
|
|
return FALSE;
|
| 603 |
|
|
}
|
| 604 |
|
|
|
| 605 |
|
|
/******************************************************************************
|
| 606 |
|
|
*
|
| 607 |
|
|
* Initialize the IIC core for Dynamic Functionality.
|
| 608 |
|
|
*
|
| 609 |
|
|
* @param InstancePtr points to the Iic instance to be worked on.
|
| 610 |
|
|
*
|
| 611 |
|
|
* @return XST_SUCCESS if Successful else XST_FAILURE.
|
| 612 |
|
|
*
|
| 613 |
|
|
* @note None.
|
| 614 |
|
|
*
|
| 615 |
|
|
******************************************************************************/
|
| 616 |
|
|
int XIic_DynamicInitialize(XIic *InstancePtr)
|
| 617 |
|
|
{
|
| 618 |
|
|
int Status;
|
| 619 |
|
|
|
| 620 |
|
|
Xil_AssertNonvoid(InstancePtr != NULL);
|
| 621 |
|
|
|
| 622 |
|
|
Status = XIic_DynInit(InstancePtr->BaseAddress);
|
| 623 |
|
|
if (Status != XST_SUCCESS) {
|
| 624 |
|
|
return XST_FAILURE;
|
| 625 |
|
|
}
|
| 626 |
|
|
|
| 627 |
|
|
return XST_SUCCESS;
|
| 628 |
|
|
}
|
| 629 |
|
|
/** @} */
|
