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/******************************************************************************
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*
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* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiic_i.h
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* @addtogroup iic_v3_1
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* @{
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*
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* This header file contains internal identifiers, which are those shared
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* between XIic components. The identifiers in this file are not intended for
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* use external to the driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.01a rfp 10/19/01 release
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* 1.01c ecm 12/05/02 new rev
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* 1.13a wgr 03/22/07 Converted to new coding style.
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* 2.00a sdm 10/22/09 Converted all register accesses to 32 bit access.
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* Removed the macro XIIC_CLEAR_STATS, user has to
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* use the the XIic_ClearStats API in its place.
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* Removed the macro XIic_mEnterCriticalRegion,
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* XIic_IntrGlobalDisable should be used in its place.
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* Removed the macro XIic_mExitCriticalRegion,
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* XIic_IntrGlobalEnable should be used in its place.
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* Removed the _m prefix from all the macros
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* XIic_mSend10BitAddrByte1 is now XIic_Send10BitAddrByte1
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* XIic_mSend10BitAddrByte2 is now XIic_Send10BitAddrByte2
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* XIic_mSend7BitAddr is now XIic_Send7BitAddr
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* XIic_mDisableIntr is now XIic_DisableIntr
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* XIic_mEnableIntr is now XIic_EnableIntr
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* XIic_mClearIntr is now XIic_ClearIntr
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* XIic_mClearEnableIntr is now XIic_ClearEnableIntr
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* XIic_mFlushRxFifo is now XIic_FlushRxFifo
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* XIic_mFlushTxFifo is now XIic_FlushTxFifo
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* XIic_mReadRecvByte is now XIic_ReadRecvByte
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* XIic_mWriteSendByte is now XIic_WriteSendByte
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* XIic_mSetControlRegister is now XIic_SetControlRegister
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* 2.07a adk 18/04/13 Updated the code to avoid unused variable warnings when
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* compiling with the -Wextra -Wall flags.
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* Changes done in files xiic.c and xiic_i.h. CR:705001
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XIIC_I_H /* prevent circular inclusions */
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#define XIIC_I_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xstatus.h"
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#include "xiic.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/******************************************************************************
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*
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* This macro sends the first byte of the address for a 10 bit address during
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* both read and write operations. It takes care of the details to format the
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* address correctly.
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*
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* address = 1111_0xxD xx = address MSBits
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* D = Tx direction = 0 = write
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*
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* @param SlaveAddress contains the address of the slave to send to.
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* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_Send10BitAddrByte1(u16 SlaveAddress, u8 Operation);
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*
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******************************************************************************/
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#define XIic_Send10BitAddrByte1(SlaveAddress, Operation) \
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{ \
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u8 LocalAddr = (u8)((SlaveAddress) >> 7); \
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LocalAddr = (LocalAddr & 0xF6) | 0xF0 | (Operation); \
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
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(u32) LocalAddr); \
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}
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/******************************************************************************
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*
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* This macro sends the second byte of the address for a 10 bit address during
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* both read and write operations. It takes care of the details to format the
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* address correctly.
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*
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* @param SlaveAddress contains the address of the slave to send to.
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*
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* @return None.
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*
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* @note Signature: void XIic_Send10BitAddrByte2(u16 SlaveAddress,
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* u8 Operation);
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*
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******************************************************************************/
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#define XIic_Send10BitAddrByte2(SlaveAddress) \
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
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(u32)(SlaveAddress)); \
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/******************************************************************************
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*
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* This macro sends the address for a 7 bit address during both read and write
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* operations. It takes care of the details to format the address correctly.
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*
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* @param SlaveAddress contains the address of the slave to send to.
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* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_Send7BitAddr(u16 SlaveAddress, u8 Operation);
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*
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******************************************************************************/
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#define XIic_Send7BitAddr(SlaveAddress, Operation) \
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{ \
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u8 LocalAddr = (u8)(SlaveAddress << 1); \
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LocalAddr = (LocalAddr & 0xFE) | (Operation); \
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
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(u32) LocalAddr); \
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}
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/******************************************************************************
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*
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* This macro disables the specified interrupts in the Interrupt enable
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* register. It is non-destructive in that the register is read and only the
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* interrupts specified is changed.
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*
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* @param BaseAddress is the base address of the IIC device.
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* @param InterruptMask contains the interrupts to be disabled
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_DisableIntr(u32 BaseAddress, u32 InterruptMask);
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*
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******************************************************************************/
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#define XIic_DisableIntr(BaseAddress, InterruptMask) \
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XIic_WriteIier((BaseAddress), \
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XIic_ReadIier(BaseAddress) & ~(InterruptMask))
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/******************************************************************************
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*
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* This macro enables the specified interrupts in the Interrupt enable
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* register. It is non-destructive in that the register is read and only the
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* interrupts specified is changed.
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*
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* @param BaseAddress is the base address of the IIC device.
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* @param InterruptMask contains the interrupts to be disabled
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_EnableIntr(u32 BaseAddress, u32 InterruptMask);
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*
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******************************************************************************/
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#define XIic_EnableIntr(BaseAddress, InterruptMask) \
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XIic_WriteIier((BaseAddress), \
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XIic_ReadIier(BaseAddress) | (InterruptMask))
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/******************************************************************************
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*
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* This macro clears the specified interrupt in the Interrupt status
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* register. It is non-destructive in that the register is read and only the
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* interrupt specified is cleared. Clearing an interrupt acknowledges it.
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*
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* @param BaseAddress is the base address of the IIC device.
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* @param InterruptMask contains the interrupts to be disabled
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_ClearIntr(u32 BaseAddress, u32 InterruptMask);
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*
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******************************************************************************/
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#define XIic_ClearIntr(BaseAddress, InterruptMask) \
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XIic_WriteIisr((BaseAddress), \
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XIic_ReadIisr(BaseAddress) & (InterruptMask))
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/******************************************************************************
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*
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* This macro clears and enables the specified interrupt in the Interrupt
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* status and enable registers. It is non-destructive in that the registers are
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* read and only the interrupt specified is modified.
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* Clearing an interrupt acknowledges it.
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*
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* @param BaseAddress is the base address of the IIC device.
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* @param InterruptMask contains the interrupts to be cleared and enabled
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_ClearEnableIntr(u32 BaseAddress, u32 InterruptMask);
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*
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******************************************************************************/
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#define XIic_ClearEnableIntr(BaseAddress, InterruptMask) \
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{ \
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XIic_WriteIisr(BaseAddress, \
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(XIic_ReadIisr(BaseAddress) & (InterruptMask))); \
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\
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XIic_WriteIier(BaseAddress, \
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(XIic_ReadIier(BaseAddress) | (InterruptMask))); \
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}
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/******************************************************************************
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*
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* This macro flushes the receive FIFO such that all bytes contained within it
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* are discarded.
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*
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* @param InstancePtr is a pointer to the IIC instance containing the FIFO
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* to be flushed.
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*
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* @return None.
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*
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* @note Signature:
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* void XIic_FlushRxFifo(XIic *InstancePtr);
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*
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******************************************************************************/
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#define XIic_FlushRxFifo(InstancePtr) \
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{ \
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int LoopCnt; \
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u8 BytesToRead = XIic_ReadReg(InstancePtr->BaseAddress, \
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XIIC_RFO_REG_OFFSET) + 1; \
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for(LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) \
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{ \
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XIic_ReadReg(InstancePtr->BaseAddress, \
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XIIC_DRR_REG_OFFSET); \
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} \
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}
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/******************************************************************************
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*
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| 275 |
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* This macro flushes the transmit FIFO such that all bytes contained within it
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* are discarded.
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*
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| 278 |
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* @param InstancePtr is a pointer to the IIC instance containing the FIFO
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* to be flushed.
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| 280 |
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*
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| 281 |
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* @return None.
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*
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| 283 |
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* @note Signature:
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| 284 |
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* void XIic_FlushTxFifo(XIic *InstancePtr);
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| 285 |
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*
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| 286 |
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******************************************************************************/
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| 287 |
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#define XIic_FlushTxFifo(InstancePtr); \
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{ \
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| 289 |
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u32 CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, \
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| 290 |
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XIIC_CR_REG_OFFSET); \
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| 291 |
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, \
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| 292 |
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CntlReg | XIIC_CR_TX_FIFO_RESET_MASK); \
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| 293 |
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, \
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CntlReg); \
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}
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|
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| 297 |
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/******************************************************************************
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| 298 |
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*
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| 299 |
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* This macro reads the next available received byte from the receive FIFO
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* and updates all the data structures to reflect it.
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*
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| 302 |
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* @param InstancePtr is a pointer to the IIC instance to be operated on.
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*
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| 304 |
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* @return None.
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| 305 |
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*
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| 306 |
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* @note Signature:
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| 307 |
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* void XIic_ReadRecvByte(XIic *InstancePtr);
|
| 308 |
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*
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| 309 |
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******************************************************************************/
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| 310 |
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#define XIic_ReadRecvByte(InstancePtr) \
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{ \
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| 312 |
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*InstancePtr->RecvBufferPtr++ = \
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XIic_ReadReg(InstancePtr->BaseAddress, XIIC_DRR_REG_OFFSET); \
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InstancePtr->RecvByteCount--; \
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InstancePtr->Stats.RecvBytes++; \
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}
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| 317 |
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| 318 |
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/******************************************************************************
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| 319 |
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*
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| 320 |
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* This macro writes the next byte to be sent to the transmit FIFO
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| 321 |
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* and updates all the data structures to reflect it.
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| 322 |
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*
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| 323 |
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* @param InstancePtr is a pointer to the IIC instance to be operated on.
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| 324 |
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*
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| 325 |
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* @return None.
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| 326 |
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*
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| 327 |
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* @note Signature:
|
| 328 |
|
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* void XIic_WriteSendByte(XIic *InstancePtr);
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| 329 |
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*
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| 330 |
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******************************************************************************/
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| 331 |
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#define XIic_WriteSendByte(InstancePtr) \
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| 332 |
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{ \
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| 333 |
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_DTR_REG_OFFSET, \
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| 334 |
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*InstancePtr->SendBufferPtr++); \
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| 335 |
|
|
InstancePtr->SendByteCount--; \
|
| 336 |
|
|
InstancePtr->Stats.SendBytes++; \
|
| 337 |
|
|
}
|
| 338 |
|
|
|
| 339 |
|
|
/******************************************************************************
|
| 340 |
|
|
*
|
| 341 |
|
|
* This macro sets up the control register for a master receive operation.
|
| 342 |
|
|
* A write is necessary if a 10 bit operation is being performed.
|
| 343 |
|
|
*
|
| 344 |
|
|
* @param InstancePtr is a pointer to the IIC instance to be operated on.
|
| 345 |
|
|
* @param ControlRegister contains the contents of the IIC device control
|
| 346 |
|
|
* register
|
| 347 |
|
|
* @param ByteCount contains the number of bytes to be received for the
|
| 348 |
|
|
* master receive operation
|
| 349 |
|
|
*
|
| 350 |
|
|
* @return None.
|
| 351 |
|
|
*
|
| 352 |
|
|
* @note Signature:
|
| 353 |
|
|
* void XIic_SetControlRegister(XIic *InstancePtr,
|
| 354 |
|
|
* u8 ControlRegister,
|
| 355 |
|
|
* int ByteCount);
|
| 356 |
|
|
*
|
| 357 |
|
|
******************************************************************************/
|
| 358 |
|
|
#define XIic_SetControlRegister(InstancePtr, ControlRegister, ByteCount) \
|
| 359 |
|
|
{ \
|
| 360 |
|
|
(ControlRegister) &= ~(XIIC_CR_NO_ACK_MASK | XIIC_CR_DIR_IS_TX_MASK); \
|
| 361 |
|
|
if (InstancePtr->Options & XII_SEND_10_BIT_OPTION) { \
|
| 362 |
|
|
(ControlRegister) |= XIIC_CR_DIR_IS_TX_MASK; \
|
| 363 |
|
|
} else { \
|
| 364 |
|
|
if ((ByteCount) == 1) \
|
| 365 |
|
|
{ \
|
| 366 |
|
|
(ControlRegister) |= XIIC_CR_NO_ACK_MASK; \
|
| 367 |
|
|
} \
|
| 368 |
|
|
} \
|
| 369 |
|
|
}
|
| 370 |
|
|
|
| 371 |
|
|
/************************** Function Prototypes ******************************/
|
| 372 |
|
|
|
| 373 |
|
|
extern XIic_Config XIic_ConfigTable[];
|
| 374 |
|
|
|
| 375 |
|
|
/* The following variables are shared across files of the driver and
|
| 376 |
|
|
* are function pointers that are necessary to break dependencies allowing
|
| 377 |
|
|
* optional parts of the driver to be used without condition compilation
|
| 378 |
|
|
*/
|
| 379 |
|
|
extern void (*XIic_AddrAsSlaveFuncPtr) (XIic *InstancePtr);
|
| 380 |
|
|
extern void (*XIic_NotAddrAsSlaveFuncPtr) (XIic *InstancePtr);
|
| 381 |
|
|
extern void (*XIic_RecvSlaveFuncPtr) (XIic *InstancePtr);
|
| 382 |
|
|
extern void (*XIic_SendSlaveFuncPtr) (XIic *InstancePtr);
|
| 383 |
|
|
extern void (*XIic_RecvMasterFuncPtr) (XIic *InstancePtr);
|
| 384 |
|
|
extern void (*XIic_SendMasterFuncPtr) (XIic *InstancePtr);
|
| 385 |
|
|
extern void (*XIic_ArbLostFuncPtr) (XIic *InstancePtr);
|
| 386 |
|
|
extern void (*XIic_BusNotBusyFuncPtr) (XIic *InstancePtr);
|
| 387 |
|
|
|
| 388 |
|
|
void XIic_TransmitFifoFill(XIic *InstancePtr, int Role);
|
| 389 |
|
|
|
| 390 |
|
|
#ifdef __cplusplus
|
| 391 |
|
|
}
|
| 392 |
|
|
#endif
|
| 393 |
|
|
|
| 394 |
|
|
#endif /* end of protection macro */
|
| 395 |
|
|
/** @} */
|
