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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [constr/] [xenie_1_0.xdc] - Blame information for rev 4

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Line No. Rev Author Line
1 4 DFC 
set_property PACKAGE_PIN D24 [get_ports I2C_SDA]
2 
set_property PACKAGE_PIN D25 [get_ports I2C_SCL]
3 
set_property IOSTANDARD LVCMOS33 [get_ports I2C_SCL]
4 
set_property IOSTANDARD LVCMOS33 [get_ports I2C_SDA]
5 
set_property PACKAGE_PIN D21 [get_ports ETH_MDIO_MDC]
6 
set_property PACKAGE_PIN A20 [get_ports ETH_MDIO_MDIO]
7 
set_property IOSTANDARD LVCMOS33 [get_ports ETH_MDIO_MDC]
8 
set_property IOSTANDARD LVCMOS33 [get_ports ETH_MDIO_MDIO]
9 
set_property PACKAGE_PIN F15 [get_ports MB_UART_TX]
10 
set_property PACKAGE_PIN J15 [get_ports MB_UART_RX]
11 
set_property IOSTANDARD LVCMOS33 [get_ports MB_UART_RX]
12 
set_property IOSTANDARD LVCMOS33 [get_ports MB_UART_TX]
13 
set_property PACKAGE_PIN B24 [get_ports {CFG_QSPI_IO[0]}]
14 
set_property PACKAGE_PIN A25 [get_ports {CFG_QSPI_IO[1]}]
15 
set_property PACKAGE_PIN B22 [get_ports {CFG_QSPI_IO[2]}]
16 
set_property PACKAGE_PIN A22 [get_ports {CFG_QSPI_IO[3]}]
17 
set_property PACKAGE_PIN C23 [get_ports CFG_QSPI_SS]
18 
set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[3]}]
19 
set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[2]}]
20 
set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[1]}]
21 
set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[0]}]
22 
set_property IOSTANDARD LVCMOS33 [get_ports CFG_QSPI_SS]
23 
set_property PACKAGE_PIN D26 [get_ports {LEDS[1]}]
24 
set_property PACKAGE_PIN E26 [get_ports {LEDS[0]}]
25 
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}]
26 
set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}]
27 
set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[5]}]
28 
set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[4]}]
29 
set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[3]}]
30 
set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[2]}]
31 
set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[1]}]
32 
set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[0]}]
33 
set_property PACKAGE_PIN C26 [get_ports {ETH_PHY_GPIO[3]}]
34 
set_property PACKAGE_PIN A23 [get_ports {ETH_PHY_GPIO[4]}]
35 
set_property PACKAGE_PIN C22 [get_ports {ETH_PHY_GPIO[5]}]
36 
set_property PACKAGE_PIN E21 [get_ports ETH_PHY_CLK_SRC_SEL]
37 
set_property PACKAGE_PIN B21 [get_ports ETH_PHY_RESETN]
38 
set_property PACKAGE_PIN G24 [get_ports ETH_PHY_RCLK1]
39 
set_property PACKAGE_PIN B20 [get_ports ETH_PHY_INTN]
40 
set_property PACKAGE_PIN H26 [get_ports ALL_SRC_PG]
41 
set_property IOSTANDARD LVCMOS33 [get_ports ALL_SRC_PG]
42 
set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_CLK_SRC_SEL]
43 
set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_INTN]
44 
set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_RCLK1]
45 
set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_RESETN]
46 
set_property PACKAGE_PIN AB11 [get_ports CLK_200M_IN_P]
47 
set_property PACKAGE_PIN C24 [get_ports {ETH_PHY_GPIO[0]}]
48 
set_property PACKAGE_PIN A24 [get_ports {ETH_PHY_GPIO[1]}]
49 
set_property PACKAGE_PIN B26 [get_ports {ETH_PHY_GPIO[2]}]
50 
set_property PACKAGE_PIN R4 [get_ports {ETH_RXAUI_RX_P[0]}]
51 
set_property PACKAGE_PIN N4 [get_ports {ETH_RXAUI_RX_P[1]}]
52 
set_property IOSTANDARD DIFF_SSTL135 [get_ports CLK_200M_IN_P]
53 
set_property IOSTANDARD DIFF_SSTL135 [get_ports CLK_200M_IN_N]
54 
set_property PACKAGE_PIN H6 [get_ports ETH_RXAUI_REFCLK_P]
55 
set_property PACKAGE_PIN H5 [get_ports ETH_RXAUI_REFCLK_N]
56 
 
57 
 
58 
set_property PACKAGE_PIN H14 [get_ports {DBG_PORT[0]}]
59 
set_property PACKAGE_PIN G14 [get_ports {DBG_PORT[1]}]
60 
set_property PACKAGE_PIN F14 [get_ports {DBG_PORT[2]}]
61 
set_property PACKAGE_PIN F13 [get_ports {DBG_PORT[3]}]
62 
set_property PACKAGE_PIN D14 [get_ports {DBG_PORT[4]}]
63 
set_property PACKAGE_PIN D13 [get_ports {DBG_PORT[5]}]
64 
set_property PACKAGE_PIN B10 [get_ports {DBG_PORT[6]}]
65 
set_property PACKAGE_PIN A10 [get_ports {DBG_PORT[7]}]
66 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[0]}]
67 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[1]}]
68 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[2]}]
69 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[3]}]
70 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[4]}]
71 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[5]}]
72 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[6]}]
73 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[7]}]
74 
 
75 
 
76 
set_property PACKAGE_PIN F9 [get_ports {DBG_PORT[8]}]
77 
set_property PACKAGE_PIN F8 [get_ports {DBG_PORT[9]}]
78 
set_property PACKAGE_PIN G11 [get_ports {DBG_PORT[10]}]
79 
set_property PACKAGE_PIN F10 [get_ports {DBG_PORT[11]}]
80 
set_property PACKAGE_PIN J8 [get_ports {DBG_PORT[12]}]
81 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[8]}]
82 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[9]}]
83 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[10]}]
84 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[11]}]
85 
set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[12]}]
86 
 
87 
 
88 
create_clock -period 5.000 -name CLK_200M_IN_P -waveform {0.000 2.500} [get_ports CLK_200M_IN_P]
89 
set_clock_groups -asynchronous -group [get_clocks rxaui_inst/U0/rxaui_block_i/gt0_wrapper_i/gtxe2_i/TXOUTCLK]
90 
 
91 
# Exclude reset of RXAUI core driven by MB GPIO from timing analysis
92 
#set_false_path -from [get_pins {main_bd_inst/axi_gpio_0/U0/gpio_core_1/Dual.gpio_Data_Out_reg[31]/C}]
93 
#set_false_path -from [get_pins {main_bd_inst/axi_gpio_2_netInfo/U0/gpio_core_1/Dual.gpio_OE_reg[*]/C}]
94 
 
95 
 
96 
 
97 
 
98 
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
99 
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
100 
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
101 
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
102 
 

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