Subversion Repositories xenie

2016.4:

 * Version 4.3 (Rev. 7)

 * Revision change in one or more subcores

2016.3:

 * Version 4.3 (Rev. 6)

 * Bug Fix: Changed "IBUF_LOW_PWR" parameter from TRUE to FALSE for IBUFs instantiated at the input of refclk_p/n

 * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

 * Revision change in one or more subcores

2016.2:

 * Version 4.3 (Rev. 5)

 * Assigned 156.25 MHz value to FREQ_HZ bus parameter for refclk_out port

 * Revision change in one or more subcores

2016.1:

 * Version 4.3 (Rev. 4)

 * Changes to HDL library management to support Vivado IP simulation library

 * Revision change in one or more subcores

2015.4.2:

 * Version 4.3 (Rev. 3)

 * No changes

2015.4.1:

 * Version 4.3 (Rev. 3)

 * No changes

2015.4:

 * Version 4.3 (Rev. 3)

 * Updated scripts for upgrade from previous release

 * Revision change in one or more subcores

2015.3:

 * Version 4.3 (Rev. 2)

 * Updated to use the latest GT Ultrascale Wizard v1.6

 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

 * Added support for ultrascale plus devices

 * Added support for xcku095 device family

 * Revision change in one or more subcores

2015.2.1:

 * Version 4.3 (Rev. 1)

 * No changes

2015.2:

 * Version 4.3 (Rev. 1)

 * For Ultrascale transceivers, an update in attributes results in a change in mode of the Rx Equalizer from DFE to LPM.

 * Added initial values to HDL registers to prevent X propagation in behavioral simulations

 * Added support for xq7z100rf1156-1I devices

2015.1:

 * Version 4.3

 * Kintex UltraScale Production support

 * Added support for Virtex Ultrascale GTYE3 transceivers

 * For Ultrascale devices, added an option to select the transceiver reference clock frequency used by the core: select from 125MHz, 156.25MHz or 312.5MHz

 * For Ultrascale devices, added GUI options to select per-core-instance Transceiver locations

 * For Ultrascale devices, issuing a transceiver GTRXRESET after entering near-end loopback and switching the loopback mode to near-end PCS loopback

 * Added a GUI option to enter the transceiver DRP clock frequency used by the core

 * When the transceiver Rx PRBS functionality is enabled through the optional transceiver control and status ports, periodic transceiver RX resets due to lack of lane alignment are inhibited

 * Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]

 * Updated to use the latest GT Ultrascale Wizard v1.5

 * Updated to use the latest 7-Series Transceiver Wizard v3.5.

 * For GTXE2 and GTHE2 7-Series transceivers, the Transceiver Wizard update includes a change in mode of the Rx Equalizer from DFE to LPM.

 * For Automotive Artix-7 devices, fixed the clocking logic by adding a missing clock buffer between the TXOUTCLK from a transceiver and the MMCM.

2014.4.1:

 * Version 4.2 (Rev. 3)

 * No changes

2014.4:

 * Version 4.2 (Rev. 3)

 * Added support for 7-Series Defense-grade, Automotive, and Low Voltage parts

 * Corrected the filename of the VHDL example design demonstration testbench from EntityName.vhd to example_design_testbench.vhd

 * Added a clock domain crossing synchronizer to signal_detect

 * Tidied up whitespace in HDL files for better alignment and indent consistency

 * When the transceiver Rx PRBS functionality is enabled through the optional transceiver control and status ports, periodic transceiver RX resets due to lack of lane synchronization are inhibited

 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time

 * Reducing the default transceiver DRPCLK frequency in the cores out-of-context XDC file from 200MHz to 125MHz.  This is the default frequency used when the core is synthesised in isolation, and is overridden when the core is implemented in a full design.

2014.3:

 * Version 4.2 (Rev. 2)

 * IBUF's have been added to the refclk_p and refclk_n inputs before the IBUFGTE2 primitive for all 7-Series devices.  These were previously inferred by the tools, so there is no change to overall logical functionality.  However, this does enable Vivado commands such as report_clock_networks to work correctly at all applicable Vivado stages

 * Updated to use the latest GT Ultrascale Wizard

 * Revised the Ultrascale reset logic to satisfy the minimum reset pulse width requirements for reset inputs of the Ultrascale GT Wizard instantiation

 * Revised the Ultrascale reset logic to assert the Rx reset to the core when the transceviers are placed in powerdown

 * For VHDL projects, all core VHDL files are now compiled into a core specific library (rxaui_v4_3 for this core version) with the exception of the top level VHDL wrapper file for the core which remains in the default library (named xil_defaultlib unless overridden by the user).  This makes the core consistent with other Xilinx IP.  No changes to core instantiations are required in customer HDL files

 * Input port default tie-off values for IP Integrator have been added to signal_detect and removed from signals which must be connected (for example input clock ports)

 * The directory path to the UltraScale FPGAs Transceivers Wizard output products has been shortened

2014.2:

 * Version 4.2 (Rev. 1)

 * Added support for Z-7015 devices

 * Updated to use the latest GT Ultrascale Wizard

 * Fixed an issue on the GUI symbol where the gt_dmonitorout ports did not appear in the transcevier_debug bus interfaces when targeting the GTHE2 and GTXE2 transceivers

2014.1:

 * Version 4.2

 * Virtex UltraScale Pre-Production support

 * Added support for extra Artix-7 devices (by enabling support for low-cost wire-bonded packages)

 * Fixed the operation of the mgt_rx_reset_inprocess signal (part of the GTPE2/GTHE2 reset logic)(see Xilinx Answer 59860)

 * Fixed GTPE2 reliability issues by ensuring that the GTPE2 cannot get permanently stuck in the wrong internal datawidth setting during reset cycles. (see Xilinx Answer 59861)

 * Fixed powerdown reliability issues by ensuring that the transceiver phase alignment state machine is reset when the powerdown state is removed. (see Xilinx Answer 59292)

 * Fixed the SIM_RESET_SPEEDUP attribute setting (now set to FALSE) for GTPE2 and GTHE2 transceivers, as per the 7-Series FPGAs Transceivers User Guides.  This is required in order to simulate correctly the transcevier reset/initialization sequence; this leads to longer reset/initialization simulation times.

 * Added missing pll0outrefclk_out port to the IP GUI customization symbol and IP integrator symbol diagrams.  This port is now present for Artix-7 designs when the shared logic is included in the core

 * Corrected the Ultrascale transceiver debug port widths in the IP GUI customization symbol and IP integrator symbol diagrams

 * Added clock frequency metadata to the Quad PLL and GT reference clocks for use in IPI only

 * Added missing XDC constraints on the MDIO signal inputs to ease timing closure (see Xilinx Answer 59914)

 * Added missing powerdown signals from the core to the Ultrascale transceiver

 * Corrected the mgt_txcharisk signal assignment in Verilog projects for Ultrascale devices

 * Corrected the 7 Series transceiver debug port rxcdrhold to route to the transceiver

 * Added commented example of GT placement in example design XDC

 * Internal device family name change, no functional changes

2013.4:

 * Version 4.1

 * Kintex UltraScale Pre-Production support

 * Increased the number of optional transceiver control and status ports.

 * The mark_debug attribute was removed from all nets so that the Xilinx lab tools would not be prepopulated with an undesired configuration.

2013.3:

 * Version 4.0

 * Moved Artix-7 and Zynq-7000 devices to production

 * FBG packages enabled

 * Fixed 7 series GTP reset logic (AR 56313)

 * Added support for IP Integrator.

 * Updated synchronizers to improve Mean Time Between Failures (MTBF) for metastability.

 * GUI 'Shared Logic' section revised to make the options clearer

 * The HDL parameter WRAPPER_SIM_GTRESET_SPEEDUP has been removed. To control the GT simulation parameter refer to the Product Guide.

 * clk156 is now always a core output (clk156_out) driven by a BUFH. This clock cannot be shared with other RXAUI core instances due to the GT buffer bypass mechanism.

 * The gt_control port has been removed and the debug port width changed to just contain RXAUI information. To enable the transceiver control ports recustomize and enable 'additional transceiver ports'

 * DRP ports are now only present if the additional transceiver control ports are enabled

 * Top level ports changed to make connecting a core with shared logic to a core without shared logic easier

 * Example Design changed to include a synthesizable pattern generator and checker.

 * Clock buffer changed from a BUFG to BUFH. To revert this back to a BUFG please see 'Unlink IP' section of UG896

 * Path to the transceivers has changed. This is now of the form */gt0_gt_wrapper_i/gtxe2_i. This will affect constraints if you use the X0Y1 style of naming. (Pin package constraints unchanged)

 * Updated 7 Series Transceiver Attributes (including AR 56332)

 * QPLL for GTH transceivers is now powered down by default (unused)

 * Fixed VHDL chbond_counter logic - core could fail to issue a reset if all lanes achieved sync

2013.2:

 * Version 3.0 (Rev. 1)

 * Fixed wrong set_false_path in XDC corresponding to AR 55229

 * Fixed Clock Correction attributes in GTP

 * Fixed RX termination attributes for 7 series GTP and GTH (AR 55840)

2013.1:

 * Version 3.0

 * Zynq support

 * The previous 'core block' level is now the top level of the core. This includes transicever instances. The transceiver instances and supporting logic are still delivered as plain HDL.

 * Core now provides a 'hierarchical' XDC file. This is automatically applied to the core by the Vivado tools

 * 'Support' Level created in example output products. This contains the clocking (including the transeiver common PLL) and reset logic

 * MARK_DEBUG attribute added to various signals to aid debug

 * New port - debug port added to aid debug when connected to an external processor the align_status and sync_status ports are now part of this

 * New port - gt_control port added to allow control of transceiver specific features

 * Support for Marvell Mode removed

 * Added support for the out-of-context flow

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