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URL https://opencores.org/ocsvn/xenie/xenie/trunk

Subversion Repositories xenie

[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [ip/] [rxaui_0/] [rxaui_0.xml] - Blame information for rev 4

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Line No. Rev Author Line
1 4 DFC
2
3 
  xilinx.com
4 
  customized_ip
5 
  rxaui_0
6 
  1.0
7
8
9 
      mdio_interface
10 
      mdio_interface
11 
      mdio interface
12
13
14
15
16
17
18 
            MDC
19
20
21 
            mdc
22
23
24
25
26 
            MDIO_I
27
28
29 
            mdio_in
30
31
32
33
34 
            MDIO_O
35
36
37 
            mdio_out
38
39
40
41
42 
            MDIO_T
43
44
45 
            mdio_tri
46
47
48
49
50
51
52 
            true
53
54
55
56
57
58 
      xgmii_interface
59 
      xgmii_interface
60
61
62
63
64
65
66 
            RXC
67
68
69 
            xgmii_rxc
70
71
72
73
74 
            RXD
75
76
77 
            xgmii_rxd
78
79
80
81
82 
            TXC
83
84
85 
            xgmii_txc
86
87
88
89
90 
            TXD
91
92
93 
            xgmii_txd
94
95
96
97
98
99 
      gt0_drp
100 
      gt0_drp
101 
      DRP Interface to Transceiver 0
102
103
104
105
106
107
108 
            DADDR
109
110
111 
            gt0_drpaddr
112
113
114
115
116 
            DEN
117
118
119 
            gt0_drpen
120
121
122
123
124 
            DI
125
126
127 
            gt0_drpdi
128
129
130
131
132 
            DO
133
134
135 
            gt0_drpdo
136
137
138
139
140 
            DRDY
141
142
143 
            gt0_drprdy
144
145
146
147
148 
            DWE
149
150
151 
            gt0_drpwe
152
153
154
155
156
157
158 
            false
159
160
161
162
163
164 
      gt1_drp
165 
      gt1_drp
166 
      DRP Interface to Transceiver 1
167
168
169
170
171
172
173 
            DADDR
174
175
176 
            gt1_drpaddr
177
178
179
180
181 
            DEN
182
183
184 
            gt1_drpen
185
186
187
188
189 
            DI
190
191
192 
            gt1_drpdi
193
194
195
196
197 
            DO
198
199
200 
            gt1_drpdo
201
202
203
204
205 
            DRDY
206
207
208 
            gt1_drprdy
209
210
211
212
213 
            DWE
214
215
216 
            gt1_drpwe
217
218
219
220
221
222
223 
            false
224
225
226
227
228
229 
      drp0
230 
      drp0
231 
      DRP Interface to Transceiver 0
232
233
234
235
236
237
238 
            DADDR
239
240
241 
            gt0_drpaddr
242
243
244
245
246 
            DEN
247
248
249 
            gt0_drpen
250
251
252
253
254 
            DI
255
256
257 
            gt0_drpdi
258
259
260
261
262 
            DO
263
264
265 
            gt0_drpdo
266
267
268
269
270 
            DRDY
271
272
273 
            gt0_drprdy
274
275
276
277
278 
            DWE
279
280
281 
            gt0_drpwe
282
283
284
285
286
287
288 
            false
289
290
291
292
293
294 
      drp1
295 
      drp1
296 
      DRP Interface to Transceiver 1
297
298
299
300
301
302
303 
            DADDR
304
305
306 
            gt1_drpaddr
307
308
309
310
311 
            DEN
312
313
314 
            gt1_drpen
315
316
317
318
319 
            DI
320
321
322 
            gt1_drpdi
323
324
325
326
327 
            DO
328
329
330 
            gt1_drpdo
331
332
333
334
335 
            DRDY
336
337
338 
            gt1_drprdy
339
340
341
342
343 
            DWE
344
345
346 
            gt1_drpwe
347
348
349
350
351
352
353 
            false
354
355
356
357
358
359 
      dclk_port
360 
      dclk
361 
      DRP Clock - free running clock used to clock DRP and some logic.
362
363
364
365
366
367
368 
            CLK
369
370
371 
            dclk
372
373
374
375
376
377 
          ASSOCIATED_BUSIF
378 
          drp0:drp1
379
380
381
382
383 
      refclk_diff_port
384 
      refclk
385 
      Differential GT reference clock
386
387
388
389
390
391
392 
            CLK_N
393
394
395 
            refclk_n
396
397
398
399
400 
            CLK_P
401
402
403 
            refclk_p
404
405
406
407
408
409
410 
            true
411
412
413
414
415
416 
      refclk_port
417 
      refclk
418 
      GT reference clock
419
420
421
422
423
424
425 
            CLK
426
427
428 
            refclk
429
430
431
432
433
434
435 
            false
436
437
438
439
440
441 
      refclk_out_port
442 
      refclk_out
443 
      Reference clock output from the differential transceiver clock buffer.
444
445
446
447
448
449
450 
            CLK
451
452
453 
            refclk_out
454
455
456
457
458
459 
          FREQ_HZ
460 
          156250000
461
462
463
464
465
466 
            true
467
468
469
470
471
472 
      clk156_out_port
473 
      clk156_out
474 
      156.25MHz output clock. Can be used to drive logic, but not another RXAUI instance.
475
476
477
478
479
480
481 
            CLK
482
483
484 
            clk156_out
485
486
487
488
489
490 
          ASSOCIATED_BUSIF
491 
          xgmii_interface
492
493
494 
          FREQ_HZ
495 
          156250000
496
497
498
499
500 
      qpll0outclk_out_port
501 
      qpll0outclk_out
502 
      Output from the quad PLL port QPLL0OUTCLK.
503
504
505
506
507
508
509 
            CLK
510
511
512 
            qpll0outclk_out
513
514
515
516
517
518
519 
            false
520
521
522
523
524
525 
      qpll0outrefclk_out_port
526 
      qpll0outrefclk_out
527 
      Output from the quad PLL port QPLL0OUTREFCLK.
528
529
530
531
532
533
534 
            CLK
535
536
537 
            qpll0outrefclk_out
538
539
540
541
542
543
544 
            false
545
546
547
548
549
550 
      qpll0outclk_port
551 
      qpll0outclk
552 
      Connect to the quad PLL output clock QPLL0OUTCLK.
553
554
555
556
557
558
559 
            CLK
560
561
562 
            qpll0outclk
563
564
565
566
567
568
569 
            false
570
571
572
573
574
575 
      qpll0outrefclk_port
576 
      qpll0outrefclk
577 
      Connect to the quad PLL output reference clock QPLL0OUTREFCLK.
578
579
580
581
582
583
584 
            CLK
585
586
587 
            qpll0outrefclk
588
589
590
591
592
593
594 
            false
595
596
597
598
599
600 
      qplloutclk_out_port
601 
      qplloutclk_out
602 
      Output from the quad PLL port QPLLOUTCLK.
603
604
605
606
607
608
609 
            CLK
610
611
612 
            qplloutclk_out
613
614
615
616
617
618
619 
            true
620
621
622
623
624
625 
      qplloutclk_port
626 
      qplloutclk
627 
      Connect to the quad PLL output clock QPLLOUTCLK.
628
629
630
631
632
633
634 
            CLK
635
636
637 
            qplloutclk
638
639
640
641
642
643
644 
            false
645
646
647
648
649
650 
      qplloutrefclk_out_port
651 
      qplloutrefclk_out
652 
      Output from the quad PLL port QPLLREFCLK.
653
654
655
656
657
658
659 
            CLK
660
661
662 
            qplloutrefclk_out
663
664
665
666
667
668
669 
            true
670
671
672
673
674
675 
      qplloutrefclk_port
676 
      qplloutrefclk
677 
      Connect to the quad PLL output reference clock QPLLOUTREFCLK.
678
679
680
681
682
683
684 
            CLK
685
686
687 
            qplloutrefclk
688
689
690
691
692
693
694 
            false
695
696
697
698
699
700 
      pll0outclk_out_port
701 
      pll0outclk_out
702 
      Output from the GTPE2_COMMON PLL port PLL0OUTCLK.
703
704
705
706
707
708
709 
            CLK
710
711
712 
            pll0outclk_out
713
714
715
716
717
718
719 
            false
720
721
722
723
724
725 
      pll0outclk_port
726 
      pll0outclk
727 
      Connect to the GTPE2_COMMON PLL port PLL0OUTCLK.
728
729
730
731
732
733
734 
            CLK
735
736
737 
            pll0outclk
738
739
740
741
742
743
744 
            false
745
746
747
748
749
750 
      pll0outrefclk_out_port
751 
      pll0outrefclk_out
752 
      Output from the GTPE2_COMMON PLL port PLL0OUTREFCLK
753
754
755
756
757
758
759 
            CLK
760
761
762 
            pll0outrefclk_out
763
764
765
766
767
768
769 
            false
770
771
772
773
774
775 
      pll0outrefclk_port
776 
      pll0outrefclk
777 
      Connect to the GTPE2_COMMON PLL REFCLK port PLL0OUTREFCLK
778
779
780
781
782
783
784 
            CLK
785
786
787 
            pll0outrefclk
788
789
790
791
792
793
794 
            false
795
796
797
798
799
800 
      pll1outclk_out_out_port
801 
      pll1outclk_out
802 
      Output from the GTPE2_COMMON PLL port PLL1OUTCLK.
803
804
805
806
807
808
809 
            CLK
810
811
812 
            pll1outclk_out
813
814
815
816
817
818
819 
            false
820
821
822
823
824
825 
      pll1outclk_port
826 
      pll1outclk
827 
      Connect to the GTPE2_COMMON PLL port PLL1OUTCLK.
828
829
830
831
832
833
834 
            CLK
835
836
837 
            pll1outclk
838
839
840
841
842
843
844 
            false
845
846
847
848
849
850 
      pll1outrefclk_out_port
851 
      pll1outrefclk_out
852 
      Output from the GTPE2_COMMON PLL port PLL1OUTREFCLK
853
854
855
856
857
858
859 
            CLK
860
861
862 
            pll1outrefclk_out
863
864
865
866
867
868
869 
            false
870
871
872
873
874
875 
      pll1outrefclk_port
876 
      pll1outrefclk
877 
      Connect to the GTPE2_COMMON PLL REFCLK port PLL1OUTREFCLK
878
879
880
881
882
883
884 
            CLK
885
886
887 
            pll1outrefclk
888
889
890
891
892
893
894 
            false
895
896
897
898
899
900 
      reset
901 
      reset
902 
      Asynchronous Reset
903
904
905
906
907
908
909 
            RST
910
911
912 
            reset
913
914
915
916
917
918 
          POLARITY
919 
          ACTIVE_HIGH
920
921
922
923
924 
      transceiver_debug0
925 
      transceiver_debug0
926 
      Transceiver Debug Interface
927
928
929
930
931
932
933 
            cplllock
934
935
936 
            gt0_cplllock_out
937
938
939
940
941 
            dmonitorout
942
943
944 
            gt0_dmonitorout_out
945
946
947
948
949 
            eyescandataerror
950
951
952 
            gt0_eyescandataerror_out
953
954
955
956
957 
            eyescanreset
958
959
960 
            gt0_eyescanreset_in
961
962
963
964
965 
            eyescantrigger
966
967
968 
            gt0_eyescantrigger_in
969
970
971
972
973 
            loopback
974
975
976 
            gt0_loopback_in
977
978
979
980
981 
            rxbufstatus
982
983
984 
            gt0_rxbufstatus_out
985
986
987
988
989 
            rxcdrhold
990
991
992 
            gt0_rxcdrhold_in
993
994
995
996
997 
            rxcommadet
998
999
1000 
            gt0_rxcommadet_out
1001
1002
1003
1004
1005 
            rxdfelpmreset
1006
1007
1008 
            gt0_rxdfelpmreset_in
1009
1010
1011
1012
1013 
            rxdisperr
1014
1015
1016 
            gt0_rxdisperr_out
1017
1018
1019
1020
1021 
            rxlpmen
1022
1023
1024 
            gt0_rxlpmen_in
1025
1026
1027
1028
1029 
            rxlpmhfhold
1030
1031
1032 
            gt0_rxlpmhfhold_in
1033
1034
1035
1036
1037 
            rxlpmhfovrden
1038
1039
1040 
            gt0_rxlpmhfovrden_in
1041
1042
1043
1044
1045 
            rxlpmlfhold
1046
1047
1048 
            gt0_rxlpmlfhold_in
1049
1050
1051
1052
1053 
            rxlpmlfovrden
1054
1055
1056 
            gt0_rxlpmlfovrden_in
1057
1058
1059
1060
1061 
            rxlpmreset
1062
1063
1064 
            gt0_rxlpmreset_in
1065
1066
1067
1068
1069 
            rxmonitorout
1070
1071
1072 
            gt0_rxmonitorout_out
1073
1074
1075
1076
1077 
            rxmonitorsel
1078
1079
1080 
            gt0_rxmonitorsel_in
1081
1082
1083
1084
1085 
            rxnotintable
1086
1087
1088 
            gt0_rxnotintable_out
1089
1090
1091
1092
1093 
            rxpcsreset
1094
1095
1096 
            gt0_rxpcsreset_in
1097
1098
1099
1100
1101 
            rxpmareset
1102
1103
1104 
            gt0_rxpmareset_in
1105
1106
1107
1108
1109 
            rxpmaresetdone
1110
1111
1112 
            gt0_rxpmaresetdone_out
1113
1114
1115
1116
1117 
            rxpolarity
1118
1119
1120 
            gt0_rxpolarity_in
1121
1122
1123
1124
1125 
            rxprbscntreset
1126
1127
1128 
            gt0_rxprbscntreset_in
1129
1130
1131
1132
1133 
            rxprbserr
1134
1135
1136 
            gt0_rxprbserr_out
1137
1138
1139
1140
1141 
            rxprbssel
1142
1143
1144 
            gt0_rxprbssel_in
1145
1146
1147
1148
1149 
            rxrate
1150
1151
1152 
            gt0_rxrate_in
1153
1154
1155
1156
1157 
            rxresetdone
1158
1159
1160 
            gt0_rxresetdone_out
1161
1162
1163
1164
1165 
            txdiffctrl
1166
1167
1168 
            gt0_txdiffctrl_in
1169
1170
1171
1172
1173 
            txdlysresetdone
1174
1175
1176 
            gt0_txdlysresetdone_out
1177
1178
1179
1180
1181 
            txinhibit
1182
1183
1184 
            gt0_txinhibit_in
1185
1186
1187
1188
1189 
            txpcsreset
1190
1191
1192 
            gt0_txpcsreset_in
1193
1194
1195
1196
1197 
            txphaligndone
1198
1199
1200 
            gt0_txphaligndone_out
1201
1202
1203
1204
1205 
            txphinitdone
1206
1207
1208 
            gt0_txphinitdone_out
1209
1210
1211
1212
1213 
            txpmareset
1214
1215
1216 
            gt0_txpmareset_in
1217
1218
1219
1220
1221 
            txpolarity
1222
1223
1224 
            gt0_txpolarity_in
1225
1226
1227
1228
1229 
            txpostcursor
1230
1231
1232 
            gt0_txpostcursor_in
1233
1234
1235
1236
1237 
            txprbsforceerr
1238
1239
1240 
            gt0_txprbsforceerr_in
1241
1242
1243
1244
1245 
            txprbssel
1246
1247
1248 
            gt0_txprbssel_in
1249
1250
1251
1252
1253 
            txprecursor
1254
1255
1256 
            gt0_txprecursor_in
1257
1258
1259
1260
1261 
            txresetdone
1262
1263
1264 
            gt0_txresetdone_out
1265
1266
1267
1268
1269
1270
1271 
            false
1272
1273
1274
1275
1276
1277 
      transceiver_debug1
1278 
      transceiver_debug1
1279 
      Transceiver Debug Interface
1280
1281
1282
1283
1284
1285
1286 
            cplllock
1287
1288
1289 
            gt1_cplllock_out
1290
1291
1292
1293
1294 
            dmonitorout
1295
1296
1297 
            gt1_dmonitorout_out
1298
1299
1300
1301
1302 
            eyescandataerror
1303
1304
1305 
            gt1_eyescandataerror_out
1306
1307
1308
1309
1310 
            eyescanreset
1311
1312
1313 
            gt1_eyescanreset_in
1314
1315
1316
1317
1318 
            eyescantrigger
1319
1320
1321 
            gt1_eyescantrigger_in
1322
1323
1324
1325
1326 
            loopback
1327
1328
1329 
            gt1_loopback_in
1330
1331
1332
1333
1334 
            rxbufstatus
1335
1336
1337 
            gt1_rxbufstatus_out
1338
1339
1340
1341
1342 
            rxcdrhold
1343
1344
1345 
            gt1_rxcdrhold_in
1346
1347
1348
1349
1350 
            rxcommadet
1351
1352
1353 
            gt1_rxcommadet_out
1354
1355
1356
1357
1358 
            rxdfelpmreset
1359
1360
1361 
            gt1_rxdfelpmreset_in
1362
1363
1364
1365
1366 
            rxdisperr
1367
1368
1369 
            gt1_rxdisperr_out
1370
1371
1372
1373
1374 
            rxlpmen
1375
1376
1377 
            gt1_rxlpmen_in
1378
1379
1380
1381
1382 
            rxlpmhfhold
1383
1384
1385 
            gt1_rxlpmhfhold_in
1386
1387
1388
1389
1390 
            rxlpmhfovrden
1391
1392
1393 
            gt1_rxlpmhfovrden_in
1394
1395
1396
1397
1398 
            rxlpmlfhold
1399
1400
1401 
            gt1_rxlpmlfhold_in
1402
1403
1404
1405
1406 
            rxlpmlfovrden
1407
1408
1409 
            gt1_rxlpmlfovrden_in
1410
1411
1412
1413
1414 
            rxlpmreset
1415
1416
1417 
            gt1_rxlpmreset_in
1418
1419
1420
1421
1422 
            rxmonitorout
1423
1424
1425 
            gt1_rxmonitorout_out
1426
1427
1428
1429
1430 
            rxmonitorsel
1431
1432
1433 
            gt1_rxmonitorsel_in
1434
1435
1436
1437
1438 
            rxnotintable
1439
1440
1441 
            gt1_rxnotintable_out
1442
1443
1444
1445
1446 
            rxpcsreset
1447
1448
1449 
            gt1_rxpcsreset_in
1450
1451
1452
1453
1454 
            rxpmareset
1455
1456
1457 
            gt1_rxpmareset_in
1458
1459
1460
1461
1462 
            rxpmaresetdone
1463
1464
1465 
            gt1_rxpmaresetdone_out
1466
1467
1468
1469
1470 
            rxpolarity
1471
1472
1473 
            gt1_rxpolarity_in
1474
1475
1476
1477
1478 
            rxprbscntreset
1479
1480
1481 
            gt1_rxprbscntreset_in
1482
1483
1484
1485
1486 
            rxprbserr
1487
1488
1489 
            gt1_rxprbserr_out
1490
1491
1492
1493
1494 
            rxprbssel
1495
1496
1497 
            gt1_rxprbssel_in
1498
1499
1500
1501
1502 
            rxrate
1503
1504
1505 
            gt1_rxrate_in
1506
1507
1508
1509
1510 
            rxresetdone
1511
1512
1513 
            gt1_rxresetdone_out
1514
1515
1516
1517
1518 
            txdiffctrl
1519
1520
1521 
            gt1_txdiffctrl_in
1522
1523
1524
1525
1526 
            txdlysresetdone
1527
1528
1529 
            gt1_txdlysresetdone_out
1530
1531
1532
1533
1534 
            txinhibit
1535
1536
1537 
            gt1_txinhibit_in
1538
1539
1540
1541
1542 
            txpcsreset
1543
1544
1545 
            gt1_txpcsreset_in
1546
1547
1548
1549
1550 
            txphaligndone
1551
1552
1553 
            gt1_txphaligndone_out
1554
1555
1556
1557
1558 
            txphinitdone
1559
1560
1561 
            gt1_txphinitdone_out
1562
1563
1564
1565
1566 
            txpmareset
1567
1568
1569 
            gt1_txpmareset_in
1570
1571
1572
1573
1574 
            txpolarity
1575
1576
1577 
            gt1_txpolarity_in
1578
1579
1580
1581
1582 
            txpostcursor
1583
1584
1585 
            gt1_txpostcursor_in
1586
1587
1588
1589
1590 
            txprbsforceerr
1591
1592
1593 
            gt1_txprbsforceerr_in
1594
1595
1596
1597
1598 
            txprbssel
1599
1600
1601 
            gt1_txprbssel_in
1602
1603
1604
1605
1606 
            txprecursor
1607
1608
1609 
            gt1_txprecursor_in
1610
1611
1612
1613
1614 
            txresetdone
1615
1616
1617 
            gt1_txresetdone_out
1618
1619
1620
1621
1622
1623
1624 
            false
1625
1626
1627
1628
1629
1630 
      transceiver_debug
1631 
      transceiver_debug
1632 
      Transceiver Debug Interface
1633
1634
1635
1636
1637
1638
1639 
            dmonitorout
1640
1641
1642 
            gt_dmonitorout
1643
1644
1645
1646
1647 
            eyescandataerror
1648
1649
1650 
            gt_eyescandataerror
1651
1652
1653
1654
1655 
            eyescanreset
1656
1657
1658 
            gt_eyescanreset
1659
1660
1661
1662
1663 
            eyescantrigger
1664
1665
1666 
            gt_eyescantrigger
1667
1668
1669
1670
1671 
            loopback
1672
1673
1674 
            gt_loopback
1675
1676
1677
1678
1679 
            pcsrsvdin
1680
1681
1682 
            gt_pcsrsvdin
1683
1684
1685
1686
1687 
            rxbufstatus
1688
1689
1690 
            gt_rxbufstatus
1691
1692
1693
1694
1695 
            rxcdrhold
1696
1697
1698 
            gt_rxcdrhold
1699
1700
1701
1702
1703 
            rxcommadet
1704
1705
1706 
            gt_rxcommadet
1707
1708
1709
1710
1711 
            rxdfelpmreset
1712
1713
1714 
            gt_rxdfelpmreset
1715
1716
1717
1718
1719 
            rxdisperr
1720
1721
1722 
            gt_rxdisperr
1723
1724
1725
1726
1727 
            rxlpmen
1728
1729
1730 
            gt_rxlpmen
1731
1732
1733
1734
1735 
            rxnotintable
1736
1737
1738 
            gt_rxnotintable
1739
1740
1741
1742
1743 
            rxpcsreset
1744
1745
1746 
            gt_rxpcsreset
1747
1748
1749
1750
1751 
            rxpmareset
1752
1753
1754 
            gt_rxpmareset
1755
1756
1757
1758
1759 
            rxpmaresetdone
1760
1761
1762 
            gt_rxpmaresetdone
1763
1764
1765
1766
1767 
            rxpolarity
1768
1769
1770 
            gt_rxpolarity
1771
1772
1773
1774
1775 
            rxprbscntreset
1776
1777
1778 
            gt_rxprbscntreset
1779
1780
1781
1782
1783 
            rxprbserr
1784
1785
1786 
            gt_rxprbserr
1787
1788
1789
1790
1791 
            rxprbssel
1792
1793
1794 
            gt_rxprbssel
1795
1796
1797
1798
1799 
            rxrate
1800
1801
1802 
            gt_rxrate
1803
1804
1805
1806
1807 
            rxresetdone
1808
1809
1810 
            gt_rxresetdone
1811
1812
1813
1814
1815 
            txdiffctrl
1816
1817
1818 
            gt_txdiffctrl
1819
1820
1821
1822
1823 
            txdlysresetdone
1824
1825
1826 
            gt_txdlysresetdone
1827
1828
1829
1830
1831 
            txinhibit
1832
1833
1834 
            gt_txinhibit
1835
1836
1837
1838
1839 
            txpcsreset
1840
1841
1842 
            gt_txpcsreset
1843
1844
1845
1846
1847 
            txphaligndone
1848
1849
1850 
            gt_txphaligndone
1851
1852
1853
1854
1855 
            txphinitdone
1856
1857
1858 
            gt_txphinitdone
1859
1860
1861
1862
1863 
            txpmareset
1864
1865
1866 
            gt_txpmareset
1867
1868
1869
1870
1871 
            txpolarity
1872
1873
1874 
            gt_txpolarity
1875
1876
1877
1878
1879 
            txpostcursor
1880
1881
1882 
            gt_txpostcursor
1883
1884
1885
1886
1887 
            txprbsforceerr
1888
1889
1890 
            gt_txprbsforceerr
1891
1892
1893
1894
1895 
            txprbssel
1896
1897
1898 
            gt_txprbssel
1899
1900
1901
1902
1903 
            txprecursor
1904
1905
1906 
            gt_txprecursor
1907
1908
1909
1910
1911 
            txresetdone
1912
1913
1914 
            gt_txresetdone
1915
1916
1917
1918
1919
1920
1921 
            false
1922
1923
1924
1925
1926
1927
1928
1929
1930 
        xilinx_elaboratesubcores
1931 
        Elaborate Sub-Cores
1932 
        :vivado.xilinx.com:elaborate.subcores
1933
1934
1935 
            boundaryCRC
1936 
            b763c113
1937
1938
1939 
            boundaryCRCversion
1940 
            1
1941
1942
1943 
            customizationCRC
1944 
            4a58e9cb
1945
1946
1947 
            customizationCRCversion
1948 
            6
1949
1950
1951
1952
1953 
        xilinx_vhdlinstantiationtemplate
1954 
        VHDL Instantiation Template
1955 
        vhdlSource:vivado.xilinx.com:synthesis.template
1956 
        vhdl
1957
1958 
          xilinx_vhdlinstantiationtemplate_view_fileset
1959
1960
1961
1962 
            GENtimestamp
1963 
            Wed Mar 29 06:25:56 UTC 2017
1964
1965
1966 
            boundaryCRC
1967 
            b763c113
1968
1969
1970 
            boundaryCRCversion
1971 
            1
1972
1973
1974 
            customizationCRC
1975 
            4a58e9cb
1976
1977
1978 
            customizationCRCversion
1979 
            6
1980
1981
1982
1983
1984 
        xilinx_versioninformation
1985 
        Version Information
1986 
        :vivado.xilinx.com:docs.versioninfo
1987
1988 
          xilinx_versioninformation_view_fileset
1989
1990
1991
1992 
            GENtimestamp
1993 
            Wed Mar 29 06:26:02 UTC 2017
1994
1995
1996 
            boundaryCRC
1997 
            b763c113
1998
1999
2000 
            boundaryCRCversion
2001 
            1
2002
2003
2004 
            customizationCRC
2005 
            4a58e9cb
2006
2007
2008 
            customizationCRCversion
2009 
            6
2010
2011
2012
2013
2014 
        xilinx_anylanguagesynthesis
2015 
        Synthesis
2016 
        :vivado.xilinx.com:synthesis
2017
2018 
          xilinx_anylanguagesynthesis_xilinx_com_ip_xaui_12_2__ref_view_fileset
2019
2020
2021 
          xilinx_anylanguagesynthesis_view_fileset
2022
2023
2024
2025 
            GENtimestamp
2026 
            Wed Mar 29 07:00:39 UTC 2017
2027
2028
2029 
            boundaryCRC
2030 
            b763c113
2031
2032
2033 
            boundaryCRCversion
2034 
            1
2035
2036
2037 
            customizationCRC
2038 
            4a58e9cb
2039
2040
2041 
            customizationCRCversion
2042 
            6
2043
2044
2045
2046
2047 
        xilinx_vhdlsynthesiswrapper
2048 
        VHDL Synthesis Wrapper
2049 
        vhdlSource:vivado.xilinx.com:synthesis.wrapper
2050 
        vhdl
2051
2052 
          xilinx_vhdlsynthesiswrapper_view_fileset
2053
2054
2055
2056 
            GENtimestamp
2057 
            Wed Mar 29 07:00:40 UTC 2017
2058
2059
2060 
            boundaryCRC
2061 
            b763c113
2062
2063
2064 
            boundaryCRCversion
2065 
            1
2066
2067
2068 
            customizationCRC
2069 
            4a58e9cb
2070
2071
2072 
            customizationCRCversion
2073 
            6
2074
2075
2076
2077
2078 
        xilinx_anylanguagebehavioralsimulation
2079 
        Simulation
2080 
        :vivado.xilinx.com:simulation
2081
2082 
          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xaui_12_2__ref_view_fileset
2083
2084
2085 
          xilinx_anylanguagebehavioralsimulation_view_fileset
2086
2087
2088
2089 
            GENtimestamp
2090 
            Wed Mar 29 07:00:39 UTC 2017
2091
2092
2093 
            boundaryCRC
2094 
            b763c113
2095
2096
2097 
            boundaryCRCversion
2098 
            1
2099
2100
2101 
            customizationCRC
2102 
            a4d2a29f
2103
2104
2105 
            customizationCRCversion
2106 
            6
2107
2108
2109
2110
2111 
        xilinx_vhdlsimulationwrapper
2112 
        VHDL Simulation Wrapper
2113 
        vhdlSource:vivado.xilinx.com:simulation.wrapper
2114 
        vhdl
2115
2116 
          xilinx_vhdlsimulationwrapper_view_fileset
2117
2118
2119
2120 
            GENtimestamp
2121 
            Wed Mar 29 07:00:40 UTC 2017
2122
2123
2124 
            boundaryCRC
2125 
            b763c113
2126
2127
2128 
            boundaryCRCversion
2129 
            1
2130
2131
2132 
            customizationCRC
2133 
            a4d2a29f
2134
2135
2136 
            customizationCRCversion
2137 
            6
2138
2139
2140
2141
2142 
        xilinx_externalfiles
2143 
        External Files
2144 
        :vivado.xilinx.com:external.files
2145
2146 
          xilinx_externalfiles_view_fileset
2147
2148
2149
2150 
            GENtimestamp
2151 
            Wed Mar 29 07:06:37 UTC 2017
2152
2153
2154 
            boundaryCRC
2155 
            b763c113
2156
2157
2158 
            boundaryCRCversion
2159 
            1
2160
2161
2162 
            customizationCRC
2163 
            4a58e9cb
2164
2165
2166 
            customizationCRCversion
2167 
            6
2168
2169
2170
2171
2172
2173
2174 
        reset
2175
2176 
          in
2177
2178
2179 
              std_logic
2180 
              xilinx_anylanguagesynthesis
2181 
              xilinx_anylanguagebehavioralsimulation
2182
2183
2184
2185 
            0
2186
2187
2188
2189
2190 
        dclk
2191
2192 
          in
2193
2194
2195 
              std_logic
2196 
              xilinx_anylanguagesynthesis
2197 
              xilinx_anylanguagebehavioralsimulation
2198
2199
2200
2201
2202
2203 
        clk156_out
2204
2205 
          out
2206
2207
2208 
              std_logic
2209 
              xilinx_anylanguagesynthesis
2210 
              xilinx_anylanguagebehavioralsimulation
2211
2212
2213
2214
2215
2216 
        clk156_lock
2217
2218 
          out
2219
2220
2221 
              std_logic
2222 
              xilinx_anylanguagesynthesis
2223 
              xilinx_anylanguagebehavioralsimulation
2224
2225
2226
2227
2228
2229 
        refclk
2230
2231 
          in
2232
2233
2234 
              std_logic
2235 
              xilinx_anylanguagesynthesis
2236 
              xilinx_anylanguagebehavioralsimulation
2237
2238
2239
2240
2241
2242
2243 
              false
2244
2245
2246
2247
2248
2249 
        refclk_out
2250
2251 
          out
2252
2253
2254 
              std_logic
2255 
              xilinx_anylanguagesynthesis
2256 
              xilinx_anylanguagebehavioralsimulation
2257
2258
2259
2260
2261
2262
2263 
              true
2264
2265
2266
2267
2268
2269 
        refclk_p
2270
2271 
          in
2272
2273
2274 
              std_logic
2275 
              xilinx_anylanguagesynthesis
2276 
              xilinx_anylanguagebehavioralsimulation
2277
2278
2279
2280 
            0
2281
2282
2283
2284
2285
2286 
              true
2287
2288
2289
2290
2291
2292 
        refclk_n
2293
2294 
          in
2295
2296
2297 
              std_logic
2298 
              xilinx_anylanguagesynthesis
2299 
              xilinx_anylanguagebehavioralsimulation
2300
2301
2302
2303 
            0
2304
2305
2306
2307
2308
2309 
              true
2310
2311
2312
2313
2314
2315 
        qpll0outclk_out
2316
2317 
          out
2318
2319
2320 
              std_logic
2321 
              xilinx_anylanguagesynthesis
2322 
              xilinx_anylanguagebehavioralsimulation
2323
2324
2325
2326
2327
2328
2329 
              false
2330
2331
2332
2333
2334
2335 
        qpll0lock_out
2336
2337 
          out
2338
2339
2340 
              std_logic
2341 
              xilinx_anylanguagesynthesis
2342 
              xilinx_anylanguagebehavioralsimulation
2343
2344
2345
2346
2347
2348
2349 
              false
2350
2351
2352
2353
2354
2355 
        qpll0outrefclk_out
2356
2357 
          out
2358
2359
2360 
              std_logic
2361 
              xilinx_anylanguagesynthesis
2362 
              xilinx_anylanguagebehavioralsimulation
2363
2364
2365
2366
2367
2368
2369 
              false
2370
2371
2372
2373
2374
2375 
        qpll0outclk
2376
2377 
          in
2378
2379
2380 
              std_logic
2381 
              xilinx_anylanguagesynthesis
2382 
              xilinx_anylanguagebehavioralsimulation
2383
2384
2385
2386
2387
2388
2389 
              false
2390
2391
2392
2393
2394
2395 
        qpll0lock
2396
2397 
          in
2398
2399
2400 
              std_logic
2401 
              xilinx_anylanguagesynthesis
2402 
              xilinx_anylanguagebehavioralsimulation
2403
2404
2405
2406 
            0
2407
2408
2409
2410
2411
2412 
              false
2413
2414
2415
2416
2417
2418 
        qpll0outrefclk
2419
2420 
          in
2421
2422
2423 
              std_logic
2424 
              xilinx_anylanguagesynthesis
2425 
              xilinx_anylanguagebehavioralsimulation
2426
2427
2428
2429
2430
2431
2432 
              false
2433
2434
2435
2436
2437
2438 
        qpll0reset
2439
2440 
          out
2441
2442
2443 
              std_logic
2444 
              xilinx_anylanguagesynthesis
2445 
              xilinx_anylanguagebehavioralsimulation
2446
2447
2448
2449
2450
2451
2452 
              false
2453
2454
2455
2456
2457
2458 
        qplloutclk_out
2459
2460 
          out
2461
2462
2463 
              std_logic
2464 
              xilinx_anylanguagesynthesis
2465 
              xilinx_anylanguagebehavioralsimulation
2466
2467
2468
2469
2470
2471
2472 
              true
2473
2474
2475
2476
2477
2478 
        qplloutclk
2479
2480 
          in
2481
2482
2483 
              std_logic
2484 
              xilinx_anylanguagesynthesis
2485 
              xilinx_anylanguagebehavioralsimulation
2486
2487
2488
2489
2490
2491
2492 
              false
2493
2494
2495
2496
2497
2498 
        qplllock
2499
2500 
          in
2501
2502
2503 
              std_logic
2504 
              xilinx_anylanguagesynthesis
2505 
              xilinx_anylanguagebehavioralsimulation
2506
2507
2508
2509 
            0
2510
2511
2512
2513
2514
2515 
              false
2516
2517
2518
2519
2520
2521 
        qplllock_out
2522
2523 
          out
2524
2525
2526 
              std_logic
2527 
              xilinx_anylanguagesynthesis
2528 
              xilinx_anylanguagebehavioralsimulation
2529
2530
2531
2532 
            0
2533
2534
2535
2536
2537
2538 
              true
2539
2540
2541
2542
2543
2544 
        qplloutrefclk
2545
2546 
          in
2547
2548
2549 
              std_logic
2550 
              xilinx_anylanguagesynthesis
2551 
              xilinx_anylanguagebehavioralsimulation
2552
2553
2554
2555
2556
2557
2558 
              false
2559
2560
2561
2562
2563
2564 
        qplloutrefclk_out
2565
2566 
          out
2567
2568
2569 
              std_logic
2570 
              xilinx_anylanguagesynthesis
2571 
              xilinx_anylanguagebehavioralsimulation
2572
2573
2574
2575
2576
2577
2578 
              true
2579
2580
2581
2582
2583
2584 
        pll0outclk
2585
2586 
          in
2587
2588
2589 
              std_logic
2590 
              xilinx_anylanguagesynthesis
2591 
              xilinx_anylanguagebehavioralsimulation
2592
2593
2594
2595
2596
2597
2598 
              false
2599
2600
2601
2602
2603
2604 
        pll0outclk_out
2605
2606 
          out
2607
2608
2609 
              std_logic
2610 
              xilinx_anylanguagesynthesis
2611 
              xilinx_anylanguagebehavioralsimulation
2612
2613
2614
2615
2616
2617
2618 
              false
2619
2620
2621
2622
2623
2624 
        pll0lock
2625
2626 
          in
2627
2628
2629 
              std_logic
2630 
              xilinx_anylanguagesynthesis
2631 
              xilinx_anylanguagebehavioralsimulation
2632
2633
2634
2635 
            0
2636
2637
2638
2639
2640
2641 
              false
2642
2643
2644
2645
2646
2647 
        pll0lock_out
2648
2649 
          out
2650
2651
2652 
              std_logic
2653 
              xilinx_anylanguagesynthesis
2654 
              xilinx_anylanguagebehavioralsimulation
2655
2656
2657
2658
2659
2660
2661 
              false
2662
2663
2664
2665
2666
2667 
        pll0outrefclk
2668
2669 
          in
2670
2671
2672 
              std_logic
2673 
              xilinx_anylanguagesynthesis
2674 
              xilinx_anylanguagebehavioralsimulation
2675
2676
2677
2678
2679
2680
2681 
              false
2682
2683
2684
2685
2686
2687 
        pll0outrefclk_out
2688
2689 
          out
2690
2691
2692 
              std_logic
2693 
              xilinx_anylanguagesynthesis
2694 
              xilinx_anylanguagebehavioralsimulation
2695
2696
2697
2698
2699
2700
2701 
              false
2702
2703
2704
2705
2706
2707 
        pll1outclk
2708
2709 
          in
2710
2711
2712 
              std_logic
2713 
              xilinx_anylanguagesynthesis
2714 
              xilinx_anylanguagebehavioralsimulation
2715
2716
2717
2718
2719
2720
2721 
              false
2722
2723
2724
2725
2726
2727 
        pll1outclk_out
2728
2729 
          out
2730
2731
2732 
              std_logic
2733 
              xilinx_anylanguagesynthesis
2734 
              xilinx_anylanguagebehavioralsimulation
2735
2736
2737
2738
2739
2740
2741 
              false
2742
2743
2744
2745
2746
2747 
        pll1outrefclk
2748
2749 
          in
2750
2751
2752 
              std_logic
2753 
              xilinx_anylanguagesynthesis
2754 
              xilinx_anylanguagebehavioralsimulation
2755
2756
2757
2758
2759
2760
2761 
              false
2762
2763
2764
2765
2766
2767 
        pll1outrefclk_out
2768
2769 
          out
2770
2771
2772 
              std_logic
2773 
              xilinx_anylanguagesynthesis
2774 
              xilinx_anylanguagebehavioralsimulation
2775
2776
2777
2778
2779
2780
2781 
              false
2782
2783
2784
2785
2786
2787 
        common_pll_reset
2788
2789 
          in
2790
2791
2792 
              std_logic
2793 
              xilinx_anylanguagesynthesis
2794 
              xilinx_anylanguagebehavioralsimulation
2795
2796
2797
2798 
            0
2799
2800
2801
2802
2803
2804 
              false
2805
2806
2807
2808
2809
2810 
        common_pll_reset_out
2811
2812 
          out
2813
2814
2815 
              std_logic
2816 
              xilinx_anylanguagesynthesis
2817 
              xilinx_anylanguagebehavioralsimulation
2818
2819
2820
2821
2822
2823
2824 
              false
2825
2826
2827
2828
2829
2830 
        xgmii_txd
2831
2832 
          in
2833
2834 
            63
2835 
            0
2836
2837
2838
2839 
              std_logic_vector
2840 
              xilinx_anylanguagesynthesis
2841 
              xilinx_anylanguagebehavioralsimulation
2842
2843
2844
2845
2846
2847 
        xgmii_txc
2848
2849 
          in
2850
2851 
            7
2852 
            0
2853
2854
2855
2856 
              std_logic_vector
2857 
              xilinx_anylanguagesynthesis
2858 
              xilinx_anylanguagebehavioralsimulation
2859
2860
2861
2862
2863
2864 
        xgmii_rxd
2865
2866 
          out
2867
2868 
            63
2869 
            0
2870
2871
2872
2873 
              std_logic_vector
2874 
              xilinx_anylanguagesynthesis
2875 
              xilinx_anylanguagebehavioralsimulation
2876
2877
2878
2879
2880
2881 
        xgmii_rxc
2882
2883 
          out
2884
2885 
            7
2886 
            0
2887
2888
2889
2890 
              std_logic_vector
2891 
              xilinx_anylanguagesynthesis
2892 
              xilinx_anylanguagebehavioralsimulation
2893
2894
2895
2896
2897
2898 
        rxaui_tx_l0_p
2899
2900 
          out
2901
2902
2903 
              std_logic
2904 
              xilinx_anylanguagesynthesis
2905 
              xilinx_anylanguagebehavioralsimulation
2906
2907
2908
2909
2910
2911 
        rxaui_tx_l0_n
2912
2913 
          out
2914
2915
2916 
              std_logic
2917 
              xilinx_anylanguagesynthesis
2918 
              xilinx_anylanguagebehavioralsimulation
2919
2920
2921
2922
2923
2924 
        rxaui_tx_l1_p
2925
2926 
          out
2927
2928
2929 
              std_logic
2930 
              xilinx_anylanguagesynthesis
2931 
              xilinx_anylanguagebehavioralsimulation
2932
2933
2934
2935
2936
2937 
        rxaui_tx_l1_n
2938
2939 
          out
2940
2941
2942 
              std_logic
2943 
              xilinx_anylanguagesynthesis
2944 
              xilinx_anylanguagebehavioralsimulation
2945
2946
2947
2948
2949
2950 
        rxaui_rx_l0_p
2951
2952 
          in
2953
2954
2955 
              std_logic
2956 
              xilinx_anylanguagesynthesis
2957 
              xilinx_anylanguagebehavioralsimulation
2958
2959
2960
2961
2962
2963 
        rxaui_rx_l0_n
2964
2965 
          in
2966
2967
2968 
              std_logic
2969 
              xilinx_anylanguagesynthesis
2970 
              xilinx_anylanguagebehavioralsimulation
2971
2972
2973
2974
2975
2976 
        rxaui_rx_l1_p
2977
2978 
          in
2979
2980
2981 
              std_logic
2982 
              xilinx_anylanguagesynthesis
2983 
              xilinx_anylanguagebehavioralsimulation
2984
2985
2986
2987
2988
2989 
        rxaui_rx_l1_n
2990
2991 
          in
2992
2993
2994 
              std_logic
2995 
              xilinx_anylanguagesynthesis
2996 
              xilinx_anylanguagebehavioralsimulation
2997
2998
2999
3000
3001
3002 
        signal_detect
3003
3004 
          in
3005
3006 
            1
3007 
            0
3008
3009
3010
3011 
              std_logic_vector
3012 
              xilinx_anylanguagesynthesis
3013 
              xilinx_anylanguagebehavioralsimulation
3014
3015
3016
3017 
            1
3018
3019
3020
3021
3022 
        debug
3023
3024 
          out
3025
3026 
            5
3027 
            0
3028
3029
3030
3031 
              std_logic_vector
3032 
              xilinx_anylanguagesynthesis
3033 
              xilinx_anylanguagebehavioralsimulation
3034
3035
3036
3037
3038
3039 
        gt_qplllock_out
3040
3041 
          out
3042
3043
3044 
              std_logic
3045 
              xilinx_anylanguagesynthesis
3046 
              xilinx_anylanguagebehavioralsimulation
3047
3048
3049
3050
3051
3052
3053 
              false
3054
3055
3056
3057
3058
3059 
        gt0_txpmareset_in
3060
3061 
          in
3062
3063
3064 
              std_logic
3065 
              xilinx_anylanguagesynthesis
3066 
              xilinx_anylanguagebehavioralsimulation
3067
3068
3069
3070 
            0
3071
3072
3073
3074
3075
3076 
              false
3077
3078
3079
3080
3081
3082 
        gt0_txpcsreset_in
3083
3084 
          in
3085
3086
3087 
              std_logic
3088 
              xilinx_anylanguagesynthesis
3089 
              xilinx_anylanguagebehavioralsimulation
3090
3091
3092
3093 
            0
3094
3095
3096
3097
3098
3099 
              false
3100
3101
3102
3103
3104
3105 
        gt0_txresetdone_out
3106
3107 
          out
3108
3109
3110 
              std_logic
3111 
              xilinx_anylanguagesynthesis
3112 
              xilinx_anylanguagebehavioralsimulation
3113
3114
3115
3116
3117
3118
3119 
              false
3120
3121
3122
3123
3124
3125 
        gt0_rxpmareset_in
3126
3127 
          in
3128
3129
3130 
              std_logic
3131 
              xilinx_anylanguagesynthesis
3132 
              xilinx_anylanguagebehavioralsimulation
3133
3134
3135
3136 
            0
3137
3138
3139
3140
3141
3142 
              false
3143
3144
3145
3146
3147
3148 
        gt0_rxpcsreset_in
3149
3150 
          in
3151
3152
3153 
              std_logic
3154 
              xilinx_anylanguagesynthesis
3155 
              xilinx_anylanguagebehavioralsimulation
3156
3157
3158
3159 
            0
3160
3161
3162
3163
3164
3165 
              false
3166
3167
3168
3169
3170
3171 
        gt0_rxpmaresetdone_out
3172
3173 
          out
3174
3175
3176 
              std_logic
3177 
              xilinx_anylanguagesynthesis
3178 
              xilinx_anylanguagebehavioralsimulation
3179
3180
3181
3182
3183
3184
3185 
              false
3186
3187
3188
3189
3190
3191 
        gt0_rxresetdone_out
3192
3193 
          out
3194
3195
3196 
              std_logic
3197 
              xilinx_anylanguagesynthesis
3198 
              xilinx_anylanguagebehavioralsimulation
3199
3200
3201
3202
3203
3204
3205 
              false
3206
3207
3208
3209
3210
3211 
        gt0_rxbufstatus_out
3212
3213 
          out
3214
3215 
            2
3216 
            0
3217
3218
3219
3220 
              std_logic_vector
3221 
              xilinx_anylanguagesynthesis
3222 
              xilinx_anylanguagebehavioralsimulation
3223
3224
3225
3226
3227
3228
3229 
              false
3230
3231
3232
3233
3234
3235 
        gt0_txphaligndone_out
3236
3237 
          out
3238
3239
3240 
              std_logic
3241 
              xilinx_anylanguagesynthesis
3242 
              xilinx_anylanguagebehavioralsimulation
3243
3244
3245
3246
3247
3248
3249 
              false
3250
3251
3252
3253
3254
3255 
        gt0_txphinitdone_out
3256
3257 
          out
3258
3259
3260 
              std_logic
3261 
              xilinx_anylanguagesynthesis
3262 
              xilinx_anylanguagebehavioralsimulation
3263
3264
3265
3266
3267
3268
3269 
              false
3270
3271
3272
3273
3274
3275 
        gt0_txdlysresetdone_out
3276
3277 
          out
3278
3279
3280 
              std_logic
3281 
              xilinx_anylanguagesynthesis
3282 
              xilinx_anylanguagebehavioralsimulation
3283
3284
3285
3286
3287
3288
3289 
              false
3290
3291
3292
3293
3294
3295 
        gt0_cplllock_out
3296
3297 
          out
3298
3299
3300 
              std_logic
3301 
              xilinx_anylanguagesynthesis
3302 
              xilinx_anylanguagebehavioralsimulation
3303
3304
3305
3306
3307
3308
3309 
              false
3310
3311
3312
3313
3314
3315 
        gt0_eyescantrigger_in
3316
3317 
          in
3318
3319
3320 
              std_logic
3321 
              xilinx_anylanguagesynthesis
3322 
              xilinx_anylanguagebehavioralsimulation
3323
3324
3325
3326 
            0
3327
3328
3329
3330
3331
3332 
              false
3333
3334
3335
3336
3337
3338 
        gt0_eyescanreset_in
3339
3340 
          in
3341
3342
3343 
              std_logic
3344 
              xilinx_anylanguagesynthesis
3345 
              xilinx_anylanguagebehavioralsimulation
3346
3347
3348
3349 
            0
3350
3351
3352
3353
3354
3355 
              false
3356
3357
3358
3359
3360
3361 
        gt0_eyescandataerror_out
3362
3363 
          out
3364
3365
3366 
              std_logic
3367 
              xilinx_anylanguagesynthesis
3368 
              xilinx_anylanguagebehavioralsimulation
3369
3370
3371
3372
3373
3374
3375 
              false
3376
3377
3378
3379
3380
3381 
        gt0_rxrate_in
3382
3383 
          in
3384
3385 
            2
3386 
            0
3387
3388
3389
3390 
              std_logic_vector
3391 
              xilinx_anylanguagesynthesis
3392 
              xilinx_anylanguagebehavioralsimulation
3393
3394
3395
3396 
            0
3397
3398
3399
3400
3401
3402 
              false
3403
3404
3405
3406
3407
3408 
        gt0_loopback_in
3409
3410 
          in
3411
3412 
            2
3413 
            0
3414
3415
3416
3417 
              std_logic_vector
3418 
              xilinx_anylanguagesynthesis
3419 
              xilinx_anylanguagebehavioralsimulation
3420
3421
3422
3423 
            0
3424
3425
3426
3427
3428
3429 
              false
3430
3431
3432
3433
3434
3435 
        gt0_rxpolarity_in
3436
3437 
          in
3438
3439
3440 
              std_logic
3441 
              xilinx_anylanguagesynthesis
3442 
              xilinx_anylanguagebehavioralsimulation
3443
3444
3445
3446 
            0
3447
3448
3449
3450
3451
3452 
              false
3453
3454
3455
3456
3457
3458 
        gt0_txpolarity_in
3459
3460 
          in
3461
3462
3463 
              std_logic
3464 
              xilinx_anylanguagesynthesis
3465 
              xilinx_anylanguagebehavioralsimulation
3466
3467
3468
3469 
            0
3470
3471
3472
3473
3474
3475 
              false
3476
3477
3478
3479
3480
3481 
        gt0_rxlpmen_in
3482
3483 
          in
3484
3485
3486 
              std_logic
3487 
              xilinx_anylanguagesynthesis
3488 
              xilinx_anylanguagebehavioralsimulation
3489
3490
3491
3492 
            0
3493
3494
3495
3496
3497
3498 
              false
3499
3500
3501
3502
3503
3504 
        gt0_rxdfelpmreset_in
3505
3506 
          in
3507
3508
3509 
              std_logic
3510 
              xilinx_anylanguagesynthesis
3511 
              xilinx_anylanguagebehavioralsimulation
3512
3513
3514
3515 
            0
3516
3517
3518
3519
3520
3521 
              false
3522
3523
3524
3525
3526
3527 
        gt0_rxmonitorsel_in
3528
3529 
          in
3530
3531 
            1
3532 
            0
3533
3534
3535
3536 
              std_logic_vector
3537 
              xilinx_anylanguagesynthesis
3538 
              xilinx_anylanguagebehavioralsimulation
3539
3540
3541
3542 
            0
3543
3544
3545
3546
3547
3548 
              false
3549
3550
3551
3552
3553
3554 
        gt0_rxmonitorout_out
3555
3556 
          out
3557
3558 
            6
3559 
            0
3560
3561
3562
3563 
              std_logic_vector
3564 
              xilinx_anylanguagesynthesis
3565 
              xilinx_anylanguagebehavioralsimulation
3566
3567
3568
3569
3570
3571
3572 
              false
3573
3574
3575
3576
3577
3578 
        gt0_rxlpmreset_in
3579
3580 
          in
3581
3582
3583 
              std_logic
3584 
              xilinx_anylanguagesynthesis
3585 
              xilinx_anylanguagebehavioralsimulation
3586
3587
3588
3589 
            0
3590
3591
3592
3593
3594
3595 
              false
3596
3597
3598
3599
3600
3601 
        gt0_rxlpmhfhold_in
3602
3603 
          in
3604
3605
3606 
              std_logic
3607 
              xilinx_anylanguagesynthesis
3608 
              xilinx_anylanguagebehavioralsimulation
3609
3610
3611
3612 
            0
3613
3614
3615
3616
3617
3618 
              false
3619
3620
3621
3622
3623
3624 
        gt0_rxlpmhfovrden_in
3625
3626 
          in
3627
3628
3629 
              std_logic
3630 
              xilinx_anylanguagesynthesis
3631 
              xilinx_anylanguagebehavioralsimulation
3632
3633
3634
3635 
            0
3636
3637
3638
3639
3640
3641 
              false
3642
3643
3644
3645
3646
3647 
        gt0_rxlpmlfhold_in
3648
3649 
          in
3650
3651
3652 
              std_logic
3653 
              xilinx_anylanguagesynthesis
3654 
              xilinx_anylanguagebehavioralsimulation
3655
3656
3657
3658 
            0
3659
3660
3661
3662
3663
3664 
              false
3665
3666
3667
3668
3669
3670 
        gt0_rxlpmlfovrden_in
3671
3672 
          in
3673
3674
3675 
              std_logic
3676 
              xilinx_anylanguagesynthesis
3677 
              xilinx_anylanguagebehavioralsimulation
3678
3679
3680
3681 
            0
3682
3683
3684
3685
3686
3687 
              false
3688
3689
3690
3691
3692
3693 
        gt0_txpostcursor_in
3694
3695 
          in
3696
3697 
            4
3698 
            0
3699
3700
3701
3702 
              std_logic_vector
3703 
              xilinx_anylanguagesynthesis
3704 
              xilinx_anylanguagebehavioralsimulation
3705
3706
3707
3708 
            0
3709
3710
3711
3712
3713
3714 
              false
3715
3716
3717
3718
3719
3720 
        gt0_txprecursor_in
3721
3722 
          in
3723
3724 
            4
3725 
            0
3726
3727
3728
3729 
              std_logic_vector
3730 
              xilinx_anylanguagesynthesis
3731 
              xilinx_anylanguagebehavioralsimulation
3732
3733
3734
3735 
            0
3736
3737
3738
3739
3740
3741 
              false
3742
3743
3744
3745
3746
3747 
        gt0_txdiffctrl_in
3748
3749 
          in
3750
3751 
            3
3752 
            0
3753
3754
3755
3756 
              std_logic_vector
3757 
              xilinx_anylanguagesynthesis
3758 
              xilinx_anylanguagebehavioralsimulation
3759
3760
3761
3762 
            0
3763
3764
3765
3766
3767
3768 
              false
3769
3770
3771
3772
3773
3774 
        gt0_rxprbscntreset_in
3775
3776 
          in
3777
3778
3779 
              std_logic
3780 
              xilinx_anylanguagesynthesis
3781 
              xilinx_anylanguagebehavioralsimulation
3782
3783
3784
3785 
            0
3786
3787
3788
3789
3790
3791 
              false
3792
3793
3794
3795
3796
3797 
        gt0_rxprbserr_out
3798
3799 
          out
3800
3801
3802 
              std_logic
3803 
              xilinx_anylanguagesynthesis
3804 
              xilinx_anylanguagebehavioralsimulation
3805
3806
3807
3808
3809
3810
3811 
              false
3812
3813
3814
3815
3816
3817 
        gt0_rxprbssel_in
3818
3819 
          in
3820
3821 
            2
3822 
            0
3823
3824
3825
3826 
              std_logic_vector
3827 
              xilinx_anylanguagesynthesis
3828 
              xilinx_anylanguagebehavioralsimulation
3829
3830
3831
3832 
            0
3833
3834
3835
3836
3837
3838 
              false
3839
3840
3841
3842
3843
3844 
        gt0_txprbssel_in
3845
3846 
          in
3847
3848 
            2
3849 
            0
3850
3851
3852
3853 
              std_logic_vector
3854 
              xilinx_anylanguagesynthesis
3855 
              xilinx_anylanguagebehavioralsimulation
3856
3857
3858
3859 
            0
3860
3861
3862
3863
3864
3865 
              false
3866
3867
3868
3869
3870
3871 
        gt0_txprbsforceerr_in
3872
3873 
          in
3874
3875
3876 
              std_logic
3877 
              xilinx_anylanguagesynthesis
3878 
              xilinx_anylanguagebehavioralsimulation
3879
3880
3881
3882 
            0
3883
3884
3885
3886
3887
3888 
              false
3889
3890
3891
3892
3893
3894 
        gt0_rxcdrhold_in
3895
3896 
          in
3897
3898
3899 
              std_logic
3900 
              xilinx_anylanguagesynthesis
3901 
              xilinx_anylanguagebehavioralsimulation
3902
3903
3904
3905 
            0
3906
3907
3908
3909
3910
3911 
              false
3912
3913
3914
3915
3916
3917 
        gt0_dmonitorout_out
3918
3919 
          out
3920
3921 
            7
3922 
            0
3923
3924
3925
3926 
              std_logic
3927 
              xilinx_anylanguagesynthesis
3928 
              xilinx_anylanguagebehavioralsimulation
3929
3930
3931
3932 
            0
3933
3934
3935
3936
3937
3938 
              false
3939
3940
3941
3942
3943
3944 
        gt0_txinhibit_in
3945
3946 
          in
3947
3948
3949 
              std_logic
3950 
              xilinx_anylanguagesynthesis
3951 
              xilinx_anylanguagebehavioralsimulation
3952
3953
3954
3955 
            0
3956
3957
3958
3959
3960
3961 
              false
3962
3963
3964
3965
3966
3967 
        gt0_rxdisperr_out
3968
3969 
          out
3970
3971 
            3
3972 
            0
3973
3974
3975
3976 
              std_logic_vector
3977 
              xilinx_anylanguagesynthesis
3978 
              xilinx_anylanguagebehavioralsimulation
3979
3980
3981
3982
3983
3984
3985 
              false
3986
3987
3988
3989
3990
3991 
        gt0_rxnotintable_out
3992
3993 
          out
3994
3995 
            3
3996 
            0
3997
3998
3999
4000 
              std_logic_vector
4001 
              xilinx_anylanguagesynthesis
4002 
              xilinx_anylanguagebehavioralsimulation
4003
4004
4005
4006
4007
4008
4009 
              false
4010
4011
4012
4013
4014
4015 
        gt0_rxcommadet_out
4016
4017 
          out
4018
4019
4020 
              std_logic
4021 
              xilinx_anylanguagesynthesis
4022 
              xilinx_anylanguagebehavioralsimulation
4023
4024
4025
4026
4027
4028
4029 
              false
4030
4031
4032
4033
4034
4035 
        gt1_txpmareset_in
4036
4037 
          in
4038
4039
4040 
              std_logic
4041 
              xilinx_anylanguagesynthesis
4042 
              xilinx_anylanguagebehavioralsimulation
4043
4044
4045
4046 
            0
4047
4048
4049
4050
4051
4052 
              false
4053
4054
4055
4056
4057
4058 
        gt1_txpcsreset_in
4059
4060 
          in
4061
4062
4063 
              std_logic
4064 
              xilinx_anylanguagesynthesis
4065 
              xilinx_anylanguagebehavioralsimulation
4066
4067
4068
4069 
            0
4070
4071
4072
4073
4074
4075 
              false
4076
4077
4078
4079
4080
4081 
        gt1_txresetdone_out
4082
4083 
          out
4084
4085
4086 
              std_logic
4087 
              xilinx_anylanguagesynthesis
4088 
              xilinx_anylanguagebehavioralsimulation
4089
4090
4091
4092
4093
4094
4095 
              false
4096
4097
4098
4099
4100
4101 
        gt1_rxpmareset_in
4102
4103 
          in
4104
4105
4106 
              std_logic
4107 
              xilinx_anylanguagesynthesis
4108 
              xilinx_anylanguagebehavioralsimulation
4109
4110
4111
4112 
            0
4113
4114
4115
4116
4117
4118 
              false
4119
4120
4121
4122
4123
4124 
        gt1_rxpcsreset_in
4125
4126 
          in
4127
4128
4129 
              std_logic
4130 
              xilinx_anylanguagesynthesis
4131 
              xilinx_anylanguagebehavioralsimulation
4132
4133
4134
4135 
            0
4136
4137
4138
4139
4140
4141 
              false
4142
4143
4144
4145
4146
4147 
        gt1_rxpmaresetdone_out
4148
4149 
          out
4150
4151
4152 
              std_logic
4153 
              xilinx_anylanguagesynthesis
4154 
              xilinx_anylanguagebehavioralsimulation
4155
4156
4157
4158
4159
4160
4161 
              false
4162
4163
4164
4165
4166
4167 
        gt1_rxresetdone_out
4168
4169 
          out
4170
4171
4172 
              std_logic
4173 
              xilinx_anylanguagesynthesis
4174 
              xilinx_anylanguagebehavioralsimulation
4175
4176
4177
4178
4179
4180
4181 
              false
4182
4183
4184
4185
4186
4187 
        gt1_rxbufstatus_out
4188
4189 
          out
4190
4191 
            2
4192 
            0
4193
4194
4195
4196 
              std_logic_vector
4197 
              xilinx_anylanguagesynthesis
4198 
              xilinx_anylanguagebehavioralsimulation
4199
4200
4201
4202
4203
4204
4205 
              false
4206
4207
4208
4209
4210
4211 
        gt1_txphaligndone_out
4212
4213 
          out
4214
4215
4216 
              std_logic
4217 
              xilinx_anylanguagesynthesis
4218 
              xilinx_anylanguagebehavioralsimulation
4219
4220
4221
4222
4223
4224
4225 
              false
4226
4227
4228
4229
4230
4231 
        gt1_txphinitdone_out
4232
4233 
          out
4234
4235
4236 
              std_logic
4237 
              xilinx_anylanguagesynthesis
4238 
              xilinx_anylanguagebehavioralsimulation
4239
4240
4241
4242
4243
4244
4245 
              false
4246
4247
4248
4249
4250
4251 
        gt1_txdlysresetdone_out
4252
4253 
          out
4254
4255
4256 
              std_logic
4257 
              xilinx_anylanguagesynthesis
4258 
              xilinx_anylanguagebehavioralsimulation
4259
4260
4261
4262
4263
4264
4265 
              false
4266
4267
4268
4269
4270
4271 
        gt1_cplllock_out
4272
4273 
          out
4274
4275
4276 
              std_logic
4277 
              xilinx_anylanguagesynthesis
4278 
              xilinx_anylanguagebehavioralsimulation
4279
4280
4281
4282
4283
4284
4285 
              false
4286
4287
4288
4289
4290
4291 
        gt1_eyescantrigger_in
4292
4293 
          in
4294
4295
4296 
              std_logic
4297 
              xilinx_anylanguagesynthesis
4298 
              xilinx_anylanguagebehavioralsimulation
4299
4300
4301
4302 
            0
4303
4304
4305
4306
4307
4308 
              false
4309
4310
4311
4312
4313
4314 
        gt1_eyescanreset_in
4315
4316 
          in
4317
4318
4319 
              std_logic
4320 
              xilinx_anylanguagesynthesis
4321 
              xilinx_anylanguagebehavioralsimulation
4322
4323
4324
4325 
            0
4326
4327
4328
4329
4330
4331 
              false
4332
4333
4334
4335
4336
4337 
        gt1_eyescandataerror_out
4338
4339 
          out
4340
4341
4342 
              std_logic
4343 
              xilinx_anylanguagesynthesis
4344 
              xilinx_anylanguagebehavioralsimulation
4345
4346
4347
4348
4349
4350
4351 
              false
4352
4353
4354
4355
4356
4357 
        gt1_rxrate_in
4358
4359 
          in
4360
4361 
            2
4362 
            0
4363
4364
4365
4366 
              std_logic_vector
4367 
              xilinx_anylanguagesynthesis
4368 
              xilinx_anylanguagebehavioralsimulation
4369
4370
4371
4372 
            0
4373
4374
4375
4376
4377
4378 
              false
4379
4380
4381
4382
4383
4384 
        gt1_loopback_in
4385
4386 
          in
4387
4388 
            2
4389 
            0
4390
4391
4392
4393 
              std_logic_vector
4394 
              xilinx_anylanguagesynthesis
4395 
              xilinx_anylanguagebehavioralsimulation
4396
4397
4398
4399 
            0
4400
4401
4402
4403
4404
4405 
              false
4406
4407
4408
4409
4410
4411 
        gt1_rxpolarity_in
4412
4413 
          in
4414
4415
4416 
              std_logic
4417 
              xilinx_anylanguagesynthesis
4418 
              xilinx_anylanguagebehavioralsimulation
4419
4420
4421
4422 
            0
4423
4424
4425
4426
4427
4428 
              false
4429
4430
4431
4432
4433
4434 
        gt1_txpolarity_in
4435
4436 
          in
4437
4438
4439 
              std_logic
4440 
              xilinx_anylanguagesynthesis
4441 
              xilinx_anylanguagebehavioralsimulation
4442
4443
4444
4445 
            0
4446
4447
4448
4449
4450
4451 
              false
4452
4453
4454
4455
4456
4457 
        gt1_rxlpmen_in
4458
4459 
          in
4460
4461
4462 
              std_logic
4463 
              xilinx_anylanguagesynthesis
4464 
              xilinx_anylanguagebehavioralsimulation
4465
4466
4467
4468 
            0
4469
4470
4471
4472
4473
4474 
              false
4475
4476
4477
4478
4479
4480 
        gt1_rxdfelpmreset_in
4481
4482 
          in
4483
4484
4485 
              std_logic
4486 
              xilinx_anylanguagesynthesis
4487 
              xilinx_anylanguagebehavioralsimulation
4488
4489
4490
4491 
            0
4492
4493
4494
4495
4496
4497 
              false
4498
4499
4500
4501
4502
4503 
        gt1_rxmonitorsel_in
4504
4505 
          in
4506
4507 
            1
4508 
            0
4509
4510
4511
4512 
              std_logic_vector
4513 
              xilinx_anylanguagesynthesis
4514 
              xilinx_anylanguagebehavioralsimulation
4515
4516
4517
4518 
            0
4519
4520
4521
4522
4523
4524 
              false
4525
4526
4527
4528
4529
4530 
        gt1_rxmonitorout_out
4531
4532 
          out
4533
4534 
            6
4535 
            0
4536
4537
4538
4539 
              std_logic_vector
4540 
              xilinx_anylanguagesynthesis
4541 
              xilinx_anylanguagebehavioralsimulation
4542
4543
4544
4545
4546
4547
4548 
              false
4549
4550
4551
4552
4553
4554 
        gt1_rxlpmreset_in
4555
4556 
          in
4557
4558
4559 
              std_logic
4560 
              xilinx_anylanguagesynthesis
4561 
              xilinx_anylanguagebehavioralsimulation
4562
4563
4564
4565 
            0
4566
4567
4568
4569
4570
4571 
              false
4572
4573
4574
4575
4576
4577 
        gt1_rxlpmhfhold_in
4578
4579 
          in
4580
4581
4582 
              std_logic
4583 
              xilinx_anylanguagesynthesis
4584 
              xilinx_anylanguagebehavioralsimulation
4585
4586
4587
4588 
            0
4589
4590
4591
4592
4593
4594 
              false
4595
4596
4597
4598
4599
4600 
        gt1_rxlpmhfovrden_in
4601
4602 
          in
4603
4604
4605 
              std_logic
4606 
              xilinx_anylanguagesynthesis
4607 
              xilinx_anylanguagebehavioralsimulation
4608
4609
4610
4611 
            0
4612
4613
4614
4615
4616
4617 
              false
4618
4619
4620
4621
4622
4623 
        gt1_rxlpmlfhold_in
4624
4625 
          in
4626
4627
4628 
              std_logic
4629 
              xilinx_anylanguagesynthesis
4630 
              xilinx_anylanguagebehavioralsimulation
4631
4632
4633
4634 
            0
4635
4636
4637
4638
4639
4640 
              false
4641
4642
4643
4644
4645
4646 
        gt1_rxlpmlfovrden_in
4647
4648 
          in
4649
4650
4651 
              std_logic
4652 
              xilinx_anylanguagesynthesis
4653 
              xilinx_anylanguagebehavioralsimulation
4654
4655
4656
4657 
            0
4658
4659
4660
4661
4662
4663 
              false
4664
4665
4666
4667
4668
4669 
        gt1_txpostcursor_in
4670
4671 
          in
4672
4673 
            4
4674 
            0
4675
4676
4677
4678 
              std_logic_vector
4679 
              xilinx_anylanguagesynthesis
4680 
              xilinx_anylanguagebehavioralsimulation
4681
4682
4683
4684 
            0
4685
4686
4687
4688
4689
4690 
              false
4691
4692
4693
4694
4695
4696 
        gt1_txprecursor_in
4697
4698 
          in
4699
4700 
            4
4701 
            0
4702
4703
4704
4705 
              std_logic_vector
4706 
              xilinx_anylanguagesynthesis
4707 
              xilinx_anylanguagebehavioralsimulation
4708
4709
4710
4711 
            0
4712
4713
4714
4715
4716
4717 
              false
4718
4719
4720
4721
4722
4723 
        gt1_txdiffctrl_in
4724
4725 
          in
4726
4727 
            3
4728 
            0
4729
4730
4731
4732 
              std_logic_vector
4733 
              xilinx_anylanguagesynthesis
4734 
              xilinx_anylanguagebehavioralsimulation
4735
4736
4737
4738 
            0
4739
4740
4741
4742
4743
4744 
              false
4745
4746
4747
4748
4749
4750 
        gt1_rxprbscntreset_in
4751
4752 
          in
4753
4754
4755 
              std_logic
4756 
              xilinx_anylanguagesynthesis
4757 
              xilinx_anylanguagebehavioralsimulation
4758
4759
4760
4761 
            0
4762
4763
4764
4765
4766
4767 
              false
4768
4769
4770
4771
4772
4773 
        gt1_rxprbserr_out
4774
4775 
          out
4776
4777
4778 
              std_logic
4779 
              xilinx_anylanguagesynthesis
4780 
              xilinx_anylanguagebehavioralsimulation
4781
4782
4783
4784
4785
4786
4787 
              false
4788
4789
4790
4791
4792
4793 
        gt1_rxprbssel_in
4794
4795 
          in
4796
4797 
            2
4798 
            0
4799
4800
4801
4802 
              std_logic_vector
4803 
              xilinx_anylanguagesynthesis
4804 
              xilinx_anylanguagebehavioralsimulation
4805
4806
4807
4808 
            0
4809
4810
4811
4812
4813
4814 
              false
4815
4816
4817
4818
4819
4820 
        gt1_txprbssel_in
4821
4822 
          in
4823
4824 
            2
4825 
            0
4826
4827
4828
4829 
              std_logic_vector
4830 
              xilinx_anylanguagesynthesis
4831 
              xilinx_anylanguagebehavioralsimulation
4832
4833
4834
4835 
            0
4836
4837
4838
4839
4840
4841 
              false
4842
4843
4844
4845
4846
4847 
        gt1_txprbsforceerr_in
4848
4849 
          in
4850
4851
4852 
              std_logic
4853 
              xilinx_anylanguagesynthesis
4854 
              xilinx_anylanguagebehavioralsimulation
4855
4856
4857
4858 
            0
4859
4860
4861
4862
4863
4864 
              false
4865
4866
4867
4868
4869
4870 
        gt1_rxcdrhold_in
4871
4872 
          in
4873
4874
4875 
              std_logic
4876 
              xilinx_anylanguagesynthesis
4877 
              xilinx_anylanguagebehavioralsimulation
4878
4879
4880
4881 
            0
4882
4883
4884
4885
4886
4887 
              false
4888
4889
4890
4891
4892
4893 
        gt1_dmonitorout_out
4894
4895 
          out
4896
4897 
            7
4898 
            0
4899
4900
4901
4902 
              std_logic_vector
4903 
              xilinx_anylanguagesynthesis
4904 
              xilinx_anylanguagebehavioralsimulation
4905
4906
4907
4908 
            0
4909
4910
4911
4912
4913
4914 
              false
4915
4916
4917
4918
4919
4920 
        gt1_txinhibit_in
4921
4922 
          in
4923
4924
4925 
              std_logic
4926 
              xilinx_anylanguagesynthesis
4927 
              xilinx_anylanguagebehavioralsimulation
4928
4929
4930
4931 
            0
4932
4933
4934
4935
4936
4937 
              false
4938
4939
4940
4941
4942
4943 
        gt1_rxdisperr_out
4944
4945 
          out
4946
4947 
            3
4948 
            0
4949
4950
4951
4952 
              std_logic_vector
4953 
              xilinx_anylanguagesynthesis
4954 
              xilinx_anylanguagebehavioralsimulation
4955
4956
4957
4958
4959
4960
4961 
              false
4962
4963
4964
4965
4966
4967 
        gt1_rxnotintable_out
4968
4969 
          out
4970
4971 
            3
4972 
            0
4973
4974
4975
4976 
              std_logic_vector
4977 
              xilinx_anylanguagesynthesis
4978 
              xilinx_anylanguagebehavioralsimulation
4979
4980
4981
4982
4983
4984
4985 
              false
4986
4987
4988
4989
4990
4991 
        gt1_rxcommadet_out
4992
4993 
          out
4994
4995
4996 
              std_logic
4997 
              xilinx_anylanguagesynthesis
4998 
              xilinx_anylanguagebehavioralsimulation
4999
5000
5001
5002
5003
5004
5005 
              false
5006
5007
5008
5009
5010
5011 
        gt_txpmareset
5012
5013 
          in
5014
5015 
            1
5016 
            0
5017
5018
5019
5020 
              std_logic_vector
5021 
              xilinx_anylanguagesynthesis
5022 
              xilinx_anylanguagebehavioralsimulation
5023
5024
5025
5026 
            0
5027
5028
5029
5030
5031
5032 
              false
5033
5034
5035
5036
5037
5038 
        gt_txpcsreset
5039
5040 
          in
5041
5042 
            1
5043 
            0
5044
5045
5046
5047 
              std_logic_vector
5048 
              xilinx_anylanguagesynthesis
5049 
              xilinx_anylanguagebehavioralsimulation
5050
5051
5052
5053 
            0
5054
5055
5056
5057
5058
5059 
              false
5060
5061
5062
5063
5064
5065 
        gt_txresetdone
5066
5067 
          out
5068
5069 
            1
5070 
            0
5071
5072
5073
5074 
              std_logic_vector
5075 
              xilinx_anylanguagesynthesis
5076 
              xilinx_anylanguagebehavioralsimulation
5077
5078
5079
5080
5081
5082
5083 
              false
5084
5085
5086
5087
5088
5089 
        gt_rxpmareset
5090
5091 
          in
5092
5093 
            1
5094 
            0
5095
5096
5097
5098 
              std_logic_vector
5099 
              xilinx_anylanguagesynthesis
5100 
              xilinx_anylanguagebehavioralsimulation
5101
5102
5103
5104 
            0
5105
5106
5107
5108
5109
5110 
              false
5111
5112
5113
5114
5115
5116 
        gt_rxpcsreset
5117
5118 
          in
5119
5120 
            1
5121 
            0
5122
5123
5124
5125 
              std_logic_vector
5126 
              xilinx_anylanguagesynthesis
5127 
              xilinx_anylanguagebehavioralsimulation
5128
5129
5130
5131 
            0
5132
5133
5134
5135
5136
5137 
              false
5138
5139
5140
5141
5142
5143 
        gt_rxpmaresetdone
5144
5145 
          out
5146
5147 
            1
5148 
            0
5149
5150
5151
5152 
              std_logic_vector
5153 
              xilinx_anylanguagesynthesis
5154 
              xilinx_anylanguagebehavioralsimulation
5155
5156
5157
5158
5159
5160
5161 
              false
5162
5163
5164
5165
5166
5167 
        gt_rxresetdone
5168
5169 
          out
5170
5171 
            1
5172 
            0
5173
5174
5175
5176 
              std_logic_vector
5177 
              xilinx_anylanguagesynthesis
5178 
              xilinx_anylanguagebehavioralsimulation
5179
5180
5181
5182
5183
5184
5185 
              false
5186
5187
5188
5189
5190
5191 
        gt_rxbufstatus
5192
5193 
          out
5194
5195 
            5
5196 
            0
5197
5198
5199
5200 
              std_logic_vector
5201 
              xilinx_anylanguagesynthesis
5202 
              xilinx_anylanguagebehavioralsimulation
5203
5204
5205
5206
5207
5208
5209 
              false
5210
5211
5212
5213
5214
5215 
        gt_txphaligndone
5216
5217 
          out
5218
5219 
            1
5220 
            0
5221
5222
5223
5224 
              std_logic_vector
5225 
              xilinx_anylanguagesynthesis
5226 
              xilinx_anylanguagebehavioralsimulation
5227
5228
5229
5230
5231
5232
5233 
              false
5234
5235
5236
5237
5238
5239 
        gt_txphinitdone
5240
5241 
          out
5242
5243 
            1
5244 
            0
5245
5246
5247
5248 
              std_logic_vector
5249 
              xilinx_anylanguagesynthesis
5250 
              xilinx_anylanguagebehavioralsimulation
5251
5252
5253
5254
5255
5256
5257 
              false
5258
5259
5260
5261
5262
5263 
        gt_txdlysresetdone
5264
5265 
          out
5266
5267 
            1
5268 
            0
5269
5270
5271
5272 
              std_logic_vector
5273 
              xilinx_anylanguagesynthesis
5274 
              xilinx_anylanguagebehavioralsimulation
5275
5276
5277
5278
5279
5280
5281 
              false
5282
5283
5284
5285
5286
5287 
        gt_qplllock
5288
5289 
          out
5290
5291
5292 
              std_logic
5293 
              xilinx_anylanguagesynthesis
5294 
              xilinx_anylanguagebehavioralsimulation
5295
5296
5297
5298
5299
5300
5301 
              false
5302
5303
5304
5305
5306
5307 
        gt_eyescantrigger
5308
5309 
          in
5310
5311 
            1
5312 
            0
5313
5314
5315
5316 
              std_logic_vector
5317 
              xilinx_anylanguagesynthesis
5318 
              xilinx_anylanguagebehavioralsimulation
5319
5320
5321
5322 
            0
5323
5324
5325
5326
5327
5328 
              false
5329
5330
5331
5332
5333
5334 
        gt_eyescanreset
5335
5336 
          in
5337
5338 
            1
5339 
            0
5340
5341
5342
5343 
              std_logic_vector
5344 
              xilinx_anylanguagesynthesis
5345 
              xilinx_anylanguagebehavioralsimulation
5346
5347
5348
5349 
            0
5350
5351
5352
5353
5354
5355 
              false
5356
5357
5358
5359
5360
5361 
        gt_eyescandataerror
5362
5363 
          out
5364
5365 
            1
5366 
            0
5367
5368
5369
5370 
              std_logic_vector
5371 
              xilinx_anylanguagesynthesis
5372 
              xilinx_anylanguagebehavioralsimulation
5373
5374
5375
5376
5377
5378
5379 
              false
5380
5381
5382
5383
5384
5385 
        gt_rxrate
5386
5387 
          in
5388
5389 
            5
5390 
            0
5391
5392
5393
5394 
              std_logic_vector
5395 
              xilinx_anylanguagesynthesis
5396 
              xilinx_anylanguagebehavioralsimulation
5397
5398
5399
5400 
            0
5401
5402
5403
5404
5405
5406 
              false
5407
5408
5409
5410
5411
5412 
        gt_loopback
5413
5414 
          in
5415
5416 
            5
5417 
            0
5418
5419
5420
5421 
              std_logic_vector
5422 
              xilinx_anylanguagesynthesis
5423 
              xilinx_anylanguagebehavioralsimulation
5424
5425
5426
5427 
            0
5428
5429
5430
5431
5432
5433 
              false
5434
5435
5436
5437
5438
5439 
        gt_rxpolarity
5440
5441 
          in
5442
5443 
            1
5444 
            0
5445
5446
5447
5448 
              std_logic_vector
5449 
              xilinx_anylanguagesynthesis
5450 
              xilinx_anylanguagebehavioralsimulation
5451
5452
5453
5454 
            0
5455
5456
5457
5458
5459
5460 
              false
5461
5462
5463
5464
5465
5466 
        gt_txpolarity
5467
5468 
          in
5469
5470 
            1
5471 
            0
5472
5473
5474
5475 
              std_logic_vector
5476 
              xilinx_anylanguagesynthesis
5477 
              xilinx_anylanguagebehavioralsimulation
5478
5479
5480
5481 
            0
5482
5483
5484
5485
5486
5487 
              false
5488
5489
5490
5491
5492
5493 
        gt_rxlpmen
5494
5495 
          in
5496
5497 
            1
5498 
            0
5499
5500
5501
5502 
              std_logic_vector
5503 
              xilinx_anylanguagesynthesis
5504 
              xilinx_anylanguagebehavioralsimulation
5505
5506
5507
5508 
            0
5509
5510
5511
5512
5513
5514 
              false
5515
5516
5517
5518
5519
5520 
        gt_rxdfelpmreset
5521
5522 
          in
5523
5524 
            1
5525 
            0
5526
5527
5528
5529 
              std_logic_vector
5530 
              xilinx_anylanguagesynthesis
5531 
              xilinx_anylanguagebehavioralsimulation
5532
5533
5534
5535 
            0
5536
5537
5538
5539
5540
5541 
              false
5542
5543
5544
5545
5546
5547 
        gt_txpostcursor
5548
5549 
          in
5550
5551 
            9
5552 
            0
5553
5554
5555
5556 
              std_logic_vector
5557 
              xilinx_anylanguagesynthesis
5558 
              xilinx_anylanguagebehavioralsimulation
5559
5560
5561
5562 
            0
5563
5564
5565
5566
5567
5568 
              false
5569
5570
5571
5572
5573
5574 
        gt_txprecursor
5575
5576 
          in
5577
5578 
            9
5579 
            0
5580
5581
5582
5583 
              std_logic_vector
5584 
              xilinx_anylanguagesynthesis
5585 
              xilinx_anylanguagebehavioralsimulation
5586
5587
5588
5589 
            0
5590
5591
5592
5593
5594
5595 
              false
5596
5597
5598
5599
5600
5601 
        gt_txdiffctrl
5602
5603 
          in
5604
5605 
            7
5606 
            0
5607
5608
5609
5610 
              std_logic_vector
5611 
              xilinx_anylanguagesynthesis
5612 
              xilinx_anylanguagebehavioralsimulation
5613
5614
5615
5616 
            0
5617
5618
5619
5620
5621
5622 
              false
5623
5624
5625
5626
5627
5628 
        gt_rxprbscntreset
5629
5630 
          in
5631
5632 
            1
5633 
            0
5634
5635
5636
5637 
              std_logic_vector
5638 
              xilinx_anylanguagesynthesis
5639 
              xilinx_anylanguagebehavioralsimulation
5640
5641
5642
5643 
            0
5644
5645
5646
5647
5648
5649 
              false
5650
5651
5652
5653
5654
5655 
        gt_rxprbserr
5656
5657 
          out
5658
5659 
            1
5660 
            0
5661
5662
5663
5664 
              std_logic_vector
5665 
              xilinx_anylanguagesynthesis
5666 
              xilinx_anylanguagebehavioralsimulation
5667
5668
5669
5670
5671
5672
5673 
              false
5674
5675
5676
5677
5678
5679 
        gt_rxprbssel
5680
5681 
          in
5682
5683 
            7
5684 
            0
5685
5686
5687
5688 
              std_logic_vector
5689 
              xilinx_anylanguagesynthesis
5690 
              xilinx_anylanguagebehavioralsimulation
5691
5692
5693
5694 
            0
5695
5696
5697
5698
5699
5700 
              false
5701
5702
5703
5704
5705
5706 
        gt_txprbssel
5707
5708 
          in
5709
5710 
            7
5711 
            0
5712
5713
5714
5715 
              std_logic_vector
5716 
              xilinx_anylanguagesynthesis
5717 
              xilinx_anylanguagebehavioralsimulation
5718
5719
5720
5721 
            0
5722
5723
5724
5725
5726
5727 
              false
5728
5729
5730
5731
5732
5733 
        gt_txprbsforceerr
5734
5735 
          in
5736
5737 
            1
5738 
            0
5739
5740
5741
5742 
              std_logic_vector
5743 
              xilinx_anylanguagesynthesis
5744 
              xilinx_anylanguagebehavioralsimulation
5745
5746
5747
5748 
            0
5749
5750
5751
5752
5753
5754 
              false
5755
5756
5757
5758
5759
5760 
        gt_rxcdrhold
5761
5762 
          in
5763
5764 
            1
5765 
            0
5766
5767
5768
5769 
              std_logic_vector
5770 
              xilinx_anylanguagesynthesis
5771 
              xilinx_anylanguagebehavioralsimulation
5772
5773
5774
5775 
            0
5776
5777
5778
5779
5780
5781 
              false
5782
5783
5784
5785
5786
5787 
        gt_dmonitorout
5788
5789 
          out
5790
5791 
            7
5792 
            0
5793
5794
5795
5796 
              std_logic_vector
5797 
              xilinx_anylanguagesynthesis
5798 
              xilinx_anylanguagebehavioralsimulation
5799
5800
5801
5802
5803
5804
5805 
              false
5806
5807
5808
5809
5810
5811 
        gt_rxdisperr
5812
5813 
          out
5814
5815 
            7
5816 
            0
5817
5818
5819
5820 
              std_logic_vector
5821 
              xilinx_anylanguagesynthesis
5822 
              xilinx_anylanguagebehavioralsimulation
5823
5824
5825
5826
5827
5828
5829 
              false
5830
5831
5832
5833
5834
5835 
        gt_rxnotintable
5836
5837 
          out
5838
5839 
            7
5840 
            0
5841
5842
5843
5844 
              std_logic_vector
5845 
              xilinx_anylanguagesynthesis
5846 
              xilinx_anylanguagebehavioralsimulation
5847
5848
5849
5850
5851
5852
5853 
              false
5854
5855
5856
5857
5858
5859 
        gt_rxcommadet
5860
5861 
          out
5862
5863 
            1
5864 
            0
5865
5866
5867
5868 
              std_logic_vector
5869 
              xilinx_anylanguagesynthesis
5870 
              xilinx_anylanguagebehavioralsimulation
5871
5872
5873
5874
5875
5876
5877 
              false
5878
5879
5880
5881
5882
5883 
        gt_txinhibit
5884
5885 
          in
5886
5887 
            1
5888 
            0
5889
5890
5891
5892 
              std_logic_vector
5893 
              xilinx_anylanguagesynthesis
5894 
              xilinx_anylanguagebehavioralsimulation
5895
5896
5897
5898 
            0
5899
5900
5901
5902
5903
5904 
              false
5905
5906
5907
5908
5909
5910 
        gt_pcsrsvdin
5911
5912 
          in
5913
5914 
            31
5915 
            0
5916
5917
5918
5919 
              std_logic_vector
5920 
              xilinx_anylanguagesynthesis
5921 
              xilinx_anylanguagebehavioralsimulation
5922
5923
5924
5925 
            0
5926
5927
5928
5929
5930
5931 
              false
5932
5933
5934
5935
5936
5937 
        gt0_drpaddr
5938
5939 
          in
5940
5941 
            8
5942 
            0
5943
5944
5945
5946 
              std_logic_vector
5947 
              xilinx_anylanguagesynthesis
5948 
              xilinx_anylanguagebehavioralsimulation
5949
5950
5951
5952 
            0
5953
5954
5955
5956
5957
5958 
              false
5959
5960
5961
5962
5963
5964 
        gt0_drpen
5965
5966 
          in
5967
5968
5969 
              std_logic
5970 
              xilinx_anylanguagesynthesis
5971 
              xilinx_anylanguagebehavioralsimulation
5972
5973
5974
5975 
            0
5976
5977
5978
5979
5980
5981 
              false
5982
5983
5984
5985
5986
5987 
        gt0_drpdi
5988
5989 
          in
5990
5991 
            15
5992 
            0
5993
5994
5995
5996 
              std_logic_vector
5997 
              xilinx_anylanguagesynthesis
5998 
              xilinx_anylanguagebehavioralsimulation
5999
6000
6001
6002 
            0
6003
6004
6005
6006
6007
6008 
              false
6009
6010
6011
6012
6013
6014 
        gt0_drpdo
6015
6016 
          out
6017
6018 
            15
6019 
            0
6020
6021
6022
6023 
              std_logic_vector
6024 
              xilinx_anylanguagesynthesis
6025 
              xilinx_anylanguagebehavioralsimulation
6026
6027
6028
6029
6030
6031
6032 
              false
6033
6034
6035
6036
6037
6038 
        gt0_drprdy
6039
6040 
          out
6041
6042
6043 
              std_logic
6044 
              xilinx_anylanguagesynthesis
6045 
              xilinx_anylanguagebehavioralsimulation
6046
6047
6048
6049
6050
6051
6052 
              false
6053
6054
6055
6056
6057
6058 
        gt0_drpwe
6059
6060 
          in
6061
6062
6063 
              std_logic
6064 
              xilinx_anylanguagesynthesis
6065 
              xilinx_anylanguagebehavioralsimulation
6066
6067
6068
6069 
            0
6070
6071
6072
6073
6074
6075 
              false
6076
6077
6078
6079
6080
6081 
        gt0_drp_busy
6082
6083 
          out
6084
6085
6086 
              std_logic
6087 
              xilinx_anylanguagesynthesis
6088 
              xilinx_anylanguagebehavioralsimulation
6089
6090
6091
6092
6093
6094
6095 
              false
6096
6097
6098
6099
6100
6101 
        gt1_drpaddr
6102
6103 
          in
6104
6105 
            8
6106 
            0
6107
6108
6109
6110 
              std_logic_vector
6111 
              xilinx_anylanguagesynthesis
6112 
              xilinx_anylanguagebehavioralsimulation
6113
6114
6115
6116 
            0
6117
6118
6119
6120
6121
6122 
              false
6123
6124
6125
6126
6127
6128 
        gt1_drpen
6129
6130 
          in
6131
6132
6133 
              std_logic
6134 
              xilinx_anylanguagesynthesis
6135 
              xilinx_anylanguagebehavioralsimulation
6136
6137
6138
6139 
            0
6140
6141
6142
6143
6144
6145 
              false
6146
6147
6148
6149
6150
6151 
        gt1_drpdi
6152
6153 
          in
6154
6155 
            15
6156 
            0
6157
6158
6159
6160 
              std_logic_vector
6161 
              xilinx_anylanguagesynthesis
6162 
              xilinx_anylanguagebehavioralsimulation
6163
6164
6165
6166 
            0
6167
6168
6169
6170
6171
6172 
              false
6173
6174
6175
6176
6177
6178 
        gt1_drpdo
6179
6180 
          out
6181
6182 
            15
6183 
            0
6184
6185
6186
6187 
              std_logic_vector
6188 
              xilinx_anylanguagesynthesis
6189 
              xilinx_anylanguagebehavioralsimulation
6190
6191
6192
6193
6194
6195
6196 
              false
6197
6198
6199
6200
6201
6202 
        gt1_drprdy
6203
6204 
          out
6205
6206
6207 
              std_logic
6208 
              xilinx_anylanguagesynthesis
6209 
              xilinx_anylanguagebehavioralsimulation
6210
6211
6212
6213
6214
6215
6216 
              false
6217
6218
6219
6220
6221
6222 
        gt1_drpwe
6223
6224 
          in
6225
6226
6227 
              std_logic
6228 
              xilinx_anylanguagesynthesis
6229 
              xilinx_anylanguagebehavioralsimulation
6230
6231
6232
6233 
            0
6234
6235
6236
6237
6238
6239 
              false
6240
6241
6242
6243
6244
6245 
        gt1_drp_busy
6246
6247 
          out
6248
6249
6250 
              std_logic
6251 
              xilinx_anylanguagesynthesis
6252 
              xilinx_anylanguagebehavioralsimulation
6253
6254
6255
6256
6257
6258
6259 
              false
6260
6261
6262
6263
6264
6265 
        mdc
6266
6267 
          in
6268
6269
6270 
              std_logic
6271 
              xilinx_anylanguagesynthesis
6272 
              xilinx_anylanguagebehavioralsimulation
6273
6274
6275
6276 
            0
6277
6278
6279
6280
6281
6282 
              true
6283
6284
6285
6286
6287
6288 
        mdio_in
6289
6290 
          in
6291
6292
6293 
              std_logic
6294 
              xilinx_anylanguagesynthesis
6295 
              xilinx_anylanguagebehavioralsimulation
6296
6297
6298
6299 
            0
6300
6301
6302
6303
6304
6305 
              true
6306
6307
6308
6309
6310
6311 
        mdio_out
6312
6313 
          out
6314
6315
6316 
              std_logic
6317 
              xilinx_anylanguagesynthesis
6318 
              xilinx_anylanguagebehavioralsimulation
6319
6320
6321
6322
6323
6324
6325 
              true
6326
6327
6328
6329
6330
6331 
        mdio_tri
6332
6333 
          out
6334
6335
6336 
              std_logic
6337 
              xilinx_anylanguagesynthesis
6338 
              xilinx_anylanguagebehavioralsimulation
6339
6340
6341
6342
6343
6344
6345 
              true
6346
6347
6348
6349
6350
6351 
        prtad
6352
6353 
          in
6354
6355 
            4
6356 
            0
6357
6358
6359
6360 
              std_logic_vector
6361 
              xilinx_anylanguagesynthesis
6362 
              xilinx_anylanguagebehavioralsimulation
6363
6364
6365
6366 
            0
6367
6368
6369
6370
6371
6372 
              true
6373
6374
6375
6376
6377
6378 
        type_sel
6379
6380 
          in
6381
6382 
            1
6383 
            0
6384
6385
6386
6387 
              std_logic_vector
6388 
              xilinx_anylanguagesynthesis
6389 
              xilinx_anylanguagebehavioralsimulation
6390
6391
6392
6393 
            0
6394
6395
6396
6397
6398
6399 
              true
6400
6401
6402
6403
6404
6405 
        configuration_vector
6406
6407 
          in
6408
6409 
            6
6410 
            0
6411
6412
6413
6414 
              std_logic_vector
6415 
              xilinx_anylanguagesynthesis
6416 
              xilinx_anylanguagebehavioralsimulation
6417
6418
6419
6420 
            0
6421
6422
6423
6424
6425
6426 
              false
6427
6428
6429
6430
6431
6432 
        status_vector
6433
6434 
          out
6435
6436 
            7
6437 
            0
6438
6439
6440
6441 
              std_logic_vector
6442 
              xilinx_anylanguagesynthesis
6443 
              xilinx_anylanguagebehavioralsimulation
6444
6445
6446
6447
6448
6449
6450 
              false
6451
6452
6453
6454
6455
6456
6457
6458 
        c_family
6459 
        kintex7
6460
6461
6462 
        c_component_name
6463 
        rxaui_0
6464
6465
6466 
        c_rxaui_mode
6467 
        0
6468
6469
6470 
        c_txdata_width
6471 
        64
6472
6473
6474 
        c_rxdata_width
6475 
        64
6476
6477
6478 
        c_has_mdio
6479 
        true
6480
6481
6482 
        c_gtwizardSubCoreName
6483 
        rxaui_0_gt
6484
6485
6486 
        c_gt_dmonitorout_width
6487 
        8
6488
6489
6490 
        c_gt_txdiffctrl_width
6491 
        8
6492
6493
6494 
        c_gt_daddr_width
6495 
        9
6496
6497
6498 
        c_refclkrate
6499 
        156.25
6500
6501
6502 
        c_drpclk_freq
6503 
        100.0
6504
6505
6506 
        c_gt_loc
6507 
        X0Y0 X0Y1
6508
6509
6510
6511
6512
6513 
      choice_list_20920dd1
6514 
      GTH
6515 
      GTY
6516
6517
6518 
      choice_list_4dbacc44
6519 
      125
6520 
      156.25
6521 
      312.5
6522
6523
6524 
      choice_list_767a41eb
6525 
      Dune
6526 
      Marvell
6527
6528
6529 
      choice_list_949abb3f
6530 
      X0Y0
6531
6532
6533 
      choice_list_e32fe488
6534 
      GTPE2
6535 
      GTXE2
6536 
      GTHE2
6537 
      GTHE3
6538 
      GTYE3
6539 
      GTHE4
6540 
      GTYE4
6541
6542
6543 
      choice_pairs_53749dec
6544 
      1
6545 
      0
6546
6547
6548
6549
6550 
      xilinx_vhdlinstantiationtemplate_view_fileset
6551
6552 
        rxaui_0.vho
6553 
        vhdlTemplate
6554
6555
6556 
        rxaui_0.veo
6557 
        verilogTemplate
6558
6559
6560
6561 
      xilinx_versioninformation_view_fileset
6562
6563 
        doc/rxaui_v4_3_changelog.txt
6564 
        text
6565
6566
6567
6568 
      xilinx_anylanguagesynthesis_xilinx_com_ip_xaui_12_2__ref_view_fileset
6569
6570 
        hdl/xaui_v12_2_rfs.vhd
6571 
        vhdlSource
6572 
        xaui_v12_2_7
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583 
      xilinx_anylanguagesynthesis_view_fileset
6584
6585 
        hdl/rxaui_v4_3_rfs.vhd
6586 
        vhdlSource
6587 
        rxaui_v4_3_7
6588
6589
6590 
        hdl/rxaui_v4_3_rfs.v
6591 
        verilogSource
6592 
        rxaui_v4_3_7
6593
6594
6595 
        synth/rxaui_0.xdc
6596 
        xdc
6597
6598
6599 
        synth/rxaui_0_ooc.xdc
6600 
        xdc
6601 
        USED_IN_implementation
6602 
        USED_IN_out_of_context
6603 
        USED_IN_synthesis
6604
6605
6606 
        synth/rxaui_0_ff_synchronizer.vhd
6607 
        vhdlSource
6608
6609
6610 
        synth/rxaui_0_tx_sync_sync_block.vhd
6611 
        vhdlSource
6612
6613
6614 
        synth/rxaui_0_tx_sync_sync_pulse.vhd
6615 
        vhdlSource
6616
6617
6618 
        tx_sync_manual_vhd.txt
6619 
        text
6620
6621
6622 
        synth/rxaui_0_gt_wrapper_tx_sync_manual.vhd
6623 
        vhdlSource
6624
6625
6626 
        synth/rxaui_0_reset_counter.vhd
6627 
        vhdlSource
6628
6629
6630 
        synth/rxaui_0_gt_wrapper_gt.vhd
6631 
        vhdlSource
6632
6633
6634 
        synth/rxaui_0_cl_clocking.vhd
6635 
        vhdlSource
6636
6637
6638 
        synth/rxaui_0_cl_resets.vhd
6639 
        vhdlSource
6640
6641
6642 
        synth/rxaui_0_block.vhd
6643 
        vhdlSource
6644
6645
6646 
        synth/rxaui_0_support.vhd
6647 
        vhdlSource
6648
6649
6650 
        synth/rxaui_0_support_clocking.vhd
6651 
        vhdlSource
6652
6653
6654 
        synth/rxaui_0_support_resets.vhd
6655 
        vhdlSource
6656
6657
6658 
        synth/rxaui_0_gt_common_wrapper.vhd
6659 
        vhdlSource
6660
6661
6662
6663 
      xilinx_vhdlsynthesiswrapper_view_fileset
6664
6665 
        synth/rxaui_0.vhd
6666 
        vhdlSource
6667
6668
6669
6670 
      xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xaui_12_2__ref_view_fileset
6671
6672 
        hdl/xaui_v12_2_rfs.vhd
6673 
        vhdlSource
6674 
        USED_IN_ipstatic
6675 
        xaui_v12_2_7
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686 
      xilinx_anylanguagebehavioralsimulation_view_fileset
6687
6688 
        hdl/rxaui_v4_3_rfs.vhd
6689 
        vhdlSource
6690 
        USED_IN_ipstatic
6691 
        rxaui_v4_3_7
6692
6693
6694 
        hdl/rxaui_v4_3_rfs.v
6695 
        verilogSource
6696 
        USED_IN_ipstatic
6697 
        rxaui_v4_3_7
6698
6699
6700 
        synth/rxaui_0_ff_synchronizer.vhd
6701 
        vhdlSource
6702
6703
6704 
        synth/rxaui_0_reset_counter.vhd
6705 
        vhdlSource
6706
6707
6708 
        synth/rxaui_0_tx_sync_sync_block.vhd
6709 
        vhdlSource
6710
6711
6712 
        synth/rxaui_0_tx_sync_sync_pulse.vhd
6713 
        vhdlSource
6714
6715
6716 
        tx_sync_manual_vhd.txt
6717 
        text
6718
6719
6720 
        synth/rxaui_0_gt_wrapper_tx_sync_manual.vhd
6721 
        vhdlSource
6722
6723
6724 
        synth/rxaui_0_gt_wrapper_gt.vhd
6725 
        vhdlSource
6726
6727
6728 
        synth/rxaui_0_cl_clocking.vhd
6729 
        vhdlSource
6730
6731
6732 
        synth/rxaui_0_cl_resets.vhd
6733 
        vhdlSource
6734
6735
6736 
        synth/rxaui_0_block.vhd
6737 
        vhdlSource
6738
6739
6740 
        synth/rxaui_0_support.vhd
6741 
        vhdlSource
6742
6743
6744 
        synth/rxaui_0_support_clocking.vhd
6745 
        vhdlSource
6746
6747
6748 
        synth/rxaui_0_support_resets.vhd
6749 
        vhdlSource
6750
6751
6752 
        synth/rxaui_0_gt_common_wrapper.vhd
6753 
        vhdlSource
6754
6755
6756
6757 
      xilinx_vhdlsimulationwrapper_view_fileset
6758
6759 
        synth/rxaui_0.vhd
6760 
        vhdlSource
6761
6762
6763
6764 
      xilinx_externalfiles_view_fileset
6765
6766 
        rxaui_0.dcp
6767 
        dcp
6768 
        USED_IN_implementation
6769 
        USED_IN_synthesis
6770 
        xil_defaultlib
6771
6772
6773 
        rxaui_0_stub.v
6774 
        verilogSource
6775 
        USED_IN_synth_blackbox_stub
6776 
        xil_defaultlib
6777
6778
6779 
        rxaui_0_stub.vhdl
6780 
        vhdlSource
6781 
        USED_IN_synth_blackbox_stub
6782 
        xil_defaultlib
6783
6784
6785 
        rxaui_0_sim_netlist.v
6786 
        verilogSource
6787 
        USED_IN_simulation
6788 
        USED_IN_single_language
6789 
        xil_defaultlib
6790
6791
6792 
        rxaui_0_sim_netlist.vhdl
6793 
        vhdlSource
6794 
        USED_IN_simulation
6795 
        USED_IN_single_language
6796 
        xil_defaultlib
6797
6798
6799
6800 
  The Xilinx Reduced Pin 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE provides a 2-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput.  Operating at an internal clock speed of 156.25 MHz, the core includes the Dune Networks RXAUI implementation, the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2008.  The core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2008 clause 45 management registers.  The MDIO interface may be omitted to save slice logic, in which case a simplified management interface is provided via bit vectors.  The core is designed to seamlessly interface with the 10 Gigabit Ethernet Media Access Controller (XGMAC) LogiCORE via the XGMII.
6801
6802
6803 
      Component_Name
6804 
      rxaui_0
6805
6806
6807
6808 
            true
6809
6810
6811
6812
6813
6814 
      RXAUI_Mode
6815 
      Dune
6816
6817
6818
6819 
            false
6820
6821
6822
6823
6824
6825 
      Mdio_Management
6826 
      true
6827
6828
6829
6830 
            true
6831
6832
6833
6834
6835
6836 
      SupportLevel
6837 
      1
6838
6839
6840
6841 
            true
6842
6843
6844
6845
6846
6847 
      TransceiverControl
6848 
      false
6849
6850
6851
6852 
            true
6853
6854
6855
6856
6857
6858 
      Transceiver
6859 
      GTXE2
6860
6861
6862
6863 
            false
6864
6865
6866
6867
6868
6869 
      vu_gt_type
6870 
      GT TYPE
6871 
      GTH
6872
6873
6874
6875 
            false
6876
6877
6878
6879
6880
6881 
      RefClkRate
6882 
      Reference Clock Frequency (MHz)
6883 
      156.25
6884
6885
6886
6887 
            false
6888
6889
6890
6891
6892
6893 
      DRPCLK_FREQ
6894 
      100.0
6895
6896
6897
6898 
            true
6899
6900
6901
6902
6903
6904 
      Locations
6905 
      Transceiver Location
6906 
      X0Y0
6907
6908
6909
6910
6911 
      RXAUI
6912 
      7
6913
6914
6915
6916
6917
6918
6919 
      2016.4
6920
6921
6922
6923
6924
6925
6926
6927

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