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1 4 DFC 
-------------------------------------------------------------------------------
2 
-- Title      : Block level
3 
-- Project    : RXAUI
4 
-------------------------------------------------------------------------------
5 
-- File       : rxaui_0_block.vhd
6 
-------------------------------------------------------------------------------
7 
-- Description: This file is a wrapper for the RXAUI core. It contains the
8 
-- RXAUI core, the transceivers and some transceiver logic.
9 
-------------------------------------------------------------------------------
10 
-- (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
11 
--
12 
-- This file contains confidential and proprietary information
13 
-- of Xilinx, Inc. and is protected under U.S. and
14 
-- international copyright and other intellectual property
15 
-- laws.
16 
--
17 
-- DISCLAIMER
18 
-- This disclaimer is not a license and does not grant any
19 
-- rights to the materials distributed herewith. Except as
20 
-- otherwise provided in a valid license issued to you by
21 
-- Xilinx, and to the maximum extent permitted by applicable
22 
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
23 
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
24 
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
25 
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
26 
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
27 
-- (2) Xilinx shall not be liable (whether in contract or tort,
28 
-- including negligence, or under any other theory of
29 
-- liability) for any loss or damage of any kind or nature
30 
-- related to, arising under or in connection with these
31 
-- materials, including for any direct, or any indirect,
32 
-- special, incidental, or consequential loss or damage
33 
-- (including loss of data, profits, goodwill, or any type of
34 
-- loss or damage suffered as a result of any action brought
35 
-- by a third party) even if such damage or loss was
36 
-- reasonably foreseeable or Xilinx had been advised of the
37 
-- possibility of the same.
38 
--
39 
-- CRITICAL APPLICATIONS
40 
-- Xilinx products are not designed or intended to be fail-
41 
-- safe, or for use in any application requiring fail-safe
42 
-- performance, such as life-support or safety devices or
43 
-- systems, Class III medical devices, nuclear facilities,
44 
-- applications related to the deployment of airbags, or any
45 
-- other applications that could lead to death, personal
46 
-- injury, or severe property or environmental damage
47 
-- (individually and collectively, "Critical
48 
-- Applications"). Customer assumes the sole risk and
49 
-- liability of any use of Xilinx products in Critical
50 
-- Applications, subject only to applicable laws and
51 
-- regulations governing limitations on product liability.
52 
--
53 
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
54 
-- PART OF THIS FILE AT ALL TIMES.
55 
-------------------------------------------------------------------------------
56 
 
57 
library ieee;
58 
use ieee.std_logic_1164.all;
59 
use ieee.numeric_std.all;
60 
 
61 
entity rxaui_0_block is
62 
    port (
63 
      reset                                 : in  std_logic; -- Asynchronous Reset
64 
      dclk                                  : in  std_logic; -- Stable Clock
65 
      clk156_out                            : out std_logic; -- 156.25MHz output clock derived from the GT
66 
      clk156_lock                           : out std_logic; -- 156.25MHz clock ready for use
67 
      refclk                                : in  std_logic; -- Refclk from IBUDS_GTE2
68 
      qplloutclk                            : in  std_logic; -- output clock from common PLL
69 
      qplllock                              : in  std_logic; -- locked indicator from common PLL
70 
      qplloutrefclk                         : in  std_logic; -- refclk from common PLL
71 
      xgmii_txd                             : in  std_logic_vector(63 downto 0); -- XGMII Tx Data
72 
      xgmii_txc                             : in  std_logic_vector(7 downto 0);  -- XGMII Tx Control
73 
      xgmii_rxd                             : out std_logic_vector(63 downto 0); -- XGMII Rx Data
74 
      xgmii_rxc                             : out std_logic_vector(7 downto 0);  -- XGMII Rx Control
75 
      rxaui_tx_l0_p                         : out std_logic; -- GT0 TXP
76 
      rxaui_tx_l0_n                         : out std_logic; -- GT0 TXN
77 
      rxaui_tx_l1_p                         : out std_logic; -- GT1 TXP
78 
      rxaui_tx_l1_n                         : out std_logic; -- GT1 TXN
79 
      rxaui_rx_l0_p                         : in  std_logic; -- GT0 RXP
80 
      rxaui_rx_l0_n                         : in  std_logic; -- GT0 RXN
81 
      rxaui_rx_l1_p                         : in  std_logic; -- GT1 RXP
82 
      rxaui_rx_l1_n                         : in  std_logic; -- GT1 RXN
83 
      signal_detect                         : in  std_logic_vector(1 downto 0); -- Signal Detect from optical interface
84 
      debug                                 : out std_logic_vector(5 downto 0); -- Debug vector
85 
   -- GT Control Ports
86 
   -- The following signals are connected directly to/from the transceiver
87 
   -- DRP
88 
      gt0_drpaddr                           : in  std_logic_vector(8 downto 0);
89 
      gt0_drpen                             : in  std_logic;
90 
      gt0_drpdi                             : in  std_logic_vector(15 downto 0);
91 
      gt0_drpdo                             : out std_logic_vector(15 downto 0);
92 
      gt0_drprdy                            : out std_logic;
93 
      gt0_drpwe                             : in  std_logic;
94 
   -- TX Reset and Initialisation
95 
      gt0_txpmareset_in                     : in std_logic;
96 
      gt0_txpcsreset_in                     : in std_logic;
97 
      gt0_txresetdone_out                   : out std_logic;
98 
   -- RX Reset and Initialisation
99 
      gt0_rxpmareset_in                     : in std_logic;
100 
      gt0_rxpcsreset_in                     : in std_logic;
101 
      gt0_rxresetdone_out                   : out std_logic;
102 
   -- Clocking
103 
      gt0_rxbufstatus_out                   : out std_logic_vector(2 downto 0);
104 
      gt0_txphaligndone_out                 : out std_logic;
105 
      gt0_txphinitdone_out                  : out std_logic;
106 
      gt0_txdlysresetdone_out               : out std_logic;
107 
      gt_qplllock_out                             : out std_logic;
108 
   -- Signal Integrity adn Functionality
109 
   -- Eye Scan
110 
      gt0_eyescantrigger_in                 : in  std_logic;
111 
      gt0_eyescanreset_in                   : in  std_logic;
112 
      gt0_eyescandataerror_out              : out std_logic;
113 
      gt0_rxrate_in                         : in  std_logic_vector(2 downto 0);
114 
   -- Loopback
115 
      gt0_loopback_in                       : in  std_logic_vector(2 downto 0);
116 
   -- Polarity
117 
      gt0_rxpolarity_in                     : in  std_logic;
118 
      gt0_txpolarity_in                     : in  std_logic;
119 
   -- RX Decision Feedback Equalizer(DFE)
120 
      gt0_rxlpmen_in                        : in  std_logic;
121 
      gt0_rxdfelpmreset_in                  : in  std_logic;
122 
      gt0_rxmonitorsel_in                   : in  std_logic_vector(1 downto 0);
123 
      gt0_rxmonitorout_out                  : out std_logic_vector(6 downto 0);
124 
   -- TX Driver
125 
      gt0_txpostcursor_in                   : in  std_logic_vector(4 downto 0);
126 
      gt0_txprecursor_in                    : in  std_logic_vector(4 downto 0);
127 
      gt0_txdiffctrl_in                     : in  std_logic_vector(3 downto 0);
128 
      gt0_txinhibit_in                      : in  std_logic;
129 
   -- PRBS
130 
      gt0_rxprbscntreset_in                 : in  std_logic;
131 
      gt0_rxprbserr_out                     : out std_logic;
132 
      gt0_rxprbssel_in                      : in  std_logic_vector(2 downto 0);
133 
      gt0_txprbssel_in                      : in  std_logic_vector(2 downto 0);
134 
      gt0_txprbsforceerr_in                 : in  std_logic;
135 
 
136 
      gt0_rxcdrhold_in                      : in  std_logic;
137 
      gt0_dmonitorout_out                   : out std_logic_vector(7 downto 0);
138 
 
139 
   -- Status
140 
      gt0_rxdisperr_out                     : out std_logic_vector(3 downto 0);
141 
      gt0_rxnotintable_out                  : out std_logic_vector(3 downto 0);
142 
      gt0_rxcommadet_out                    : out std_logic;
143 
   -- DRP
144 
      gt1_drpaddr                           : in  std_logic_vector(8 downto 0);
145 
      gt1_drpen                             : in  std_logic;
146 
      gt1_drpdi                             : in  std_logic_vector(15 downto 0);
147 
      gt1_drpdo                             : out std_logic_vector(15 downto 0);
148 
      gt1_drprdy                            : out std_logic;
149 
      gt1_drpwe                             : in  std_logic;
150 
   -- TX Reset and Initialisation
151 
      gt1_txpmareset_in                     : in std_logic;
152 
      gt1_txpcsreset_in                     : in std_logic;
153 
      gt1_txresetdone_out                   : out std_logic;
154 
   -- RX Reset and Initialisation
155 
      gt1_rxpmareset_in                     : in std_logic;
156 
      gt1_rxpcsreset_in                     : in std_logic;
157 
      gt1_rxresetdone_out                   : out std_logic;
158 
   -- Clocking
159 
      gt1_rxbufstatus_out                   : out std_logic_vector(2 downto 0);
160 
      gt1_txphaligndone_out                 : out std_logic;
161 
      gt1_txphinitdone_out                  : out std_logic;
162 
      gt1_txdlysresetdone_out               : out std_logic;
163 
   -- Signal Integrity adn Functionality
164 
   -- Eye Scan
165 
      gt1_eyescantrigger_in                 : in  std_logic;
166 
      gt1_eyescanreset_in                   : in  std_logic;
167 
      gt1_eyescandataerror_out              : out std_logic;
168 
      gt1_rxrate_in                         : in  std_logic_vector(2 downto 0);
169 
   -- Loopback
170 
      gt1_loopback_in                       : in  std_logic_vector(2 downto 0);
171 
   -- Polarity
172 
      gt1_rxpolarity_in                     : in  std_logic;
173 
      gt1_txpolarity_in                     : in  std_logic;
174 
   -- RX Decision Feedback Equalizer(DFE)
175 
      gt1_rxlpmen_in                        : in  std_logic;
176 
      gt1_rxdfelpmreset_in                  : in  std_logic;
177 
      gt1_rxmonitorsel_in                   : in  std_logic_vector(1 downto 0);
178 
      gt1_rxmonitorout_out                  : out std_logic_vector(6 downto 0);
179 
   -- TX Driver
180 
      gt1_txpostcursor_in                   : in  std_logic_vector(4 downto 0);
181 
      gt1_txprecursor_in                    : in  std_logic_vector(4 downto 0);
182 
      gt1_txdiffctrl_in                     : in  std_logic_vector(3 downto 0);
183 
      gt1_txinhibit_in                      : in  std_logic;
184 
   -- PRBS
185 
      gt1_rxprbscntreset_in                 : in  std_logic;
186 
      gt1_rxprbserr_out                     : out std_logic;
187 
      gt1_rxprbssel_in                      : in  std_logic_vector(2 downto 0);
188 
      gt1_txprbssel_in                      : in  std_logic_vector(2 downto 0);
189 
      gt1_txprbsforceerr_in                 : in  std_logic;
190 
 
191 
      gt1_rxcdrhold_in                      : in  std_logic;
192 
      gt1_dmonitorout_out                   : out std_logic_vector(7 downto 0);
193 
 
194 
   -- Status
195 
      gt1_rxdisperr_out                     : out std_logic_vector(3 downto 0);
196 
      gt1_rxnotintable_out                  : out std_logic_vector(3 downto 0);
197 
      gt1_rxcommadet_out                    : out std_logic;
198 
   -- MDIO Interface
199 
      mdc                                   : in  std_logic;                    -- MDIO Clock
200 
      mdio_in                               : in  std_logic;                    -- MDIO Input
201 
      mdio_out                              : out std_logic;                    -- MDIO Output
202 
      mdio_tri                              : out std_logic;                    -- MDIO Tri-state enable
203 
      prtad                                 : in  std_logic_vector(4 downto 0); -- MDIO PRTAD
204 
      type_sel                              : in  std_logic_vector(1 downto 0)  -- type_sel control
205 
);
206 
end rxaui_0_block;
207 
 
208 
library ieee;
209 
use ieee.numeric_std.all;
210 
 
211 
library unisim;
212 
use unisim.vcomponents.all;
213 
 
214 
library rxaui_v4_3_7;
215 
use rxaui_v4_3_7.all;
216 
 
217 
architecture wrapper of rxaui_0_block is
218 
 
219 
----------------------------------------------------------------------------
220 
-- Component Declaration for the RXAUI core.
221 
----------------------------------------------------------------------------
222 
 
223 
   component rxaui_v4_3_7_top
224 
      generic (
225 
      c_family                              : string  := "virtex7";
226 
      c_rxaui_mode                          : integer := 0;
227 
      c_txdata_width                        : integer := 0;
228 
      c_rxdata_width                        : integer := 0;
229 
      c_has_mdio                            : boolean := true
230 
      );
231 
      port (
232 
      reset                                 : in  std_logic;
233 
      xgmii_txd                             : in  std_logic_vector(63 downto 0);
234 
      xgmii_txc                             : in  std_logic_vector(7 downto 0);
235 
      xgmii_rxd                             : out std_logic_vector(63 downto 0);
236 
      xgmii_rxc                             : out std_logic_vector(7 downto 0);
237 
      usrclk                                : in  std_logic;
238 
      rxclk                                 : in  std_logic;
239 
      mgt_txdata                            : out std_logic_vector(c_txdata_width - 1 downto 0);
240 
      mgt_txcharisk                         : out std_logic_vector(7 downto 0);
241 
      mgt_rxdata                            : in  std_logic_vector(c_rxdata_width - 1 downto 0);
242 
      mgt_rxcharisk                         : in std_logic_vector(7 downto 0);
243 
      mgt_codevalid                         : in std_logic_vector(7 downto 0);
244 
      mgt_codecomma                         : in std_logic_vector(7 downto 0);
245 
      mgt_enchansync                        : out std_logic;
246 
      mgt_enable_align                      : out std_logic_vector(1 downto 0);
247 
      mgt_rxlock                            : in  std_logic_vector(1 downto 0);
248 
      mgt_loopback                          : out std_logic;
249 
      mgt_powerdown                         : out std_logic;
250 
      mgt_tx_reset                          : in  std_logic_vector(1 downto 0);
251 
      mgt_rx_reset                          : in  std_logic_vector(1 downto 0);
252 
      soft_reset                            : out std_logic;
253 
      signal_detect                         : in  std_logic_vector(1 downto 0);
254 
      align_status                          : out std_logic;
255 
      sync_status                           : out std_logic_vector(3 downto 0);
256 
      mdc                                   : in  std_logic;
257 
      mdio_in                               : in  std_logic;
258 
      mdio_out                              : out std_logic;
259 
      mdio_tri                              : out std_logic;
260 
      prtad                                 : in  std_logic_vector(4 downto 0);
261 
      type_sel                              : in  std_logic_vector(1 downto 0);
262 
      configuration_vector                  : in  std_logic_vector(6 downto 0);
263 
      status_vector                         : out std_logic_vector(7 downto 0));
264 
  end component;
265 
 
266 
  component rxaui_0_gt_wrapper_GT
267 
  generic
268 
  (
269 
    -- Simulation attributes
270 
    GT_SIM_GTRESET_SPEEDUP                  : string     := "true";
271 
    RX_DFE_KL_CFG2_IN                       : bit_vector := X"3010D90C";
272 
    SIM_CPLLREFCLK_SEL                      : bit_vector :=   "001";
273 
    PMA_RSV_IN                              : bit_vector := X"00000000";
274 
    PCS_RSVD_ATTR_IN                        : bit_vector := X"000000000000"
275 
  );
276 
  port
277 
  (
278 
    cpllrefclksel_in : in std_logic_vector(2 downto 0);
279 
    ---------------------------------- Channel ---------------------------------
280 
    qpllclk_in                              : in   std_logic;
281 
    qpllrefclk_in                           : in   std_logic;
282 
    ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
283 
    drpaddr_in                              : in   std_logic_vector(8 downto 0);
284 
    drpclk_in                               : in   std_logic;
285 
    drpdi_in                                : in   std_logic_vector(15 downto 0);
286 
    drpdo_out                               : out  std_logic_vector(15 downto 0);
287 
    drpen_in                                : in   std_logic;
288 
    drprdy_out                              : out  std_logic;
289 
    drpwe_in                                : in   std_logic;
290 
    ------------------------- Digital Monitor Ports --------------------------
291 
    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
292 
    ------------------------------- Eye Scan Ports -----------------------------
293 
    eyescandataerror_out                    : out  std_logic;
294 
    eyescanreset_in                         : in   std_logic;
295 
    eyescantrigger_in                       : in   std_logic;
296 
    rxrate_in                               : in   std_logic_vector(2 downto 0);
297 
    ------------------------- Receive Ports - CDR Ports ------------------------
298 
    rxcdrhold_in                            : in   std_logic;
299 
    ------------------------ Loopback and Powerdown Ports ----------------------
300 
    loopback_in                             : in   std_logic_vector(2 downto 0);
301 
    rxpd_in                                 : in   std_logic_vector(1 downto 0);
302 
    txpd_in                                 : in   std_logic_vector(1 downto 0);
303 
    ------------------------------- Receive Ports ------------------------------
304 
    rxuserrdy_in                            : in   std_logic;
305 
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
306 
    rxchariscomma_out                       : out  std_logic_vector(3 downto 0);
307 
    rxcharisk_out                           : out  std_logic_vector(3 downto 0);
308 
    rxdisperr_out                           : out  std_logic_vector(3 downto 0);
309 
    rxnotintable_out                        : out  std_logic_vector(3 downto 0);
310 
    ------------------- Receive Ports - Channel Bonding Ports ------------------
311 
    rxchanbondseq_out                       : out  std_logic;
312 
    rxchbonden_in                           : in   std_logic;
313 
    rxchbondi_in                            : in   std_logic_vector(4 downto 0);
314 
    rxchbondlevel_in                        : in   std_logic_vector(2 downto 0);
315 
    rxchbondmaster_in                       : in   std_logic;
316 
    rxchbondo_out                           : out  std_logic_vector(4 downto 0);
317 
    rxchbondslave_in                        : in   std_logic;
318 
    ------------------- Receive Ports - Channel Bonding Ports  -----------------
319 
    rxchanisaligned_out                     : out  std_logic;
320 
    rxchanrealign_out                       : out  std_logic;
321 
    ------------------- Receive Ports - Clock Correction Ports -----------------
322 
    rxclkcorcnt_out                         : out  std_logic_vector(1 downto 0);
323 
    --------------- Receive Ports - Comma Detection and Alignment --------------
324 
    rxbyteisaligned_out                     : out  std_logic;
325 
    rxbyterealign_out                       : out  std_logic;
326 
    rxcommadet_out                          : out  std_logic;
327 
    rxmcommaalignen_in                      : in   std_logic;
328 
    rxpcommaalignen_in                      : in   std_logic;
329 
    ----------------------- Receive Ports - PRBS Detection ---------------------
330 
    rxprbscntreset_in                       : in   std_logic;
331 
    rxprbserr_out                           : out  std_logic;
332 
    rxprbssel_in                            : in   std_logic_vector(2 downto 0);
333 
    ------------------- Receive Ports - RX Data Path interface -----------------
334 
    gtrxreset_in                            : in   std_logic;
335 
    rxpcsreset_in                           : in   std_logic;
336 
    rxpmareset_in                           : in   std_logic;
337 
    rxdata_out                              : out  std_logic_vector(31 downto 0);
338 
    rxoutclk_out                            : out  std_logic;
339 
    rxusrclk_in                             : in   std_logic;
340 
    rxusrclk2_in                            : in   std_logic;
341 
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
342 
    rxpolarity_in                           : in   std_logic;
343 
    ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
344 
    rxlpmhfhold_in                          : in   std_logic;
345 
    rxdfelpmreset_in                        : in   std_logic;
346 
    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
347 
    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
348 
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
349 
    gtxrxn_in                               : in   std_logic;
350 
    gtxrxp_in                               : in   std_logic;
351 
    rxlpmlfhold_in                          : in   std_logic;
352 
    rxlpmen_in                              : in   std_logic;
353 
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
354 
    rxbufreset_in                           : in   std_logic;
355 
    rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
356 
    ------------------------ Receive Ports - RX PLL Ports ----------------------
357 
    rxresetdone_out                         : out  std_logic;
358 
    ------------------------------- Transmit Ports -----------------------------
359 
    txpostcursor_in                         : in   std_logic_vector(4 downto 0);
360 
    txprecursor_in                          : in   std_logic_vector(4 downto 0);
361 
    txuserrdy_in                            : in   std_logic;
362 
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
363 
    txcharisk_in                            : in   std_logic_vector(3 downto 0);
364 
    ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
365 
    txdlyen_in                              : in   std_logic;
366 
    txdlysreset_in                          : in   std_logic;
367 
    txdlysresetdone_out                     : out  std_logic;
368 
    txphalign_in                            : in   std_logic;
369 
    txphaligndone_out                       : out  std_logic;
370 
    txphalignen_in                          : in   std_logic;
371 
    txphdlyreset_in                         : in   std_logic;
372 
    txphinit_in                             : in   std_logic;
373 
    txphinitdone_out                        : out  std_logic;
374 
    ------------------ Transmit Ports - TX Data Path interface -----------------
375 
    gttxreset_in                            : in   std_logic;
376 
    txdata_in                               : in   std_logic_vector(31 downto 0);
377 
    txoutclk_out                            : out  std_logic;
378 
    txoutclkfabric_out                      : out  std_logic;
379 
    txoutclkpcs_out                         : out  std_logic;
380 
    rxratedone_out                          : out  std_logic;
381 
    txusrclk_in                             : in   std_logic;
382 
    txusrclk2_in                            : in   std_logic;
383 
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
384 
    gtxtxn_out                              : out  std_logic;
385 
    gtxtxp_out                              : out  std_logic;
386 
    txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
387 
    txinhibit_in                            : in   std_logic;
388 
    ----------------------- Transmit Ports - TX PLL Ports ----------------------
389 
    txpcsreset_in                           : in   std_logic;
390 
    txpmareset_in                           : in   std_logic;
391 
    txresetdone_out                         : out  std_logic;
392 
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
393 
    txpolarity_in                           : in   std_logic;
394 
    --------------------- Transmit Ports - TX PRBS Generator -------------------
395 
    txprbsforceerr_in                       : in   std_logic;
396 
    txprbssel_in                            : in   std_logic_vector(2 downto 0);
397 
    ----------------- Transmit Ports - TX Ports for PCI Express ----------------
398 
    txelecidle_in                           : in   std_logic
399 
  );
400 
  end component;
401 
 
402 
  component rxaui_0_cl_clocking
403 
  port (
404 
    txoutclk             : in std_logic;
405 
    clk156               : out std_logic
406 
  );
407 
  end component;
408 
 
409 
  component rxaui_0_cl_resets
410 
  port (
411 
    reset                : in  std_logic;
412 
    clk156               : in  std_logic;
413 
    uclk_txlock          : in  std_logic;
414 
    reset156             : out std_logic
415 
  );
416 
  end component;
417 
 
418 
  component rxaui_0_gt_wrapper_tx_sync_manual
419 
  Generic (
420 
    NUMBER_OF_LANES      : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
421 
    MASTER_LANE_ID       : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
422 
  );
423 
 
424 
  Port (
425 
    STABLE_CLOCK         : in  std_logic;              --Stable Clock, either a stable clock from the PCB
426 
                                                       --or reference-clock present at startup.
427 
    RESET_PHALIGNMENT    : in  std_logic;
428 
    RUN_PHALIGNMENT      : in  std_logic;
429 
    PHASE_ALIGNMENT_DONE : out std_logic := '0';       -- Manual phase-alignment performed sucessfully
430 
    TXDLYSRESET          : out std_logic_vector(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
431 
    TXDLYSRESETDONE      : in  std_logic_vector(NUMBER_OF_LANES-1 downto 0);
432 
    TXPHINIT             : out std_logic_vector(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
433 
    TXPHINITDONE         : in  std_logic_vector(NUMBER_OF_LANES-1 downto 0);
434 
    TXPHALIGN            : out std_logic_vector(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
435 
    TXPHALIGNDONE        : in  std_logic_vector(NUMBER_OF_LANES-1 downto 0);
436 
    TXDLYEN              : out std_logic_vector(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
437 
   );
438 
   end component;
439 
 
440 
  component rxaui_0_reset_counter
441 
    port
442 
    (
443 
      clk                : in  std_logic;
444 
      done               : out std_logic
445 
    );
446 
  end component;
447 
 
448 
  component rxaui_0_ff_synchronizer
449 
    generic
450 
    (
451 
      C_NUM_SYNC_REGS    : integer := 3
452 
    );
453 
    port
454 
    (
455 
      clk                : in  std_logic;
456 
      data_in            : in std_logic;
457 
      data_out           : out std_logic
458 
    );
459 
  end component;
460 
 
461 
  component rxaui_0_pulse_stretcher
462 
    generic
463 
    (
464 
      C_NUM_SYNC_REGS    : integer := 3
465 
    );
466 
    port
467 
    (
468 
      clk                : in  std_logic;
469 
      data_in            : in std_logic;
470 
      data_out           : out std_logic
471 
    );
472 
  end component;
473 
 
474 
  component rxaui_0_gt_wrapper_tx_sync_manual_done_stretch
475 
  Port (
476 
  -- User Interface
477 
      USER_DONE          : out STD_LOGIC := '0';
478 
  -- GT Interface
479 
      GT_DONE            : in STD_LOGIC;
480 
  -- Clock and Reset
481 
      CLK                : in STD_LOGIC
482 
  );
483 
  end component;
484 
 
485 
  constant SYNC_COUNT_LENGTH   : integer := 16;
486 
  constant CHBOND_COUNT_LENGTH : integer := 16;
487 
 
488 
----------------------------------------------------------------------------
489 
-- Signal declarations.
490 
---------------------------------------------------------------------------
491 
  attribute ASYNC_REG : string;
492 
  attribute shreg_extract : string;
493 
  signal uclk_signal_detect                : std_logic_vector(1 downto 0);
494 
  signal core_mgt_rx_reset                 : std_logic_vector(1 downto 0);
495 
  signal mgt_txdata                        : std_logic_vector(63 downto 0);
496 
  signal mgt_txcharisk                     : std_logic_vector(7 downto 0);
497 
  signal mgt_rxdata                        : std_logic_vector(63 downto 0);
498 
  signal mgt_rxcharisk                     : std_logic_vector(7 downto 0);
499 
  signal mgt_enable_align                  : std_logic_vector(1 downto 0);
500 
  signal mgt_enchansync                    : std_logic;
501 
  signal mgt_rxdisperr                     : std_logic_vector(7 downto 0);
502 
  signal mgt_rxnotintable                  : std_logic_vector(7 downto 0);
503 
  signal uclk_mgt_rx_reset                 : std_logic;
504 
  signal uclk_mgt_tx_reset                 : std_logic;
505 
  signal mgt_codevalid                     : std_logic_vector(7 downto 0);
506 
  signal mgt_rxchariscomma                 : std_logic_vector(7 downto 0);
507 
  signal mgt_rxdata_reg                    : std_logic_vector(63 downto 0) := X"0000000000000000";
508 
  signal mgt_rxcharisk_reg                 : std_logic_vector(7 downto 0) := X"00";
509 
  signal mgt_rxnotintable_reg              : std_logic_vector(7 downto 0) := X"00";
510 
  signal mgt_rxdisperr_reg                 : std_logic_vector(7 downto 0) := X"00";
511 
  signal mgt_codecomma_reg                 : std_logic_vector(7 downto 0) := X"00";
512 
  signal uclk_mgt_rxbuf_reset              : std_logic_vector(1 downto 0);
513 
  signal mgt_tx_fault                      : std_logic_vector(1 downto 0);
514 
  signal mgt_loopback                      : std_logic;
515 
  signal mgt_loopback_r                    : std_logic;
516 
  signal uclk_mgt_loopback_falling         : std_logic;
517 
  signal mgt_powerdown                     : std_logic;
518 
  signal mgt_powerdown_2                   : std_logic_vector(1 downto 0);
519 
  signal mgt_powerdown_r                   : std_logic := '0';
520 
  signal uclk_mgt_powerdown_falling        : std_logic := '0';
521 
  signal uclk_plllocked                    : std_logic;
522 
  signal uclk_rxlock                       : std_logic_vector(1 downto 0);
523 
  signal uclk_txlock                       : std_logic;
524 
  signal uclk_mgt_rxbuferr                 : std_logic_vector(1 downto 0);
525 
  signal uclk_mgt_rxbufstatus              : std_logic_vector(5 downto 0);
526 
  signal uclk_mgt_rxbufstatus_reg          : std_logic_vector(5 downto 0) := (others => '0');
527 
  signal uclk_txresetdone_reg              : std_logic_vector(1 downto 0) := (others => '0');
528 
  signal loopback_int                      : std_logic_vector(2 downto 0);
529 
  signal mgt_txuserrdy                     : std_logic;
530 
  signal mgt_rxuserrdy                     : std_logic;
531 
  signal uclk_reset_count_done             : std_logic;
532 
  signal uclk_soft_reset                   : std_logic;
533 
  signal gt0_txoutclk_i                    : std_logic;
534 
  -- GT Control
535 
  signal gt0_loopback                      : std_logic_vector(2 downto 0);
536 
 
537 
  signal uclk_gt0_rxresetdone              : std_logic;
538 
  signal uclk_gt0_txresetdone              : std_logic;
539 
  -- Debug Wires
540 
 
541 
  -- TX Reset and Initialisation
542 
  signal gt0_gttxreset                     : std_logic;
543 
  signal gt0_txpmareset                    : std_logic;
544 
  signal gt0_txpcsreset                    : std_logic;
545 
  signal gt0_txuserrdy                     : std_logic;
546 
  -- RX Reset and Initialisation
547 
  signal gt0_gtrxreset                     : std_logic;
548 
  signal gt0_rxpmareset                    : std_logic;
549 
  signal gt0_rxpcsreset                    : std_logic;
550 
  signal gt0_rxbufreset                    : std_logic;
551 
  signal gt0_rxuserrdy                     : std_logic;
552 
 
553 
  signal gt0_rxchanbondseq                 : std_logic;
554 
  signal gt0_rxchanisaligned               : std_logic;
555 
  signal gt0_rxchanrealign                 : std_logic;
556 
  signal gt0_rxclkcorcnt                   : std_logic_vector(1 downto 0);
557 
  signal gt0_rxbyteisaligned               : std_logic;
558 
  signal gt0_rxbyterealign                 : std_logic;
559 
  signal gt0_rxcommadet                    : std_logic;
560 
  -------------------------- Channel Bonding Wires ---------------------------
561 
  signal gt0_rxchbondo_i                   : std_logic_vector(4 downto 0);
562 
  signal gt1_loopback                      : std_logic_vector(2 downto 0);
563 
 
564 
  signal uclk_gt1_rxresetdone              : std_logic;
565 
  signal uclk_gt1_txresetdone              : std_logic;
566 
  -- Debug Wires
567 
 
568 
  -- TX Reset and Initialisation
569 
  signal gt1_gttxreset                     : std_logic;
570 
  signal gt1_txpmareset                    : std_logic;
571 
  signal gt1_txpcsreset                    : std_logic;
572 
  signal gt1_txuserrdy                     : std_logic;
573 
  -- RX Reset and Initialisation
574 
  signal gt1_gtrxreset                     : std_logic;
575 
  signal gt1_rxpmareset                    : std_logic;
576 
  signal gt1_rxpcsreset                    : std_logic;
577 
  signal gt1_rxbufreset                    : std_logic;
578 
  signal gt1_rxuserrdy                     : std_logic;
579 
 
580 
  signal gt1_rxchanbondseq                 : std_logic;
581 
  signal gt1_rxchanisaligned               : std_logic;
582 
  signal gt1_rxchanrealign                 : std_logic;
583 
  signal gt1_rxclkcorcnt                   : std_logic_vector(1 downto 0);
584 
  signal gt1_rxbyteisaligned               : std_logic;
585 
  signal gt1_rxbyterealign                 : std_logic;
586 
  signal gt1_rxcommadet                    : std_logic;
587 
  -------------------------- Channel Bonding Wires ---------------------------
588 
  signal gt1_rxchbondo_i                   : std_logic_vector(4 downto 0);
589 
 
590 
  signal uclk_sync_status                  : std_logic_vector(3 downto 0);
591 
  signal uclk_align_status                 : std_logic;
592 
  signal gt_txdlysreset                    : std_logic_vector(1 downto 0);
593 
  signal gt_txdlysresetdone                : std_logic_vector(1 downto 0);
594 
  signal gt_txphaligndone                  : std_logic_vector(1 downto 0);
595 
 
596 
  signal  gt_txphinit                      : std_logic_vector(1 downto 0);
597 
  signal  gt_txphinitdone                  : std_logic_vector(1 downto 0);
598 
  signal  gt_txphalign                     : std_logic_vector(1 downto 0);
599 
  signal  gt_txdlyen                       : std_logic_vector(1 downto 0);
600 
  signal  uclk_txsync_start_phase_align    : std_logic := '0';
601 
  signal  uclk_phase_align_complete        : std_logic;
602 
 
603 
  signal uclk_chbond_counter               : unsigned(CHBOND_COUNT_LENGTH -1 downto 0) := (others => '0');
604 
  signal uclk_sync_counter                 : unsigned(SYNC_COUNT_LENGTH -1 downto 0)   := (others => '0');
605 
  signal dclk_reset_count_done             : std_logic := '0';
606 
  signal dclk_initial_reset                : std_logic := '0';
607 
  signal clk156                            : std_logic;
608 
  signal uclk_reset156                     : std_logic;
609 
 
610 
  signal rxprbs_in_use                     : std_logic := '0';
611 
 
612 
----------------------------------------------------------------------------
613 
-- Function declarations.
614 
---------------------------------------------------------------------------
615 
function IsBufError (bufStatus:std_logic_vector(2 downto 0)) return std_logic is
616 
  variable result : std_logic;
617 
begin
618 
  if bufStatus = "101" or bufStatus = "110" then
619 
    result := '1';
620 
  else
621 
    result := '0';
622 
  end if;
623 
  return result;
624 
end;
625 
 
626 
begin
627 
 
628 
  -- Assign output port from interal signals
629 
  debug <= uclk_align_status & uclk_sync_status & uclk_phase_align_complete;
630 
  clk156_out <= clk156;
631 
  clk156_lock <= uclk_txlock;
632 
 
633 
   rxaui_cl_clocking_i : rxaui_0_cl_clocking
634 
    port map(
635 
      txoutclk    => gt0_txoutclk_i,
636 
      clk156      => clk156
637 
    );
638 
 
639 
  rxaui_cl_resets_i : rxaui_0_cl_resets
640 
    port map(
641 
      reset       => reset,
642 
      clk156      => clk156,
643 
      uclk_txlock => uclk_txlock,
644 
      reset156    => uclk_reset156
645 
    );
646 
 
647 
 
648 
  -- Synchronize signal_detect to clk156
649 
  signal_detect_0_sync_i : rxaui_0_ff_synchronizer
650 
    generic map (
651 
      C_NUM_SYNC_REGS => 5)
652 
    port map (
653 
     clk      => clk156,
654 
     data_in  => signal_detect(0),
655 
     data_out => uclk_signal_detect(0)
656 
    );
657 
  signal_detect_1_sync_i : rxaui_0_ff_synchronizer
658 
    generic map (
659 
      C_NUM_SYNC_REGS => 5)
660 
    port map (
661 
     clk      => clk156,
662 
     data_in  => signal_detect(1),
663 
     data_out => uclk_signal_detect(1)
664 
    );
665 
 
666 
  rxaui_0_core : rxaui_v4_3_7_top
667 
    generic map (
668 
      c_family             => "kintex7",
669 
      c_rxaui_mode         => 0,
670 
      c_txdata_width       => 64,
671 
      c_rxdata_width       => 64,
672 
      c_has_mdio           => true
673 
    )
674 
    port map (
675 
      reset                => uclk_reset156,
676 
      xgmii_txd            => xgmii_txd,
677 
      xgmii_txc            => xgmii_txc,
678 
      xgmii_rxd            => xgmii_rxd,
679 
      xgmii_rxc            => xgmii_rxc,
680 
      usrclk               => clk156,
681 
      rxclk                => '0',
682 
      mgt_txdata           => mgt_txdata,
683 
      mgt_txcharisk        => mgt_txcharisk,
684 
      mgt_rxdata           => mgt_rxdata_reg,
685 
      mgt_rxcharisk        => mgt_rxcharisk_reg,
686 
      mgt_codevalid        => mgt_codevalid,
687 
      mgt_codecomma        => mgt_codecomma_reg,
688 
      mgt_enable_align     => mgt_enable_align,
689 
      mgt_enchansync       => mgt_enchansync,
690 
      mgt_rxlock           => uclk_rxlock,
691 
      mgt_loopback         => mgt_loopback,
692 
      mgt_powerdown        => mgt_powerdown,
693 
      mgt_tx_reset         => mgt_tx_fault,
694 
      mgt_rx_reset         => core_mgt_rx_reset,
695 
      soft_reset           => uclk_soft_reset,
696 
      signal_detect        => uclk_signal_detect,
697 
      align_status         => uclk_align_status,
698 
      sync_status          => uclk_sync_status,
699 
      mdc                  => mdc,
700 
      mdio_in              => mdio_in,
701 
      mdio_out             => mdio_out,
702 
      mdio_tri             => mdio_tri,
703 
      prtad                => prtad,
704 
      type_sel             => type_sel,
705 
      configuration_vector => (others => '0'),
706 
      status_vector        => open);
707 
 
708 
  ----------------------------------------------------------------------
709 
   -- Transceiver instances
710 
   gt0_wrapper_i : rxaui_0_gt_wrapper_GT
711 
    generic map (
712 
        GT_SIM_GTRESET_SPEEDUP      =>      "TRUE",
713 
        RX_DFE_KL_CFG2_IN           =>      X"3010D90C",
714 
        SIM_CPLLREFCLK_SEL          =>      "001",
715 
        PCS_RSVD_ATTR_IN            =>      X"000000000002",
716 
        PMA_RSV_IN                  =>      X"00018480"
717 
    )
718 
    port map (
719 
        --_____________________________________________________________________
720 
        --_____________________________________________________________________
721 
        --GT0
722 
        cpllrefclksel_in            =>      "001",
723 
        ---------------------------------- Channel ---------------------------------
724 
        qpllclk_in                  =>      qplloutclk,
725 
        qpllrefclk_in               =>      qplloutrefclk,
726 
        ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
727 
        drpaddr_in                  =>      gt0_drpaddr,
728 
        drpclk_in                   =>      dclk,
729 
        drpdi_in                    =>      gt0_drpdi,
730 
        drpdo_out                   =>      gt0_drpdo,
731 
        drpen_in                    =>      gt0_drpen,
732 
        drprdy_out                  =>      gt0_drprdy,
733 
        drpwe_in                    =>      gt0_drpwe,
734 
        ------------------------- Digital Monitor Ports --------------------------
735 
        dmonitorout_out             =>      gt0_dmonitorout_out,
736 
        ------------------------------- Eye Scan Ports -----------------------------
737 
        eyescandataerror_out        =>      gt0_eyescandataerror_out,
738 
        eyescanreset_in             =>      gt0_eyescanreset_in,
739 
        eyescantrigger_in           =>      gt0_eyescantrigger_in,
740 
        ------------------------- Receive Ports - CDR Ports ------------------------
741 
        rxcdrhold_in                =>      gt0_rxcdrhold_in,
742 
        ------------------------ Loopback and Powerdown Ports ----------------------
743 
        loopback_in                 =>      gt0_loopback,
744 
        rxpd_in                     =>      mgt_powerdown_2,
745 
        txpd_in                     =>      mgt_powerdown_2,
746 
        ------------------------------- Receive Ports ------------------------------
747 
        rxuserrdy_in                =>      mgt_rxuserrdy,
748 
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
749 
        rxchariscomma_out           =>      mgt_rxchariscomma(3 downto 0),
750 
        rxcharisk_out               =>      mgt_rxcharisk(3 downto 0),
751 
        rxdisperr_out               =>      mgt_rxdisperr(3 downto 0),
752 
        rxnotintable_out            =>      mgt_rxnotintable(3 downto 0),
753 
        ------------------- Receive Ports - Channel Bonding Ports ------------------
754 
        rxchanbondseq_out           =>      gt0_rxchanbondseq,
755 
        rxchbonden_in               =>      mgt_enchansync,
756 
        rxchbondi_in                =>      gt1_rxchbondo_i,
757 
        rxchbondlevel_in            =>      "000",
758 
        rxchbondmaster_in           =>      '0',
759 
        rxchbondo_out               =>      gt0_rxchbondo_i,
760 
        rxchbondslave_in            =>      '1',
761 
        ------------------- Receive Ports - Channel Bonding Ports  -----------------
762 
        rxchanisaligned_out         =>      gt0_rxchanisaligned,
763 
        rxchanrealign_out           =>      gt0_rxchanrealign,
764 
        ------------------- Receive Ports - Clock Correction Ports -----------------
765 
        rxclkcorcnt_out             =>      gt0_rxclkcorcnt,
766 
        --------------- Receive Ports - Comma Detection and Alignment --------------
767 
        rxbyteisaligned_out         =>      gt0_rxbyteisaligned,
768 
        rxbyterealign_out           =>      gt0_rxbyterealign,
769 
        rxcommadet_out              =>      gt0_rxcommadet,
770 
        rxmcommaalignen_in          =>      mgt_enable_align(0),
771 
        rxpcommaalignen_in          =>      mgt_enable_align(0),
772 
        ----------------------- Receive Ports - PRBS Detection ---------------------
773 
        rxprbscntreset_in           =>      gt0_rxprbscntreset_in,
774 
        rxprbserr_out               =>      gt0_rxprbserr_out,
775 
        rxprbssel_in                =>      gt0_rxprbssel_in,
776 
        ------------------- Receive Ports - RX Data Path interface -----------------
777 
        gtrxreset_in                =>      gt0_gtrxreset,
778 
        rxpcsreset_in               =>      gt0_rxpcsreset_in,
779 
        rxpmareset_in               =>      gt0_rxpmareset,
780 
        rxdata_out                  =>      mgt_rxdata(31 downto 0),
781 
        rxoutclk_out                =>      open,
782 
        rxusrclk_in                 =>      clk156,
783 
        rxusrclk2_in                =>      clk156,
784 
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
785 
        rxpolarity_in               =>      gt0_rxpolarity_in,
786 
        ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
787 
        rxlpmhfhold_in              =>      '0',
788 
        rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
789 
        rxmonitorout_out            =>      gt0_rxmonitorout_out,
790 
        rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
791 
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
792 
        gtxrxn_in                   =>      rxaui_rx_l0_n,
793 
        gtxrxp_in                   =>      rxaui_rx_l0_p,
794 
        rxlpmen_in                  =>      gt0_rxlpmen_in,
795 
        rxlpmlfhold_in              =>      '0',
796 
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
797 
        rxbufreset_in               =>      gt0_rxbufreset,
798 
        rxbufstatus_out             =>      uclk_mgt_rxbufstatus(2 downto 0),
799 
        ------------------------ Receive Ports - RX PLL Ports ----------------------
800 
        rxresetdone_out             =>      uclk_gt0_rxresetdone,
801 
        ------------------------------- Transmit Ports -----------------------------
802 
        txprecursor_in              =>      gt0_txprecursor_in,
803 
        txpostcursor_in             =>      gt0_txpostcursor_in,
804 
        txuserrdy_in                =>      mgt_txuserrdy,
805 
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
806 
        txcharisk_in                =>      mgt_txcharisk(3 downto 0),
807 
        ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
808 
 
809 
        txdlyen_in                  =>      gt_txdlyen(0),
810 
        txdlysreset_in              =>      gt_txdlysreset(0),
811 
        txdlysresetdone_out         =>      gt_txdlysresetdone(0),
812 
        txphalign_in                =>      gt_txphalign(0),
813 
        txphaligndone_out           =>      gt_txphaligndone(0),
814 
        txphalignen_in              =>      '1',
815 
        txphdlyreset_in             =>      '0',
816 
        txphinit_in                 =>      gt_txphinit(0),
817 
        txphinitdone_out            =>      gt_txphinitdone(0),
818 
 
819 
        ------------------ Transmit Ports - TX Data Path interface -----------------
820 
        gttxreset_in                =>      uclk_mgt_tx_reset,
821 
        txdata_in                   =>      mgt_txdata(31 downto 0),
822 
        txoutclk_out                =>      gt0_txoutclk_i,
823 
        txoutclkfabric_out          =>      open,
824 
        txoutclkpcs_out             =>      open,
825 
        rxratedone_out              =>      open,
826 
        txusrclk_in                 =>      clk156,
827 
        txusrclk2_in                =>      clk156,
828 
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
829 
        gtxtxn_out                  =>      rxaui_tx_l0_n,
830 
        gtxtxp_out                  =>      rxaui_tx_l0_p,
831 
        txdiffctrl_in               =>      gt0_txdiffctrl_in,
832 
        txinhibit_in                =>      gt0_txinhibit_in,
833 
        ----------------------- Transmit Ports - TX PLL Ports ----------------------
834 
        txpcsreset_in               =>      gt0_txpcsreset_in,
835 
        txpmareset_in               =>      gt0_txpmareset_in,
836 
        txresetdone_out             =>      uclk_gt0_txresetdone,
837 
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
838 
        txpolarity_in              =>       gt0_txpolarity_in,
839 
        --------------------- Transmit Ports - TX PRBS Generator -------------------
840 
        txprbsforceerr_in           =>      gt0_txprbsforceerr_in,
841 
        txprbssel_in                =>      gt0_txprbssel_in,
842 
        ----------------- Transmit Ports - TX Ports for PCI Express ----------------
843 
        rxrate_in                   =>      gt0_rxrate_in,
844 
        txelecidle_in               =>      mgt_powerdown_r
845 
    );
846 
 
847 
   gt1_wrapper_i : rxaui_0_gt_wrapper_GT
848 
    generic map (
849 
        GT_SIM_GTRESET_SPEEDUP      =>      "TRUE",
850 
        RX_DFE_KL_CFG2_IN           =>      X"3010D90C",
851 
        SIM_CPLLREFCLK_SEL          =>      "001",
852 
        PCS_RSVD_ATTR_IN            =>      X"000000000002",
853 
        PMA_RSV_IN                  =>      X"00018480"
854 
    )
855 
    port map (
856 
        --_____________________________________________________________________
857 
        --_____________________________________________________________________
858 
        --GT1
859 
        cpllrefclksel_in            =>      "001",
860 
        ---------------------------------- Channel ---------------------------------
861 
        qpllclk_in                  =>      qplloutclk,
862 
        qpllrefclk_in               =>      qplloutrefclk,
863 
        ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
864 
        drpaddr_in                  =>      gt1_drpaddr,
865 
        drpclk_in                   =>      dclk,
866 
        drpdi_in                    =>      gt1_drpdi,
867 
        drpdo_out                   =>      gt1_drpdo,
868 
        drpen_in                    =>      gt1_drpen,
869 
        drprdy_out                  =>      gt1_drprdy,
870 
        drpwe_in                    =>      gt1_drpwe,
871 
        ------------------------- Digital Monitor Ports --------------------------
872 
        dmonitorout_out             =>      gt1_dmonitorout_out,
873 
        ------------------------------- Eye Scan Ports -----------------------------
874 
        eyescandataerror_out        =>      gt1_eyescandataerror_out,
875 
        eyescanreset_in             =>      gt1_eyescanreset_in,
876 
        eyescantrigger_in           =>      gt1_eyescantrigger_in,
877 
        ------------------------- Receive Ports - CDR Ports ------------------------
878 
        rxcdrhold_in                =>      gt1_rxcdrhold_in,
879 
        ------------------------ Loopback and Powerdown Ports ----------------------
880 
        loopback_in                 =>      gt1_loopback,
881 
        rxpd_in                     =>      mgt_powerdown_2,
882 
        txpd_in                     =>      mgt_powerdown_2,
883 
        ------------------------------- Receive Ports ------------------------------
884 
        rxuserrdy_in                =>      mgt_rxuserrdy,
885 
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
886 
        rxchariscomma_out           =>      mgt_rxchariscomma(7 downto 4),
887 
        rxcharisk_out               =>      mgt_rxcharisk(7 downto 4),
888 
        rxdisperr_out               =>      mgt_rxdisperr(7 downto 4),
889 
        rxnotintable_out            =>      mgt_rxnotintable(7 downto 4),
890 
        ------------------- Receive Ports - Channel Bonding Ports ------------------
891 
        rxchanbondseq_out           =>      gt1_rxchanbondseq,
892 
        rxchbonden_in               =>      mgt_enchansync,
893 
        rxchbondi_in                =>      (others => '0'),
894 
        rxchbondlevel_in            =>      "001",
895 
        rxchbondmaster_in           =>      '1',
896 
        rxchbondo_out               =>      gt1_rxchbondo_i,
897 
        rxchbondslave_in            =>      '0',
898 
        ------------------- Receive Ports - Channel Bonding Ports  -----------------
899 
        rxchanisaligned_out         =>      gt1_rxchanisaligned,
900 
        rxchanrealign_out           =>      gt1_rxchanrealign,
901 
        ------------------- Receive Ports - Clock Correction Ports -----------------
902 
        rxclkcorcnt_out             =>      gt1_rxclkcorcnt,
903 
        --------------- Receive Ports - Comma Detection and Alignment --------------
904 
        rxbyteisaligned_out         =>      gt1_rxbyteisaligned,
905 
        rxbyterealign_out           =>      gt1_rxbyterealign,
906 
        rxcommadet_out              =>      gt1_rxcommadet,
907 
        rxmcommaalignen_in          =>      mgt_enable_align(1),
908 
        rxpcommaalignen_in          =>      mgt_enable_align(1),
909 
        ----------------------- Receive Ports - PRBS Detection ---------------------
910 
        rxprbscntreset_in           =>      gt1_rxprbscntreset_in,
911 
        rxprbserr_out               =>      gt1_rxprbserr_out,
912 
        rxprbssel_in                =>      gt1_rxprbssel_in,
913 
        ------------------- Receive Ports - RX Data Path interface -----------------
914 
        gtrxreset_in                =>      gt1_gtrxreset,
915 
        rxpcsreset_in               =>      gt1_rxpcsreset_in,
916 
        rxpmareset_in               =>      gt1_rxpmareset,
917 
        rxdata_out                  =>      mgt_rxdata(63 downto 32),
918 
        rxoutclk_out                =>      open,
919 
        rxusrclk_in                 =>      clk156,
920 
        rxusrclk2_in                =>      clk156,
921 
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
922 
        rxpolarity_in               =>      gt1_rxpolarity_in,
923 
        ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
924 
        rxlpmhfhold_in              =>      '0',
925 
        rxdfelpmreset_in            =>      gt1_rxdfelpmreset_in,
926 
        rxmonitorout_out            =>      gt1_rxmonitorout_out,
927 
        rxmonitorsel_in             =>      gt1_rxmonitorsel_in,
928 
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
929 
        gtxrxn_in                   =>      rxaui_rx_l1_n,
930 
        gtxrxp_in                   =>      rxaui_rx_l1_p,
931 
 
932 
        rxlpmen_in                  =>      gt1_rxlpmen_in,
933 
        rxlpmlfhold_in              =>      '0',
934 
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
935 
        rxbufreset_in               =>      gt1_rxbufreset,
936 
        rxbufstatus_out             =>      uclk_mgt_rxbufstatus(5 downto 3),
937 
        ------------------------ Receive Ports - RX PLL Ports ----------------------
938 
        rxresetdone_out             =>      uclk_gt1_rxresetdone,
939 
        ------------------------------- Transmit Ports -----------------------------
940 
        txprecursor_in              =>      gt1_txprecursor_in,
941 
        txpostcursor_in             =>      gt1_txpostcursor_in,
942 
        txuserrdy_in                =>      mgt_txuserrdy,
943 
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
944 
        txcharisk_in                =>      mgt_txcharisk(7 downto 4),
945 
        ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
946 
        txdlyen_in                  =>      gt_txdlyen(1),
947 
        txdlysreset_in              =>      gt_txdlysreset(1),
948 
        txdlysresetdone_out         =>      gt_txdlysresetdone(1),
949 
        txphalign_in                =>      gt_txphalign(1),
950 
        txphaligndone_out           =>      gt_txphaligndone(1),
951 
        txphalignen_in              =>      '1',
952 
        txphdlyreset_in             =>      '0',
953 
        txphinit_in                 =>      gt_txphinit(1),
954 
        txphinitdone_out            =>      gt_txphinitdone(1),
955 
 
956 
        ------------------ Transmit Ports - TX Data Path interface -----------------
957 
        gttxreset_in                =>      uclk_mgt_tx_reset,
958 
        txdata_in                   =>      mgt_txdata(63 downto 32),
959 
        txoutclk_out                =>      open,
960 
        txoutclkfabric_out          =>      open,
961 
        txoutclkpcs_out             =>      open,
962 
        rxratedone_out              =>      open,
963 
        txusrclk_in                 =>      clk156,
964 
        txusrclk2_in                =>      clk156,
965 
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
966 
        gtxtxn_out                  =>      rxaui_tx_l1_n,
967 
        gtxtxp_out                  =>      rxaui_tx_l1_p,
968 
        txdiffctrl_in               =>      gt1_txdiffctrl_in,
969 
        txinhibit_in                =>      gt1_txinhibit_in,
970 
        ----------------------- Transmit Ports - TX PLL Ports ----------------------
971 
        txpcsreset_in               =>      gt1_txpcsreset_in,
972 
        txpmareset_in               =>      gt1_txpmareset_in,
973 
        txresetdone_out             =>      uclk_gt1_txresetdone,
974 
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
975 
        txpolarity_in               =>      gt1_txpolarity_in,
976 
        --------------------- Transmit Ports - TX PRBS Generator -------------------
977 
        txprbsforceerr_in           =>      gt1_txprbsforceerr_in,
978 
        txprbssel_in                =>      gt1_txprbssel_in,
979 
        ----------------- Transmit Ports - TX Ports for PCI Express ----------------
980 
        rxrate_in                   =>      gt1_rxrate_in,
981 
        txelecidle_in               =>      mgt_powerdown_r
982 
  );
983 
 
984 
  gt0_loopback             <= loopback_int or gt0_loopback_in;
985 
  gt0_rxresetdone_out      <= uclk_gt0_rxresetdone;
986 
  gt0_txresetdone_out      <= uclk_gt0_txresetdone;
987 
  gt0_rxdisperr_out        <= mgt_rxdisperr(3 downto 0);
988 
  gt0_rxnotintable_out     <= mgt_rxnotintable(3 downto 0);
989 
  gt0_rxcommadet_out       <= gt0_rxcommadet;
990 
  gt0_rxbufstatus_out      <= uclk_mgt_rxbufstatus(2 downto 0);
991 
 
992 
  gt0_txphaligndone_out   <= gt_txphaligndone(0);
993 
  gt0_txphinitdone_out    <= gt_txphinitdone(0);
994 
  gt0_txdlysresetdone_out <= gt_txdlysresetdone(0);
995 
 
996 
  gt_qplllock_out               <= uclk_plllocked;
997 
 
998 
  gt0_gttxreset  <= uclk_mgt_tx_reset;
999 
  gt0_txpmareset <= gt0_txpmareset_in;
1000 
  gt0_txpcsreset <= gt0_txpcsreset_in;
1001 
  gt0_txuserrdy  <= mgt_txuserrdy;
1002 
 
1003 
  gt0_gtrxreset  <= uclk_mgt_rx_reset;
1004 
  gt0_rxbufreset <= uclk_mgt_rxbuf_reset(0);
1005 
 
1006 
  -- Synchronize the rxpmareset signal
1007 
  rxpmareset_sync0_i : rxaui_0_ff_synchronizer
1008 
    generic map (
1009 
      C_NUM_SYNC_REGS => 5)
1010 
    port map (
1011 
      clk      => dclk,
1012 
      data_in  => gt0_rxpmareset_in,
1013 
      data_out => gt0_rxpmareset
1014 
    );
1015 
 
1016 
  gt0_rxpcsreset <= gt0_rxpcsreset_in;
1017 
  gt0_rxuserrdy  <= mgt_rxuserrdy;
1018 
  gt1_loopback             <= loopback_int or gt1_loopback_in;
1019 
  gt1_rxresetdone_out      <= uclk_gt1_rxresetdone;
1020 
  gt1_txresetdone_out      <= uclk_gt1_txresetdone;
1021 
  gt1_rxdisperr_out        <= mgt_rxdisperr(7 downto 4);
1022 
  gt1_rxnotintable_out     <= mgt_rxnotintable(7 downto 4);
1023 
  gt1_rxcommadet_out       <= gt1_rxcommadet;
1024 
  gt1_rxbufstatus_out      <= uclk_mgt_rxbufstatus(5 downto 3);
1025 
 
1026 
  gt1_txphaligndone_out   <= gt_txphaligndone(1);
1027 
  gt1_txphinitdone_out    <= gt_txphinitdone(1);
1028 
  gt1_txdlysresetdone_out <= gt_txdlysresetdone(1);
1029 
 
1030 
  gt_qplllock_out               <= uclk_plllocked;
1031 
 
1032 
  gt1_gttxreset  <= uclk_mgt_tx_reset;
1033 
  gt1_txpmareset <= gt1_txpmareset_in;
1034 
  gt1_txpcsreset <= gt1_txpcsreset_in;
1035 
  gt1_txuserrdy  <= mgt_txuserrdy;
1036 
 
1037 
  gt1_gtrxreset  <= uclk_mgt_rx_reset;
1038 
  gt1_rxbufreset <= uclk_mgt_rxbuf_reset(1);
1039 
 
1040 
  -- Synchronize the rxpmareset signal
1041 
  rxpmareset_sync1_i : rxaui_0_ff_synchronizer
1042 
    generic map (
1043 
      C_NUM_SYNC_REGS => 5)
1044 
    port map (
1045 
      clk      => dclk,
1046 
      data_in  => gt1_rxpmareset_in,
1047 
      data_out => gt1_rxpmareset
1048 
    );
1049 
 
1050 
  gt1_rxpcsreset <= gt1_rxpcsreset_in;
1051 
  gt1_rxuserrdy  <= mgt_rxuserrdy;
1052 
 
1053 
  mgt_codevalid   <= not (mgt_rxnotintable_reg or mgt_rxdisperr_reg);
1054 
 
1055 
  -- The Actual GT Loopback is can be set by the external gt_control port
1056 
  -- logical OR this. The user should not drive both the XAUI Loopback
1057 
  -- and gt_control ports simultaneously
1058 
  loopback_int    <= "010" when mgt_loopback_r = '1' else "000";
1059 
 
1060 
  mgt_powerdown_2 <= mgt_powerdown & mgt_powerdown;
1061 
  mgt_txuserrdy   <= uclk_txlock;
1062 
  mgt_rxuserrdy   <= uclk_txlock;
1063 
 
1064 
 
1065 
  -- Synchronize the PLL Locked signal
1066 
  plllocked_sync_i : rxaui_0_ff_synchronizer
1067 
    generic map (
1068 
      C_NUM_SYNC_REGS => 5)
1069 
    port map (
1070 
     clk      => clk156,
1071 
     data_in  => qplllock,
1072 
     data_out => uclk_plllocked
1073 
    );
1074 
 
1075 
 
1076 
 -- Synchronize the dclk_reset_count_done signal to clk156
1077 
  reset_count_done_sync_i : rxaui_0_ff_synchronizer
1078 
    generic map (
1079 
      C_NUM_SYNC_REGS => 5)
1080 
    port map (
1081 
     clk      => clk156,
1082 
     data_in  => dclk_reset_count_done,
1083 
     data_out => uclk_reset_count_done
1084 
    );
1085 
 
1086 
 
1087 
  process(clk156) begin
1088 
    if rising_edge(clk156) then
1089 
      core_mgt_rx_reset(0) <= not uclk_gt0_rxresetdone;
1090 
      core_mgt_rx_reset(1) <= not uclk_gt1_rxresetdone;
1091 
    end if;
1092 
  end process;
1093 
 
1094 
  -- Detect falling edge of mgt_powerdown and mgt_loopback
1095 
  p_gt_r : process(clk156)
1096 
  begin
1097 
    if rising_edge(clk156) then
1098 
      mgt_powerdown_r <= mgt_powerdown;
1099 
      mgt_loopback_r  <= mgt_loopback;
1100 
    end if;
1101 
  end process;
1102 
 
1103 
  p_powerdown_falling : process(clk156)
1104 
  begin
1105 
    if rising_edge(clk156) then
1106 
      if mgt_powerdown_r = '1' and mgt_powerdown = '0' then
1107 
        uclk_mgt_powerdown_falling <= '1';
1108 
      else
1109 
        uclk_mgt_powerdown_falling <= '0';
1110 
      end if;
1111 
    end if;
1112 
  end process;
1113 
 
1114 
  p_loopback_falling : process(clk156)
1115 
  begin
1116 
    if rising_edge(clk156) then
1117 
      if mgt_loopback_r = '1' and mgt_loopback = '0' then
1118 
        uclk_mgt_loopback_falling <= '1';
1119 
      else
1120 
        uclk_mgt_loopback_falling <= '0';
1121 
      end if;
1122 
    end if;
1123 
  end process;
1124 
 
1125 
  RXBUFERR_P: process (uclk_mgt_rxbufstatus_reg)
1126 
  begin
1127 
    for i in 0 to 1 loop
1128 
      uclk_mgt_rxbuferr(i) <= IsBufError(uclk_mgt_rxbufstatus_reg(i*3+2 downto i*3));
1129 
    end loop;
1130 
  end process;
1131 
 
1132 
  -- chbond counter. Resets the GTX RX Buffers if the core fails to align due
1133 
  -- to extra skew introduced by the buffers.
1134 
  process (clk156) begin
1135 
    if rising_edge(clk156) then
1136 
      if ((uclk_chbond_counter(CHBOND_COUNT_LENGTH-1) = '1') or (uclk_align_status = '1') or (rxprbs_in_use = '1')) then
1137 
        uclk_chbond_counter <= (others => '0');
1138 
      elsif (uclk_sync_status = "1111") then
1139 
        uclk_chbond_counter <= uclk_chbond_counter + 1;
1140 
      else
1141 
        uclk_chbond_counter <= (others => '0');
1142 
      end if;
1143 
    end if;
1144 
  end process;
1145 
 
1146 
  -- Detect when the Rx PRBS is in use.  When it is, auto-generated periodic uclk_sync_counter
1147 
  -- and uclk_cbm_rx_reset resets will be inhibited
1148 
  process (clk156) begin
1149 
    if rising_edge(clk156) then
1150 
      if (gt0_rxprbssel_in  /= "000" or gt1_rxprbssel_in  /= "000") then
1151 
        rxprbs_in_use <= '1';
1152 
      else
1153 
        rxprbs_in_use <= '0';
1154 
      end if;
1155 
    end if;
1156 
  end process;
1157 
 
1158 
  -- sync timeout counter. GTX requires a reset if the far end powers down.
1159 
  process (clk156) begin
1160 
    if rising_edge(clk156) then
1161 
      if (uclk_sync_counter(SYNC_COUNT_LENGTH-1) = '1' or mgt_powerdown = '1' or rxprbs_in_use = '1') then
1162 
        uclk_sync_counter <= (others => '0');
1163 
      elsif (uclk_sync_status /= "1111") then
1164 
        uclk_sync_counter <= uclk_sync_counter + 1;
1165 
      else
1166 
        uclk_sync_counter <= (others => '0');
1167 
      end if;
1168 
    end if;
1169 
  end process;
1170 
 
1171 
   -- reset logic
1172 
  uclk_txlock <= uclk_plllocked;
1173 
  uclk_rxlock <= "11" when uclk_txlock = '1' else "00";
1174 
  mgt_tx_fault <= "11" when uclk_phase_align_complete = '0' else "00";
1175 
 
1176 
  process (clk156)
1177 
  begin
1178 
    if rising_edge(clk156) then
1179 
    uclk_mgt_rx_reset <= (uclk_soft_reset or uclk_reset156 or (not uclk_txlock) or uclk_mgt_powerdown_falling or
1180 
                          uclk_mgt_loopback_falling or uclk_sync_counter(SYNC_COUNT_LENGTH-1)) and uclk_reset_count_done;
1181 
    uclk_mgt_tx_reset <= (uclk_soft_reset or uclk_reset156 or (not uclk_txlock) or uclk_mgt_powerdown_falling) and
1182 
                          uclk_reset_count_done;
1183 
    end if;
1184 
  end process;
1185 
 
1186 
  -- reset the rx side when the buffer overflows / underflows
1187 
  process (clk156)
1188 
  begin
1189 
    if rising_edge(clk156) then
1190 
      if (uclk_mgt_rxbuferr /= "00") or (uclk_chbond_counter(CHBOND_COUNT_LENGTH-1) = '1') then
1191 
        uclk_mgt_rxbuf_reset <= "11";
1192 
      else
1193 
        uclk_mgt_rxbuf_reset <= "00";
1194 
      end if;
1195 
    end if;
1196 
  end process;
1197 
 
1198 
  p_mgt_reg : process(clk156)
1199 
  begin
1200 
    if rising_edge(clk156) then
1201 
        mgt_rxdata_reg          <= mgt_rxdata;
1202 
        mgt_rxcharisk_reg       <= mgt_rxcharisk;
1203 
        mgt_rxnotintable_reg    <= mgt_rxnotintable;
1204 
        mgt_rxdisperr_reg       <= mgt_rxdisperr;
1205 
        mgt_codecomma_reg       <= mgt_rxchariscomma;
1206 
        uclk_mgt_rxbufstatus_reg <= uclk_mgt_rxbufstatus;
1207 
        uclk_txresetdone_reg(0) <= uclk_gt0_txresetdone;
1208 
        uclk_txresetdone_reg(1) <= uclk_gt1_txresetdone;
1209 
    end if;
1210 
  end process p_mgt_reg;
1211 
 
1212 
  reset_counter_i : rxaui_0_reset_counter
1213 
  port map (
1214 
    clk           => dclk,
1215 
    done          => dclk_reset_count_done);
1216 
 
1217 
    --------------------------- TX Buffer Bypass Logic --------------------
1218 
    -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
1219 
 
1220 
  process (clk156) begin
1221 
    if (rising_edge(clk156)) then
1222 
      if (uclk_reset_count_done = '1') then
1223 
        if (uclk_txresetdone_reg = "11") then
1224 
          uclk_txsync_start_phase_align <= '1';
1225 
        else
1226 
          uclk_txsync_start_phase_align <= '0';
1227 
        end if;
1228 
      end if;
1229 
    end if;
1230 
  end process;
1231 
 
1232 
  txsync_i : rxaui_0_gt_wrapper_tx_sync_manual
1233 
  generic map
1234 
  ( NUMBER_OF_LANES      => 2,
1235 
    MASTER_LANE_ID       => 0
1236 
   )
1237 
  port map
1238 
  (
1239 
    STABLE_CLOCK         => clk156,
1240 
    RESET_PHALIGNMENT    => uclk_mgt_tx_reset,
1241 
    RUN_PHALIGNMENT      => uclk_txsync_start_phase_align,
1242 
    PHASE_ALIGNMENT_DONE => uclk_phase_align_complete,
1243 
    TXDLYSRESET          => gt_txdlysreset,
1244 
    TXDLYSRESETDONE      => gt_txdlysresetdone,
1245 
    TXPHINIT             => gt_txphinit,
1246 
    TXPHINITDONE         => gt_txphinitdone,
1247 
    TXPHALIGN            => gt_txphalign,
1248 
    TXPHALIGNDONE        => gt_txphaligndone,
1249 
    TXDLYEN              => gt_txdlyen
1250 
  );
1251 
 
1252 
 
1253 
end wrapper;

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