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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [ip/] [rxaui_0/] [synth/] [rxaui_0_ooc.xdc] - Blame information for rev 4

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# This constraints file contains default clock frequencies to be used during creation of a
# Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified
# to match the target frequencies.
# This constraints file is not used in top-down/global synthesis (not the default flow of Vivado).
create_clock -period 10.00 [get_ports dclk]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports dclk]

Line No.	Rev	Author	Line
1	4	DFC	`# This constraints file contains default clock frequencies to be used during creation of a`
2			`# Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified`
3			`# to match the target frequencies.`
4			`# This constraints file is not used in top-down/global synthesis (not the default flow of Vivado).`
5			`create_clock -period 10.00 [get_ports dclk]`
6			`set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports dclk]`

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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [ip/] [rxaui_0/] [synth/] [rxaui_0_ooc.xdc] - Blame information for rev 4