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-------------------------------------------------------------------------------

-- Title      : Reset Counter

-------------------------------------------------------------------------------

-- File       : rxaui_0_reset_counter.vhd

-------------------------------------------------------------------------------

-- Description: This module counts for a minimum of 500ns after configuration,

--              then raises the 'done' flag. This is based on a worst case

--              200MHz Clock which is the maximum DRP frequency for Artix-7

--             (Higher than Kintex-7 and Virtex-7)

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library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity rxaui_0_reset_counter is

    port (

      clk              : in  std_logic;

      done             : out std_logic

      );

end rxaui_0_reset_counter;

architecture rtl of rxaui_0_reset_counter is

  constant COUNT_WIDTH : integer := 8;

  signal count : unsigned (COUNT_WIDTH-1 downto 0) := (others => '0');

begin

  process(clk) begin

    if rising_edge(clk) then

      if (count(COUNT_WIDTH-1) = '0') then

        count <= count + 1;

      end if;

    end if;

  end process;

  done <= std_logic(count(COUNT_WIDTH -1));

end rtl;