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1 4 DFC 
-------------------------------------------------------------------------------
2 
-- Title      : Support Module
3 
-- Project    : RXAUI
4 
-------------------------------------------------------------------------------
5 
-- File       : rxaui_0_support.vhd
6 
-------------------------------------------------------------------------------
7 
-- Description: This module holds the support level for the RXAUI core
8 
--              This can be used as-is in a single core design, or adapted
9 
--              for use with multi-core implementations
10 
-------------------------------------------------------------------------------
11 
-- (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
12 
--
13 
-- This file contains confidential and proprietary information
14 
-- of Xilinx, Inc. and is protected under U.S. and
15 
-- international copyright and other intellectual property
16 
-- laws.
17 
--
18 
-- DISCLAIMER
19 
-- This disclaimer is not a license and does not grant any
20 
-- rights to the materials distributed herewith. Except as
21 
-- otherwise provided in a valid license issued to you by
22 
-- Xilinx, and to the maximum extent permitted by applicable
23 
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
24 
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
25 
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
26 
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
27 
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
28 
-- (2) Xilinx shall not be liable (whether in contract or tort,
29 
-- including negligence, or under any other theory of
30 
-- liability) for any loss or damage of any kind or nature
31 
-- related to, arising under or in connection with these
32 
-- materials, including for any direct, or any indirect,
33 
-- special, incidental, or consequential loss or damage
34 
-- (including loss of data, profits, goodwill, or any type of
35 
-- loss or damage suffered as a result of any action brought
36 
-- by a third party) even if such damage or loss was
37 
-- reasonably foreseeable or Xilinx had been advised of the
38 
-- possibility of the same.
39 
--
40 
-- CRITICAL APPLICATIONS
41 
-- Xilinx products are not designed or intended to be fail-
42 
-- safe, or for use in any application requiring fail-safe
43 
-- performance, such as life-support or safety devices or
44 
-- systems, Class III medical devices, nuclear facilities,
45 
-- applications related to the deployment of airbags, or any
46 
-- other applications that could lead to death, personal
47 
-- injury, or severe property or environmental damage
48 
-- (individually and collectively, "Critical
49 
-- Applications"). Customer assumes the sole risk and
50 
-- liability of any use of Xilinx products in Critical
51 
-- Applications, subject only to applicable laws and
52 
-- regulations governing limitations on product liability.
53 
--
54 
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
55 
-- PART OF THIS FILE AT ALL TIMES.
56 
 
57 
library ieee;
58 
use ieee.std_logic_1164.all;
59 
 
60 
entity rxaui_0_support is
61 
    port (
62 
      reset                    : in  std_logic;                     -- Asynchronous Reset
63 
      dclk                     : in  std_logic;                     -- Stable Clock
64 
      clk156_out               : out std_logic;                     -- 156.25MHz output clock derived from the GT
65 
      clk156_lock              : out  std_logic;                    -- 156.25MHz clock ready for use
66 
      qplloutclk_out           : out std_logic;                     -- Clock from common PLL
67 
      qplllock_out             : out std_logic;                     -- Lock from common PLL
68 
      qplloutrefclk_out        : out std_logic;                     -- Refclk from common PLL
69 
      refclk_out               : out std_logic;                     -- Refclk from differential GT clock buffer
70 
      refclk_p                 : in  std_logic;                     -- Refclk P - to differential GT clock buffer
71 
      refclk_n                 : in  std_logic;                     -- Refclk N - to differential GT clock buffer
72 
      xgmii_txd                : in  std_logic_vector(63 downto 0); -- XGMII Tx Data
73 
      xgmii_txc                : in  std_logic_vector(7 downto 0);  -- XGMII Tx Control
74 
      xgmii_rxd                : out std_logic_vector(63 downto 0); -- XGMII Rx Data
75 
      xgmii_rxc                : out std_logic_vector(7 downto 0);  -- XGMII Rx Control
76 
      rxaui_tx_l0_p            : out std_logic;                     -- GT0 Tx P
77 
      rxaui_tx_l0_n            : out std_logic;                     -- GT0 Tx N
78 
      rxaui_tx_l1_p            : out std_logic;                     -- GT1 Tx P
79 
      rxaui_tx_l1_n            : out std_logic;                     -- GT1 Tx P
80 
      rxaui_rx_l0_p            : in  std_logic;                     -- GT0 Rx P
81 
      rxaui_rx_l0_n            : in  std_logic;                     -- GT0 Rx N
82 
      rxaui_rx_l1_p            : in  std_logic;                     -- GT1 Rx P
83 
      rxaui_rx_l1_n            : in  std_logic;                     -- GT1 Rx N
84 
      signal_detect            : in  std_logic_vector(1 downto 0);  -- Signal detect from optics
85 
      debug                    : out std_logic_vector(5 downto 0);  -- Debug vector
86 
   -- GT Control Ports
87 
   -- The following signals are connected directly to/from the transceiver
88 
   -- DRP
89 
      gt0_drpaddr              : in  std_logic_vector(8 downto 0);
90 
      gt0_drpen                : in  std_logic;
91 
      gt0_drpdi                : in  std_logic_vector(15 downto 0);
92 
      gt0_drpdo                : out std_logic_vector(15 downto 0);
93 
      gt0_drprdy               : out std_logic;
94 
      gt0_drpwe                : in  std_logic;
95 
   -- TX Reset and Initialisation
96 
      gt0_txpmareset_in        : in std_logic;
97 
      gt0_txpcsreset_in        : in std_logic;
98 
      gt0_txresetdone_out      : out std_logic;
99 
   -- RX Reset and Initialisation
100 
      gt0_rxpmareset_in        : in std_logic;
101 
      gt0_rxpcsreset_in        : in std_logic;
102 
      gt0_rxresetdone_out      : out std_logic;
103 
   -- Clocking
104 
      gt0_rxbufstatus_out      : out std_logic_vector(2 downto 0);
105 
      gt0_txphaligndone_out    : out std_logic;
106 
      gt0_txphinitdone_out     : out std_logic;
107 
      gt0_txdlysresetdone_out  : out std_logic;
108 
      gt_qplllock_out                : out std_logic;
109 
   -- Signal Integrity adn Functionality
110 
   -- Eye Scan
111 
      gt0_eyescantrigger_in    : in  std_logic;
112 
      gt0_eyescanreset_in      : in  std_logic;
113 
      gt0_eyescandataerror_out : out std_logic;
114 
      gt0_rxrate_in            : in  std_logic_vector(2 downto 0);
115 
   -- Loopback
116 
      gt0_loopback_in          : in  std_logic_vector(2 downto 0);
117 
   -- Polarity
118 
      gt0_rxpolarity_in        : in  std_logic;
119 
      gt0_txpolarity_in        : in  std_logic;
120 
   -- RX Decision Feedback Equalizer(DFE)
121 
      gt0_rxlpmen_in           : in  std_logic;
122 
      gt0_rxdfelpmreset_in     : in  std_logic;
123 
      gt0_rxmonitorsel_in      : in  std_logic_vector(1 downto 0);
124 
      gt0_rxmonitorout_out     : out std_logic_vector(6 downto 0);
125 
   -- TX Driver
126 
      gt0_txpostcursor_in      : in  std_logic_vector(4 downto 0);
127 
      gt0_txprecursor_in       : in  std_logic_vector(4 downto 0);
128 
      gt0_txdiffctrl_in        : in  std_logic_vector(3 downto 0);
129 
      gt0_txinhibit_in         : in  std_logic;
130 
   -- PRBS
131 
      gt0_rxprbscntreset_in    : in  std_logic;
132 
      gt0_rxprbserr_out        : out std_logic;
133 
      gt0_rxprbssel_in         : in  std_logic_vector(2 downto 0);
134 
      gt0_txprbssel_in         : in  std_logic_vector(2 downto 0);
135 
      gt0_txprbsforceerr_in    : in  std_logic;
136 
 
137 
      gt0_rxcdrhold_in         : in  std_logic;
138 
      gt0_dmonitorout_out      : out std_logic_vector(7 downto 0);
139 
 
140 
   -- Status
141 
      gt0_rxdisperr_out        : out std_logic_vector(3 downto 0);
142 
      gt0_rxnotintable_out     : out std_logic_vector(3 downto 0);
143 
      gt0_rxcommadet_out       : out std_logic;
144 
   -- DRP
145 
      gt1_drpaddr              : in  std_logic_vector(8 downto 0);
146 
      gt1_drpen                : in  std_logic;
147 
      gt1_drpdi                : in  std_logic_vector(15 downto 0);
148 
      gt1_drpdo                : out std_logic_vector(15 downto 0);
149 
      gt1_drprdy               : out std_logic;
150 
      gt1_drpwe                : in  std_logic;
151 
   -- TX Reset and Initialisation
152 
      gt1_txpmareset_in        : in std_logic;
153 
      gt1_txpcsreset_in        : in std_logic;
154 
      gt1_txresetdone_out      : out std_logic;
155 
   -- RX Reset and Initialisation
156 
      gt1_rxpmareset_in        : in std_logic;
157 
      gt1_rxpcsreset_in        : in std_logic;
158 
      gt1_rxresetdone_out      : out std_logic;
159 
   -- Clocking
160 
      gt1_rxbufstatus_out      : out std_logic_vector(2 downto 0);
161 
      gt1_txphaligndone_out    : out std_logic;
162 
      gt1_txphinitdone_out     : out std_logic;
163 
      gt1_txdlysresetdone_out  : out std_logic;
164 
   -- Signal Integrity adn Functionality
165 
   -- Eye Scan
166 
      gt1_eyescantrigger_in    : in  std_logic;
167 
      gt1_eyescanreset_in      : in  std_logic;
168 
      gt1_eyescandataerror_out : out std_logic;
169 
      gt1_rxrate_in            : in  std_logic_vector(2 downto 0);
170 
   -- Loopback
171 
      gt1_loopback_in          : in  std_logic_vector(2 downto 0);
172 
   -- Polarity
173 
      gt1_rxpolarity_in        : in  std_logic;
174 
      gt1_txpolarity_in        : in  std_logic;
175 
   -- RX Decision Feedback Equalizer(DFE)
176 
      gt1_rxlpmen_in           : in  std_logic;
177 
      gt1_rxdfelpmreset_in     : in  std_logic;
178 
      gt1_rxmonitorsel_in      : in  std_logic_vector(1 downto 0);
179 
      gt1_rxmonitorout_out     : out std_logic_vector(6 downto 0);
180 
   -- TX Driver
181 
      gt1_txpostcursor_in      : in  std_logic_vector(4 downto 0);
182 
      gt1_txprecursor_in       : in  std_logic_vector(4 downto 0);
183 
      gt1_txdiffctrl_in        : in  std_logic_vector(3 downto 0);
184 
      gt1_txinhibit_in         : in  std_logic;
185 
   -- PRBS
186 
      gt1_rxprbscntreset_in    : in  std_logic;
187 
      gt1_rxprbserr_out        : out std_logic;
188 
      gt1_rxprbssel_in         : in  std_logic_vector(2 downto 0);
189 
      gt1_txprbssel_in         : in  std_logic_vector(2 downto 0);
190 
      gt1_txprbsforceerr_in    : in  std_logic;
191 
 
192 
      gt1_rxcdrhold_in         : in  std_logic;
193 
      gt1_dmonitorout_out      : out std_logic_vector(7 downto 0);
194 
 
195 
   -- Status
196 
      gt1_rxdisperr_out        : out std_logic_vector(3 downto 0);
197 
      gt1_rxnotintable_out     : out std_logic_vector(3 downto 0);
198 
      gt1_rxcommadet_out       : out std_logic;
199 
      mdc                      : in  std_logic;                    -- MDIO Clock
200 
      mdio_in                  : in  std_logic;                    -- MDIO input
201 
      mdio_out                 : out std_logic;                    -- MDIO Output
202 
      mdio_tri                 : out std_logic;                    -- MDIO tri-state enable
203 
      prtad                    : in  std_logic_vector(4 downto 0); -- MDIO PRTAD
204 
      type_sel                 : in  std_logic_vector(1 downto 0)  -- type_sel control
205 
);
206 
end rxaui_0_support;
207 
 
208 
library ieee;
209 
use ieee.numeric_std.all;
210 
 
211 
architecture wrapper of rxaui_0_support is
212 
 
213 
----------------------------------------------------------------------------
214 
-- Component Declarations
215 
----------------------------------------------------------------------------
216 
 
217 
 component rxaui_0_support_clocking is
218 
    port (
219 
      refclk_p                 : in  std_logic;
220 
      refclk_n                 : in  std_logic;
221 
      refclk                   : out std_logic
222 
      );
223 
 end component;
224 
 
225 
 component rxaui_0_support_resets is
226 
    port (
227 
      reset                    : in  std_logic;
228 
      dclk                     : in  std_logic;
229 
      common_pll_reset         : out std_logic
230 
      );
231 
 end component;
232 
 
233 
 component rxaui_0_gt_common_wrapper is
234 
   generic (
235 
    SIM_RESET_SPEEDUP          : string := "false" -- Set to "true" to speed up sim reset
236 
   );
237 
   port
238 
  (
239 
    GTREFCLK0_IN               : in std_logic;
240 
    QPLLLOCK_OUT               : out std_logic;
241 
    QPLLLOCKDETCLK_IN          : in std_logic;
242 
    QPLLOUTCLK_OUT             : out std_logic;
243 
    QPLLOUTREFCLK_OUT          : out std_logic;
244 
    QPLLREFCLKLOST_OUT         : out std_logic;
245 
    QPLLRESET_IN               : in std_logic
246 
  );
247 
 end component;
248 
 
249 
 component rxaui_0_block is
250 
    port (
251 
      reset                    : in  std_logic;
252 
      dclk                     : in  std_logic;
253 
      clk156_out               : out std_logic;
254 
      clk156_lock              : out  std_logic;
255 
      refclk                   : in  std_logic;
256 
      qplloutclk               : in  std_logic;
257 
      qplllock                 : in  std_logic;
258 
      qplloutrefclk            : in  std_logic;
259 
      xgmii_txd                : in  std_logic_vector(63 downto 0);
260 
      xgmii_txc                : in  std_logic_vector(7 downto 0);
261 
      xgmii_rxd                : out std_logic_vector(63 downto 0);
262 
      xgmii_rxc                : out std_logic_vector(7 downto 0);
263 
      rxaui_tx_l0_p            : out std_logic;
264 
      rxaui_tx_l0_n            : out std_logic;
265 
      rxaui_tx_l1_p            : out std_logic;
266 
      rxaui_tx_l1_n            : out std_logic;
267 
      rxaui_rx_l0_p            : in  std_logic;
268 
      rxaui_rx_l0_n            : in  std_logic;
269 
      rxaui_rx_l1_p            : in  std_logic;
270 
      rxaui_rx_l1_n            : in  std_logic;
271 
      signal_detect            : in  std_logic_vector(1 downto 0);
272 
      debug                    : out std_logic_vector(5 downto 0);
273 
   -- GT Control Ports
274 
   -- DRP
275 
      gt0_drpaddr              : in  std_logic_vector(8 downto 0);
276 
      gt0_drpen                : in  std_logic;
277 
      gt0_drpdi                : in  std_logic_vector(15 downto 0);
278 
      gt0_drpdo                : out std_logic_vector(15 downto 0);
279 
      gt0_drprdy               : out std_logic;
280 
      gt0_drpwe                : in  std_logic;
281 
   -- TX Reset and Initialisation
282 
      gt0_txpmareset_in        : in std_logic;
283 
      gt0_txpcsreset_in        : in std_logic;
284 
      gt0_txresetdone_out      : out std_logic;
285 
   -- RX Reset and Initialisation
286 
      gt0_rxpmareset_in        : in std_logic;
287 
      gt0_rxpcsreset_in        : in std_logic;
288 
      gt0_rxresetdone_out      : out std_logic;
289 
   -- Clocking
290 
      gt0_rxbufstatus_out      : out std_logic_vector(2 downto 0);
291 
      gt0_txphaligndone_out    : out std_logic;
292 
      gt0_txphinitdone_out     : out std_logic;
293 
      gt0_txdlysresetdone_out  : out std_logic;
294 
      gt_qplllock_out                : out std_logic;
295 
   -- Signal Integrity adn Functionality
296 
   -- Eye Scan
297 
      gt0_eyescantrigger_in    : in  std_logic;
298 
      gt0_eyescanreset_in      : in  std_logic;
299 
      gt0_eyescandataerror_out : out std_logic;
300 
      gt0_rxrate_in            : in  std_logic_vector(2 downto 0);
301 
   -- Loopback
302 
      gt0_loopback_in          : in  std_logic_vector(2 downto 0);
303 
   -- Polarity
304 
      gt0_rxpolarity_in        : in  std_logic;
305 
      gt0_txpolarity_in        : in  std_logic;
306 
   -- RX Decision Feedback Equalizer(DFE)
307 
      gt0_rxlpmen_in           : in  std_logic;
308 
      gt0_rxdfelpmreset_in     : in  std_logic;
309 
      gt0_rxmonitorsel_in      : in  std_logic_vector(1 downto 0);
310 
      gt0_rxmonitorout_out     : out std_logic_vector(6 downto 0);
311 
   -- TX Driver
312 
      gt0_txpostcursor_in      : in  std_logic_vector(4 downto 0);
313 
      gt0_txprecursor_in       : in  std_logic_vector(4 downto 0);
314 
      gt0_txdiffctrl_in        : in  std_logic_vector(3 downto 0);
315 
      gt0_txinhibit_in         : in  std_logic;
316 
   -- PRBS
317 
      gt0_rxprbscntreset_in    : in  std_logic;
318 
      gt0_rxprbserr_out        : out std_logic;
319 
      gt0_rxprbssel_in         : in  std_logic_vector(2 downto 0);
320 
      gt0_txprbssel_in         : in  std_logic_vector(2 downto 0);
321 
      gt0_txprbsforceerr_in    : in  std_logic;
322 
 
323 
      gt0_rxcdrhold_in         : in  std_logic;
324 
      gt0_dmonitorout_out      : out std_logic_vector(7 downto 0);
325 
 
326 
   -- Status
327 
      gt0_rxdisperr_out        : out std_logic_vector(3 downto 0);
328 
      gt0_rxnotintable_out     : out std_logic_vector(3 downto 0);
329 
      gt0_rxcommadet_out       : out std_logic;
330 
   -- DRP
331 
      gt1_drpaddr              : in  std_logic_vector(8 downto 0);
332 
      gt1_drpen                : in  std_logic;
333 
      gt1_drpdi                : in  std_logic_vector(15 downto 0);
334 
      gt1_drpdo                : out std_logic_vector(15 downto 0);
335 
      gt1_drprdy               : out std_logic;
336 
      gt1_drpwe                : in  std_logic;
337 
   -- TX Reset and Initialisation
338 
      gt1_txpmareset_in        : in std_logic;
339 
      gt1_txpcsreset_in        : in std_logic;
340 
      gt1_txresetdone_out      : out std_logic;
341 
   -- RX Reset and Initialisation
342 
      gt1_rxpmareset_in        : in std_logic;
343 
      gt1_rxpcsreset_in        : in std_logic;
344 
      gt1_rxresetdone_out      : out std_logic;
345 
   -- Clocking
346 
      gt1_rxbufstatus_out      : out std_logic_vector(2 downto 0);
347 
      gt1_txphaligndone_out    : out std_logic;
348 
      gt1_txphinitdone_out     : out std_logic;
349 
      gt1_txdlysresetdone_out  : out std_logic;
350 
   -- Signal Integrity adn Functionality
351 
   -- Eye Scan
352 
      gt1_eyescantrigger_in    : in  std_logic;
353 
      gt1_eyescanreset_in      : in  std_logic;
354 
      gt1_eyescandataerror_out : out std_logic;
355 
      gt1_rxrate_in            : in  std_logic_vector(2 downto 0);
356 
   -- Loopback
357 
      gt1_loopback_in          : in  std_logic_vector(2 downto 0);
358 
   -- Polarity
359 
      gt1_rxpolarity_in        : in  std_logic;
360 
      gt1_txpolarity_in        : in  std_logic;
361 
   -- RX Decision Feedback Equalizer(DFE)
362 
      gt1_rxlpmen_in           : in  std_logic;
363 
      gt1_rxdfelpmreset_in     : in  std_logic;
364 
      gt1_rxmonitorsel_in      : in  std_logic_vector(1 downto 0);
365 
      gt1_rxmonitorout_out     : out std_logic_vector(6 downto 0);
366 
   -- TX Driver
367 
      gt1_txpostcursor_in      : in  std_logic_vector(4 downto 0);
368 
      gt1_txprecursor_in       : in  std_logic_vector(4 downto 0);
369 
      gt1_txdiffctrl_in        : in  std_logic_vector(3 downto 0);
370 
      gt1_txinhibit_in         : in  std_logic;
371 
   -- PRBS
372 
      gt1_rxprbscntreset_in    : in  std_logic;
373 
      gt1_rxprbserr_out        : out std_logic;
374 
      gt1_rxprbssel_in         : in  std_logic_vector(2 downto 0);
375 
      gt1_txprbssel_in         : in  std_logic_vector(2 downto 0);
376 
      gt1_txprbsforceerr_in    : in  std_logic;
377 
 
378 
      gt1_rxcdrhold_in         : in  std_logic;
379 
      gt1_dmonitorout_out      : out std_logic_vector(7 downto 0);
380 
 
381 
   -- Status
382 
      gt1_rxdisperr_out        : out std_logic_vector(3 downto 0);
383 
      gt1_rxnotintable_out     : out std_logic_vector(3 downto 0);
384 
      gt1_rxcommadet_out       : out std_logic;
385 
      mdc                      : in  std_logic;
386 
      mdio_in                  : in  std_logic;
387 
      mdio_out                 : out std_logic;
388 
      mdio_tri                 : out std_logic;
389 
      prtad                    : in  std_logic_vector(4 downto 0);
390 
      type_sel                 : in  std_logic_vector(1 downto 0)
391 
);
392 
end component;
393 
 
394 
----------------------------------------------------------------------------
395 
-- Signal declarations.
396 
----------------------------------------------------------------------------
397 
  signal refclk                : std_logic;
398 
 
399 
  signal qplloutclk_i          : std_logic;
400 
  signal qplllock_i            : std_logic;
401 
  signal qplloutrefclk_i       : std_logic;
402 
  signal common_pll_reset_i    : std_logic;
403 
 
404 
begin
405 
 
406 
  rxaui_block_i : rxaui_0_block
407 
    port map (
408 
      reset                    => reset,
409 
      dclk                     => dclk,
410 
      clk156_out               => clk156_out,
411 
      clk156_lock              => clk156_lock,
412 
      refclk                   => refclk,
413 
      qplloutclk               => qplloutclk_i,
414 
      qplllock                 => qplllock_i,
415 
      qplloutrefclk            => qplloutrefclk_i,
416 
      xgmii_txd                => xgmii_txd,
417 
      xgmii_txc                => xgmii_txc,
418 
      xgmii_rxd                => xgmii_rxd,
419 
      xgmii_rxc                => xgmii_rxc,
420 
      rxaui_tx_l0_p            => rxaui_tx_l0_p,
421 
      rxaui_tx_l0_n            => rxaui_tx_l0_n,
422 
      rxaui_tx_l1_p            => rxaui_tx_l1_p,
423 
      rxaui_tx_l1_n            => rxaui_tx_l1_n,
424 
      rxaui_rx_l0_p            => rxaui_rx_l0_p,
425 
      rxaui_rx_l0_n            => rxaui_rx_l0_n,
426 
      rxaui_rx_l1_p            => rxaui_rx_l1_p,
427 
      rxaui_rx_l1_n            => rxaui_rx_l1_n,
428 
      signal_detect            => signal_detect,
429 
      debug                    => debug,
430 
   -- GT Control Ports
431 
   -- DRP
432 
      gt0_drpaddr              => gt0_drpaddr,
433 
      gt0_drpen                => gt0_drpen,
434 
      gt0_drpdi                => gt0_drpdi,
435 
      gt0_drpdo                => gt0_drpdo,
436 
      gt0_drprdy               => gt0_drprdy,
437 
      gt0_drpwe                => gt0_drpwe,
438 
   -- TX Reset and Initialisation
439 
      gt0_txpmareset_in        => gt0_txpmareset_in,
440 
      gt0_txpcsreset_in        => gt0_txpcsreset_in,
441 
      gt0_txresetdone_out      => gt0_txresetdone_out,
442 
   -- RX Reset and Initialisation
443 
      gt0_rxpmareset_in        => gt0_rxpmareset_in,
444 
      gt0_rxpcsreset_in        => gt0_rxpcsreset_in,
445 
      gt0_rxresetdone_out      => gt0_rxresetdone_out,
446 
   -- Clocking
447 
      gt0_rxbufstatus_out      => gt0_rxbufstatus_out,
448 
      gt0_txphaligndone_out    => gt0_txphaligndone_out,
449 
      gt0_txphinitdone_out     => gt0_txphinitdone_out,
450 
      gt0_txdlysresetdone_out  => gt0_txdlysresetdone_out,
451 
      gt_qplllock_out                => gt_qplllock_out,
452 
   -- Signal Integrity adn Functionality
453 
   -- Eye Scan
454 
      gt0_eyescantrigger_in    => gt0_eyescantrigger_in,
455 
      gt0_eyescanreset_in      => gt0_eyescanreset_in,
456 
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
457 
      gt0_rxrate_in            => gt0_rxrate_in,
458 
   -- Loopback
459 
      gt0_loopback_in          => gt0_loopback_in,
460 
   -- Polarity
461 
      gt0_rxpolarity_in        => gt0_rxpolarity_in,
462 
      gt0_txpolarity_in        => gt0_txpolarity_in,
463 
   -- RX Decision Feedback Equalizer(DFE)
464 
      gt0_rxlpmen_in           => gt0_rxlpmen_in,
465 
      gt0_rxdfelpmreset_in     => gt0_rxdfelpmreset_in,
466 
      gt0_rxmonitorsel_in      => gt0_rxmonitorsel_in,
467 
      gt0_rxmonitorout_out     => gt0_rxmonitorout_out,
468 
   -- TX Driver
469 
      gt0_txpostcursor_in      => gt0_txpostcursor_in,
470 
      gt0_txprecursor_in       => gt0_txprecursor_in,
471 
      gt0_txdiffctrl_in        => gt0_txdiffctrl_in,
472 
      gt0_txinhibit_in         => gt0_txinhibit_in,
473 
   -- PRBS
474 
      gt0_rxprbscntreset_in    => gt0_rxprbscntreset_in,
475 
      gt0_rxprbserr_out        => gt0_rxprbserr_out,
476 
      gt0_rxprbssel_in         => gt0_rxprbssel_in,
477 
      gt0_txprbssel_in         => gt0_txprbssel_in,
478 
      gt0_txprbsforceerr_in    => gt0_txprbsforceerr_in,
479 
 
480 
      gt0_rxcdrhold_in         => gt0_rxcdrhold_in,
481 
      gt0_dmonitorout_out      => gt0_dmonitorout_out,
482 
 
483 
   -- Status
484 
      gt0_rxdisperr_out        => gt0_rxdisperr_out,
485 
      gt0_rxnotintable_out     => gt0_rxnotintable_out,
486 
      gt0_rxcommadet_out       => gt0_rxcommadet_out,
487 
   -- DRP
488 
      gt1_drpaddr              => gt1_drpaddr,
489 
      gt1_drpen                => gt1_drpen,
490 
      gt1_drpdi                => gt1_drpdi,
491 
      gt1_drpdo                => gt1_drpdo,
492 
      gt1_drprdy               => gt1_drprdy,
493 
      gt1_drpwe                => gt1_drpwe,
494 
   -- TX Reset and Initialisation
495 
      gt1_txpmareset_in        => gt1_txpmareset_in,
496 
      gt1_txpcsreset_in        => gt1_txpcsreset_in,
497 
      gt1_txresetdone_out      => gt1_txresetdone_out,
498 
   -- RX Reset and Initialisation
499 
      gt1_rxpmareset_in        => gt1_rxpmareset_in,
500 
      gt1_rxpcsreset_in        => gt1_rxpcsreset_in,
501 
      gt1_rxresetdone_out      => gt1_rxresetdone_out,
502 
   -- Clocking
503 
      gt1_rxbufstatus_out      => gt1_rxbufstatus_out,
504 
      gt1_txphaligndone_out    => gt1_txphaligndone_out,
505 
      gt1_txphinitdone_out     => gt1_txphinitdone_out,
506 
      gt1_txdlysresetdone_out  => gt1_txdlysresetdone_out,
507 
   -- Signal Integrity adn Functionality
508 
   -- Eye Scan
509 
      gt1_eyescantrigger_in    => gt1_eyescantrigger_in,
510 
      gt1_eyescanreset_in      => gt1_eyescanreset_in,
511 
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
512 
      gt1_rxrate_in            => gt1_rxrate_in,
513 
   -- Loopback
514 
      gt1_loopback_in          => gt1_loopback_in,
515 
   -- Polarity
516 
      gt1_rxpolarity_in        => gt1_rxpolarity_in,
517 
      gt1_txpolarity_in        => gt1_txpolarity_in,
518 
   -- RX Decision Feedback Equalizer(DFE)
519 
      gt1_rxlpmen_in           => gt1_rxlpmen_in,
520 
      gt1_rxdfelpmreset_in     => gt1_rxdfelpmreset_in,
521 
      gt1_rxmonitorsel_in      => gt1_rxmonitorsel_in,
522 
      gt1_rxmonitorout_out     => gt1_rxmonitorout_out,
523 
   -- TX Driver
524 
      gt1_txpostcursor_in      => gt1_txpostcursor_in,
525 
      gt1_txprecursor_in       => gt1_txprecursor_in,
526 
      gt1_txdiffctrl_in        => gt1_txdiffctrl_in,
527 
      gt1_txinhibit_in         => gt1_txinhibit_in,
528 
   -- PRBS
529 
      gt1_rxprbscntreset_in    => gt1_rxprbscntreset_in,
530 
      gt1_rxprbserr_out        => gt1_rxprbserr_out,
531 
      gt1_rxprbssel_in         => gt1_rxprbssel_in,
532 
      gt1_txprbssel_in         => gt1_txprbssel_in,
533 
      gt1_txprbsforceerr_in    => gt1_txprbsforceerr_in,
534 
 
535 
      gt1_rxcdrhold_in         => gt1_rxcdrhold_in,
536 
      gt1_dmonitorout_out      => gt1_dmonitorout_out,
537 
 
538 
   -- Status
539 
      gt1_rxdisperr_out        => gt1_rxdisperr_out,
540 
      gt1_rxnotintable_out     => gt1_rxnotintable_out,
541 
      gt1_rxcommadet_out       => gt1_rxcommadet_out,
542 
      mdc                      => mdc,
543 
      mdio_in                  => mdio_in,
544 
      mdio_out                 => mdio_out,
545 
      mdio_tri                 => mdio_tri,
546 
      prtad                    => prtad,
547 
      type_sel                 => type_sel);
548 
 
549 
  rxaui_support_clocking_i : rxaui_0_support_clocking
550 
    port map (
551 
      refclk_p                 => refclk_p,
552 
      refclk_n                 => refclk_n,
553 
      refclk                   => refclk
554 
      );
555 
 
556 
  rxaui_support_resets_i : rxaui_0_support_resets
557 
    port map (
558 
      reset                    => reset,
559 
      dclk                     => dclk,
560 
      common_pll_reset         => common_pll_reset_i
561 
      );
562 
 
563 
  rxaui_gt_common_i : rxaui_0_gt_common_wrapper
564 
    generic map(
565 
     SIM_RESET_SPEEDUP         => "TRUE")
566 
    port map(
567 
     GTREFCLK0_IN => refclk,
568 
     QPLLLOCK_OUT              => qplllock_i,
569 
     QPLLLOCKDETCLK_IN         => dclk,
570 
     QPLLOUTCLK_OUT            => qplloutclk_i,
571 
     QPLLOUTREFCLK_OUT         => qplloutrefclk_i,
572 
     QPLLREFCLKLOST_OUT        => open,
573 
     QPLLRESET_IN              => common_pll_reset_i
574 
  );
575 
 
576 
  qplllock_out      <= qplllock_i;
577 
  qplloutclk_out    <= qplloutclk_i;
578 
  qplloutrefclk_out <= qplloutrefclk_i;
579 
  refclk_out        <= refclk;
580 
 
581 
end wrapper;

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