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--

--   ____  ____ 

--  /   /\/   / 

-- /___/  \  /    Vendor: Xilinx 

-- \   \   \/     Version : 3.5

--  \   \         Application : 7 Series FPGAs Transceivers Wizard 

--  /   /         Filename : rxaui_0_tx_sync_sync_block.vhd

-- /___/   /\     

-- \   \  /  \ 

--  \___\/\___\ 

--

-- Description: Used on signals crossing from one clock domain to

--              another, this is a flip-flop pair, with both flops

--              placed together with RLOCs into the same slice.  Thus

--              the routing delay between the two is minimum to safe-

--              guard against metastability issues.

--

--  Module  rxaui_0_tx_sync_sync_block

--  Generated by Xilinx 7 Series FPGAs Transceivers Wizard

-- 

-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.

-- 

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

-- 

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-- otherwise provided in a valid license issued to you by

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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

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-- PART OF THIS FILE AT ALL TIMES. 

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

entity rxaui_0_tx_sync_sync_block is

  generic (

    INITIALISE : bit_vector(5 downto 0) := "000000"

  );

  port (

    clk         : in  std_logic;          -- clock to be sync'ed to

    data_in     : in  std_logic;          -- Data to be 'synced'

    data_out    : out std_logic           -- synced data

    );

-- attribute dont_touch : string;

-- attribute dont_touch    of   gtwizard_0_sync_block : entity is "yes";

end rxaui_0_tx_sync_sync_block;

architecture structural of rxaui_0_tx_sync_sync_block is

  -- Internal Signals

  signal data_sync1 : std_logic;

  signal data_sync2 : std_logic;

  signal data_sync3 : std_logic;

  signal data_sync4 : std_logic;

  signal data_sync5 : std_logic;

  -- These attributes will stop timing errors being reported in back annotated

  -- SDF simulation.

  attribute ASYNC_REG                       : string;

  attribute ASYNC_REG of data_sync_reg1    : label is "true";

  attribute ASYNC_REG of data_sync_reg2    : label is "true";

  attribute ASYNC_REG of data_sync_reg3    : label is "true";

  attribute ASYNC_REG of data_sync_reg4    : label is "true";

  attribute ASYNC_REG of data_sync_reg5    : label is "true";

  attribute ASYNC_REG of data_sync_reg6    : label is "true";

  -- These attributes will stop XST translating the desired flip-flops into an

  -- SRL based shift register.

  attribute shreg_extract                   : string;

  attribute shreg_extract of data_sync_reg1 : label is "no";

  attribute shreg_extract of data_sync_reg2 : label is "no";

  attribute shreg_extract of data_sync_reg3 : label is "no";

  attribute shreg_extract of data_sync_reg4 : label is "no";

  attribute shreg_extract of data_sync_reg5 : label is "no";

  attribute shreg_extract of data_sync_reg6 : label is "no";

begin

  data_sync_reg1 : FD

  generic map (

    INIT => INITIALISE(0)

  )

  port map (

    C    => clk,

    D    => data_in,

    Q    => data_sync1

  );

 data_sync_reg2 : FD

  generic map (

    INIT => INITIALISE(1)

  )

  port map (

    C    => clk,

    D    => data_sync1,

    Q    => data_sync2

  );

 data_sync_reg3 : FD

  generic map (

    INIT => INITIALISE(2)

  )

  port map (

    C    => clk,

    D    => data_sync2,

    Q    => data_sync3

  );

 data_sync_reg4 : FD

  generic map (

    INIT => INITIALISE(3)

  )

  port map (

    C    => clk,

    D    => data_sync3,

    Q    => data_sync4

  );

 data_sync_reg5 : FD

  generic map (

    INIT => INITIALISE(4)

  )

  port map (

    C    => clk,

    D    => data_sync4,

    Q    => data_sync5

  );

  data_sync_reg6 : FD

  generic map (

    INIT => INITIALISE(5)

  )

  port map (

    C    => clk,

    D    => data_sync5,

    Q    => data_out

  );

end structural;