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--// /___/  \  /    Vendor: Xilinx 

--// \   \   \/     Version : 3.5

--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 

--//  /   /         Filename : rxaui_0_tx_sync_sync_pulse.vhd

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--

-- Description: Used on signals crossing from faster clock domain 

--                     

--

-- Module rxaui_0_tx_sync_sync_pulse

-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard

-- 

-- 

-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.

-- 

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

-- 

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity rxaui_0_tx_sync_sync_pulse is

  Generic(

           C_NUM_SRETCH_REGS                  : integer  := 3;

           C_NUM_SYNC_REGS                    : integer  := 3

         );

    Port (

  -- Clock and Reset

           CLK          : in  STD_LOGIC;

  -- User Interface

           USER_DONE    : out STD_LOGIC := '0';

  -- GT Interface

           GT_DONE      : in  STD_LOGIC

           );

end rxaui_0_tx_sync_sync_pulse;

architecture RTL of rxaui_0_tx_sync_sync_pulse is

-- ---------------------------------------------------------------------------

-- Wire and Register Declaration

-- ---------------------------------------------------------------------------

signal stretch_r : std_logic_vector (C_NUM_SRETCH_REGS-1 downto 0):= (others=>'0');

signal sync1_r   : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0');

signal sync2_r   : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0');

  -- These attributes will stop Vivado translating the desired flip-flops into an

  -- SRL based shift register.

  attribute ASYNC_REG                       : string;

  attribute ASYNC_REG of sync1_r            : signal is "TRUE";

  attribute ASYNC_REG of sync2_r            : signal is "TRUE";

 -- These attributes will stop XST translating the desired flip-flops into an

  -- SRL based shift register.

  attribute shreg_extract                   : string;

  attribute shreg_extract of sync1_r        : signal is "no";

  attribute shreg_extract of sync2_r        : signal is "no";

begin

------------------------------------------------------------------------------

-- Stretch GT_DONE Signal

------------------------------------------------------------------------------

     process (CLK,GT_DONE)

      begin

         if (GT_DONE = '0') then

           stretch_r <= (others=>'0');

         elsif (CLK'event and CLK = '1') then

           stretch_r <= ('1' & stretch_r(C_NUM_SRETCH_REGS-1 downto 1));

       end if;

      end process;

------------------------------------------------------------------------------

-- Synchronizers

------------------------------------------------------------------------------

     process (CLK)

      begin

         if (CLK'event and CLK = '1') then

           sync1_r <= (stretch_r(0) & sync1_r(C_NUM_SYNC_REGS-1 downto 1));

         end if;

      end process;

     process (CLK)

      begin

         if (CLK'event and CLK = '1') then

           sync2_r <= (GT_DONE & sync2_r(C_NUM_SYNC_REGS-1 downto 1));

         end if;

      end process;

------------------------------------------------------------------------------

-- Final Flop Stage with AND of both synchronizers - keeps USER_DONE low 

-- when input is low for many cycles...

------------------------------------------------------------------------------

     process (CLK)

      begin

         if (CLK'event and CLK = '1') then

           USER_DONE <= sync1_r(0) and sync2_r(0);

         end if;

      end process;

end RTL;