OpenCores
URL https://opencores.org/ocsvn/xenie/xenie/trunk

Subversion Repositories xenie

[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [tcl/] [recreate_bd_xc7k160t.tcl] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 DFC 
 
2 
################################################################
3 
# This is a generated script based on design: main_bd
4 
#
5 
# Though there are limitations about the generated script,
6 
# the main purpose of this utility is to make learning
7 
# IP Integrator Tcl commands easier.
8 
################################################################
9 
 
10 
namespace eval _tcl {
11 
proc get_script_folder {} {
12 
   set script_path [file normalize [info script]]
13 
   set script_folder [file dirname $script_path]
14 
   return $script_folder
15 
}
16 
}
17 
variable script_folder
18 
set script_folder [_tcl::get_script_folder]
19 
 
20 
################################################################
21 
# Check if script is running in correct Vivado version.
22 
################################################################
23 
set scripts_vivado_version 2016.4
24 
set current_vivado_version [version -short]
25 
 
26 
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
27 
   puts ""
28 
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
29 
 
30 
   return 1
31 
}
32 
 
33 
################################################################
34 
# START
35 
################################################################
36 
 
37 
# To test this script, run the following commands from Vivado Tcl console:
38 
# source main_bd_script.tcl
39 
 
40 
# If there is no project opened, this script will create a
41 
# project, but make sure you do not have an existing project
42 
# <./myproj/project_1.xpr> in the current working folder.
43 
 
44 
set list_projs [get_projects -quiet]
45 
if { $list_projs eq "" } {
46 
   create_project project_1 myproj -part xc7k160tffg676-1
47 
}
48 
 
49 
 
50 
# CHANGE DESIGN NAME HERE
51 
set design_name main_bd
52 
 
53 
# This script was generated for a remote BD. To create a non-remote design,
54 
# change the variable <run_remote_bd_flow> to <0>.
55 
 
56 
set run_remote_bd_flow 1
57 
if { $run_remote_bd_flow == 1 } {
58 
  # Set the reference directory for source file relative paths (by default
59 
  # the value is script directory path)
60 
  set origin_dir ./bd
61 
 
62 
  # Use origin directory path location variable, if specified in the tcl shell
63 
  if { [info exists ::origin_dir_loc] } {
64 
     set origin_dir $::origin_dir_loc
65 
  }
66 
 
67 
  set str_bd_folder [file normalize ${origin_dir}]
68 
  set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
69 
 
70 
  # Check if remote design exists on disk
71 
  if { [file exists $str_bd_filepath ] == 1 } {
72 
     catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
73 
     common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
74 
     common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
75 
 
76 
     return 1
77 
  }
78 
 
79 
  # Check if design exists in memory
80 
  set list_existing_designs [get_bd_designs -quiet $design_name]
81 
  if { $list_existing_designs ne "" } {
82 
     catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
83 
 
84 
     common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
85 
 
86 
     return 1
87 
  }
88 
 
89 
  # Check if design exists on disk within project
90 
  set list_existing_designs [get_files */${design_name}.bd]
91 
  if { $list_existing_designs ne "" } {
92 
     catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
93 
    $list_existing_designs"}
94 
     catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
95 
 
96 
     common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
97 
 
98 
     return 1
99 
  }
100 
 
101 
  # Now can create the remote BD
102 
  # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
103 
  create_bd_design -dir $str_bd_folder $design_name
104 
} else {
105 
 
106 
  # Create regular design
107 
  if { [catch {create_bd_design $design_name} errmsg] } {
108 
     common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
109 
 
110 
     return 1
111 
  }
112 
}
113 
 
114 
current_bd_design $design_name
115 
 
116 
 
117 
##################################################################
118 
# MIG PRJ FILE TCL PROCs
119 
##################################################################
120 
 
121 
proc write_mig_file_main_bd_mig_7series_0_0 { str_mig_prj_filepath } {
122 
 
123 
   set mig_prj_file [open $str_mig_prj_filepath  w+]
124 
 
125 
   puts $mig_prj_file {<?xml version='1.0' encoding='UTF-8'?>}
126 
   puts $mig_prj_file {<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->}
127 
   puts $mig_prj_file {<Project NoOfControllers="1" >}
128 
   puts $mig_prj_file {    <ModuleName>main_bd_mig_7series_0_0</ModuleName>}
129 
   puts $mig_prj_file {    <dci_inouts_inputs>1</dci_inouts_inputs>}
130 
   puts $mig_prj_file {    <dci_inputs>1</dci_inputs>}
131 
   puts $mig_prj_file {    <Debug_En>OFF</Debug_En>}
132 
   puts $mig_prj_file {    <DataDepth_En>1024</DataDepth_En>}
133 
   puts $mig_prj_file {    <LowPower_En>ON</LowPower_En>}
134 
   puts $mig_prj_file {    <XADC_En>Enabled</XADC_En>}
135 
   puts $mig_prj_file {    <TargetFPGA>xc7k160t-ffg676/-1</TargetFPGA>}
136 
   puts $mig_prj_file {    <Version>4.0</Version>}
137 
   puts $mig_prj_file {    <SystemClock>No Buffer</SystemClock>}
138 
   puts $mig_prj_file {    <ReferenceClock>Use System Clock</ReferenceClock>}
139 
   puts $mig_prj_file {    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>}
140 
   puts $mig_prj_file {    <BankSelectionFlag>FALSE</BankSelectionFlag>}
141 
   puts $mig_prj_file {    <InternalVref>0</InternalVref>}
142 
   puts $mig_prj_file {    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>}
143 
   puts $mig_prj_file {    <dci_cascade>0</dci_cascade>}
144 
   puts $mig_prj_file {    <Controller number="0" >}
145 
   puts $mig_prj_file {        <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>}
146 
   puts $mig_prj_file {        <TimePeriod>3077</TimePeriod>}
147 
   puts $mig_prj_file {        <VccAuxIO>1.8V</VccAuxIO>}
148 
   puts $mig_prj_file {        <PHYRatio>4:1</PHYRatio>}
149 
   puts $mig_prj_file {        <InputClkFreq>199.995</InputClkFreq>}
150 
   puts $mig_prj_file {        <UIExtraClocks>1</UIExtraClocks>}
151 
   puts $mig_prj_file {        <MMCM_VCO>649</MMCM_VCO>}
152 
   puts $mig_prj_file {        <MMCMClkOut0> 1.000</MMCMClkOut0>}
153 
   puts $mig_prj_file {        <MMCMClkOut1>1</MMCMClkOut1>}
154 
   puts $mig_prj_file {        <MMCMClkOut2>1</MMCMClkOut2>}
155 
   puts $mig_prj_file {        <MMCMClkOut3>1</MMCMClkOut3>}
156 
   puts $mig_prj_file {        <MMCMClkOut4>1</MMCMClkOut4>}
157 
   puts $mig_prj_file {        <DataWidth>32</DataWidth>}
158 
   puts $mig_prj_file {        <DeepMemory>1</DeepMemory>}
159 
   puts $mig_prj_file {        <DataMask>1</DataMask>}
160 
   puts $mig_prj_file {        <ECC>Disabled</ECC>}
161 
   puts $mig_prj_file {        <Ordering>Normal</Ordering>}
162 
   puts $mig_prj_file {        <BankMachineCnt>4</BankMachineCnt>}
163 
   puts $mig_prj_file {        <CustomPart>FALSE</CustomPart>}
164 
   puts $mig_prj_file {        <NewPartName></NewPartName>}
165 
   puts $mig_prj_file {        <RowAddress>15</RowAddress>}
166 
   puts $mig_prj_file {        <ColAddress>10</ColAddress>}
167 
   puts $mig_prj_file {        <BankAddress>3</BankAddress>}
168 
   puts $mig_prj_file {        <MemoryVoltage>1.35V</MemoryVoltage>}
169 
   puts $mig_prj_file {        <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>}
170 
   puts $mig_prj_file {        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>}
171 
   puts $mig_prj_file {        <PinSelection>}
172 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF10" SLEW="" name="ddr3_addr[0]" IN_TERM="" />}
173 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />}
174 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD13" SLEW="" name="ddr3_addr[11]" IN_TERM="" />}
175 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE11" SLEW="" name="ddr3_addr[12]" IN_TERM="" />}
176 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF13" SLEW="" name="ddr3_addr[13]" IN_TERM="" />}
177 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC12" SLEW="" name="ddr3_addr[14]" IN_TERM="" />}
178 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA9" SLEW="" name="ddr3_addr[1]" IN_TERM="" />}
179 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />}
180 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />}
181 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE12" SLEW="" name="ddr3_addr[4]" IN_TERM="" />}
182 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />}
183 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF12" SLEW="" name="ddr3_addr[6]" IN_TERM="" />}
184 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE13" SLEW="" name="ddr3_addr[7]" IN_TERM="" />}
185 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />}
186 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />}
187 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />}
188 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AB9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />}
189 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD10" SLEW="" name="ddr3_ba[2]" IN_TERM="" />}
190 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD8" SLEW="" name="ddr3_cas_n" IN_TERM="" />}
191 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135" PADName="AF7" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />}
192 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135" PADName="AE7" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />}
193 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AB7" SLEW="" name="ddr3_cke[0]" IN_TERM="" />}
194 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD9" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />}
195 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD5" SLEW="" name="ddr3_dm[0]" IN_TERM="" />}
196 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />}
197 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="V3" SLEW="" name="ddr3_dm[2]" IN_TERM="" />}
198 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="Y2" SLEW="" name="ddr3_dm[3]" IN_TERM="" />}
199 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AB4" SLEW="" name="ddr3_dq[0]" IN_TERM="" />}
200 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[10]" IN_TERM="" />}
201 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AD1" SLEW="" name="ddr3_dq[11]" IN_TERM="" />}
202 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />}
203 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AD4" SLEW="" name="ddr3_dq[13]" IN_TERM="" />}
204 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[14]" IN_TERM="" />}
205 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[15]" IN_TERM="" />}
206 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U1" SLEW="" name="ddr3_dq[16]" IN_TERM="" />}
207 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V4" SLEW="" name="ddr3_dq[17]" IN_TERM="" />}
208 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U7" SLEW="" name="ddr3_dq[18]" IN_TERM="" />}
209 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="W3" SLEW="" name="ddr3_dq[19]" IN_TERM="" />}
210 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[1]" IN_TERM="" />}
211 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U5" SLEW="" name="ddr3_dq[20]" IN_TERM="" />}
212 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V6" SLEW="" name="ddr3_dq[21]" IN_TERM="" />}
213 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U2" SLEW="" name="ddr3_dq[22]" IN_TERM="" />}
214 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U6" SLEW="" name="ddr3_dq[23]" IN_TERM="" />}
215 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AA3" SLEW="" name="ddr3_dq[24]" IN_TERM="" />}
216 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y1" SLEW="" name="ddr3_dq[25]" IN_TERM="" />}
217 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y3" SLEW="" name="ddr3_dq[26]" IN_TERM="" />}
218 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V2" SLEW="" name="ddr3_dq[27]" IN_TERM="" />}
219 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AB2" SLEW="" name="ddr3_dq[28]" IN_TERM="" />}
220 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V1" SLEW="" name="ddr3_dq[29]" IN_TERM="" />}
221 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y5" SLEW="" name="ddr3_dq[2]" IN_TERM="" />}
222 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[30]" IN_TERM="" />}
223 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="W1" SLEW="" name="ddr3_dq[31]" IN_TERM="" />}
224 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />}
225 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AA4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />}
226 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />}
227 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />}
228 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC3" SLEW="" name="ddr3_dq[7]" IN_TERM="" />}
229 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[8]" IN_TERM="" />}
230 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE2" SLEW="" name="ddr3_dq[9]" IN_TERM="" />}
231 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AB5" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />}
232 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AF4" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />}
233 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="W5" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />}
234 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AC1" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />}
235 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AA5" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />}
236 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AF5" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />}
237 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="W6" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />}
238 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AB1" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />}
239 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />}
240 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC7" SLEW="" name="ddr3_ras_n" IN_TERM="" />}
241 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA2" SLEW="" name="ddr3_reset_n" IN_TERM="" />}
242 
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF8" SLEW="" name="ddr3_we_n" IN_TERM="" />}
243 
   puts $mig_prj_file {        </PinSelection>}
244 
   puts $mig_prj_file {        <System_Control>}
245 
   puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />}
246 
   puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />}
247 
   puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />}
248 
   puts $mig_prj_file {        </System_Control>}
249 
   puts $mig_prj_file {        <TimingParameters>}
250 
   puts $mig_prj_file {            <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />}
251 
   puts $mig_prj_file {        </TimingParameters>}
252 
   puts $mig_prj_file {        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>}
253 
   puts $mig_prj_file {        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>}
254 
   puts $mig_prj_file {        <mrCasLatency name="CAS Latency" >5</mrCasLatency>}
255 
   puts $mig_prj_file {        <mrMode name="Mode" >Normal</mrMode>}
256 
   puts $mig_prj_file {        <mrDllReset name="DLL Reset" >No</mrDllReset>}
257 
   puts $mig_prj_file {        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>}
258 
   puts $mig_prj_file {        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>}
259 
   puts $mig_prj_file {        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>}
260 
   puts $mig_prj_file {        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>}
261 
   puts $mig_prj_file {        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>}
262 
   puts $mig_prj_file {        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>}
263 
   puts $mig_prj_file {        <emrPosted name="Additive Latency (AL)" >0</emrPosted>}
264 
   puts $mig_prj_file {        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>}
265 
   puts $mig_prj_file {        <emrDQS name="TDQS enable" >Enabled</emrDQS>}
266 
   puts $mig_prj_file {        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>}
267 
   puts $mig_prj_file {        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>}
268 
   puts $mig_prj_file {        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>}
269 
   puts $mig_prj_file {        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>}
270 
   puts $mig_prj_file {        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>}
271 
   puts $mig_prj_file {        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>}
272 
   puts $mig_prj_file {        <PortInterface>AXI</PortInterface>}
273 
   puts $mig_prj_file {        <AXIParameters>}
274 
   puts $mig_prj_file {            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>}
275 
   puts $mig_prj_file {            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>}
276 
   puts $mig_prj_file {            <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>}
277 
   puts $mig_prj_file {            <C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>}
278 
   puts $mig_prj_file {            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>}
279 
   puts $mig_prj_file {        </AXIParameters>}
280 
   puts $mig_prj_file {    </Controller>}
281 
   puts $mig_prj_file {</Project>}
282 
 
283 
   close $mig_prj_file
284 
}
285 
# End of write_mig_file_main_bd_mig_7series_0_0()
286 
 
287 
 
288 
 
289 
##################################################################
290 
# DESIGN PROCs
291 
##################################################################
292 
 
293 
 
294 
# Hierarchical cell: microblaze_0_local_memory
295 
proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
296 
 
297 
  variable script_folder
298 
 
299 
  if { $parentCell eq "" || $nameHier eq "" } {
300 
     catch {common::send_msg_id "BD_TCL-102" "ERROR" create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"}
301 
     return
302 
  }
303 
 
304 
  # Get object for parentCell
305 
  set parentObj [get_bd_cells $parentCell]
306 
  if { $parentObj == "" } {
307 
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
308 
     return
309 
  }
310 
 
311 
  # Make sure parentObj is hier blk
312 
  set parentType [get_property TYPE $parentObj]
313 
  if { $parentType ne "hier" } {
314 
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
315 
     return
316 
  }
317 
 
318 
  # Save current instance; Restore later
319 
  set oldCurInst [current_bd_instance .]
320 
 
321 
  # Set parent object as current
322 
  current_bd_instance $parentObj
323 
 
324 
  # Create cell and set as current instance
325 
  set hier_obj [create_bd_cell -type hier $nameHier]
326 
  current_bd_instance $hier_obj
327 
 
328 
  # Create interface pins
329 
  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
330 
  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
331 
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:lmb_rtl:1.0 SLMB1
332 
 
333 
  # Create pins
334 
  create_bd_pin -dir I -type clk LMB_Clk
335 
  create_bd_pin -dir I -type rst SYS_Rst
336 
 
337 
  # Create instance: dlmb_bram_if_cntlr, and set properties
338 
  set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
339 
  set_property -dict [ list \
340 
CONFIG.C_ECC {0} \
341 
CONFIG.C_NUM_LMB {2} \
342 
 ] $dlmb_bram_if_cntlr
343 
 
344 
  # Create instance: dlmb_v10, and set properties
345 
  set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
346 
  set_property -dict [ list \
347 
CONFIG.C_LMB_NUM_SLAVES {1} \
348 
 ] $dlmb_v10
349 
 
350 
  # Create instance: ilmb_bram_if_cntlr, and set properties
351 
  set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
352 
  set_property -dict [ list \
353 
CONFIG.C_ECC {0} \
354 
 ] $ilmb_bram_if_cntlr
355 
 
356 
  # Create instance: ilmb_v10, and set properties
357 
  set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
358 
 
359 
  # Create instance: lmb_bram, and set properties
360 
  set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 lmb_bram ]
361 
  set_property -dict [ list \
362 
CONFIG.Memory_Type {True_Dual_Port_RAM} \
363 
CONFIG.use_bram_block {BRAM_Controller} \
364 
 ] $lmb_bram
365 
 
366 
  # Create interface connections
367 
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins SLMB1] [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB1]
368 
  connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
369 
  connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
370 
  connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
371 
  connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
372 
  connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
373 
  connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
374 
 
375 
  # Create port connections
376 
  connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
377 
  connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
378 
 
379 
  # Restore current instance
380 
  current_bd_instance $oldCurInst
381 
}
382 
 
383 
 
384 
# Procedure to create entire design; Provide argument to make
385 
# procedure reusable. If parentCell is "", will use root.
386 
proc create_root_design { parentCell } {
387 
 
388 
  variable script_folder
389 
 
390 
  if { $parentCell eq "" } {
391 
     set parentCell [get_bd_cells /]
392 
  }
393 
 
394 
  # Get object for parentCell
395 
  set parentObj [get_bd_cells $parentCell]
396 
  if { $parentObj == "" } {
397 
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
398 
     return
399 
  }
400 
 
401 
  # Make sure parentObj is hier blk
402 
  set parentType [get_property TYPE $parentObj]
403 
  if { $parentType ne "hier" } {
404 
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
405 
     return
406 
  }
407 
 
408 
  # Save current instance; Restore later
409 
  set oldCurInst [current_bd_instance .]
410 
 
411 
  # Set parent object as current
412 
  current_bd_instance $parentObj
413 
 
414 
 
415 
  # Create interface ports
416 
  set DDR3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 ]
417 
  set IIC_RTL [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_RTL ]
418 
  set MB_MDIO [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 MB_MDIO ]
419 
  set MB_UART [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 MB_UART ]
420 
  set SPI_RTL [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI_RTL ]
421 
 
422 
  # Create ports
423 
  set AXI_CLK [ create_bd_port -dir O -type clk AXI_CLK ]
424 
  set GPIO2_IO_I [ create_bd_port -dir I -from 31 -to 0 GPIO2_IO_I ]
425 
  set GPIO2_IO_O [ create_bd_port -dir O -from 31 -to 0 GPIO2_IO_O ]
426 
  set GPIO2_IO_T [ create_bd_port -dir O -from 31 -to 0 GPIO2_IO_T ]
427 
  set GPIO_IO_I [ create_bd_port -dir I -from 31 -to 0 GPIO_IO_I ]
428 
  set GPIO_IO_O [ create_bd_port -dir O -from 31 -to 0 GPIO_IO_O ]
429 
  set GPIO_IO_T [ create_bd_port -dir O -from 31 -to 0 GPIO_IO_T ]
430 
  set HOST_IP [ create_bd_port -dir O -from 31 -to 0 HOST_IP ]
431 
  set HOST_IP_NETMASK [ create_bd_port -dir O -from 31 -to 0 HOST_IP_NETMASK ]
432 
  set HOST_MAC0 [ create_bd_port -dir O -from 31 -to 0 HOST_MAC0 ]
433 
  set HOST_MAC1 [ create_bd_port -dir O -from 31 -to 0 HOST_MAC1 ]
434 
  set SYS_CLK_I [ create_bd_port -dir I -type clk SYS_CLK_I ]
435 
  set_property -dict [ list \
436 
CONFIG.CLK_DOMAIN {main_bd_util_ds_buf_0_0_IBUF_OUT} \
437 
CONFIG.FREQ_HZ {200000000} \
438 
 ] $SYS_CLK_I
439 
  set VERSION_GPIO [ create_bd_port -dir I -from 63 -to 0 VERSION_GPIO ]
440 
 
441 
  # Create instance: Const_no_ext_rst, and set properties
442 
  set Const_no_ext_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 Const_no_ext_rst ]
443 
 
444 
  # Create instance: axi_gpio_0, and set properties
445 
  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
446 
  set_property -dict [ list \
447 
CONFIG.C_IS_DUAL {1} \
448 
 ] $axi_gpio_0
449 
 
450 
  # Create instance: axi_gpio_1_version, and set properties
451 
  set axi_gpio_1_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1_version ]
452 
  set_property -dict [ list \
453 
CONFIG.C_ALL_INPUTS {1} \
454 
CONFIG.C_ALL_INPUTS_2 {1} \
455 
CONFIG.C_IS_DUAL {1} \
456 
 ] $axi_gpio_1_version
457 
 
458 
  # Create instance: axi_gpio_2_netInfo, and set properties
459 
  set axi_gpio_2_netInfo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2_netInfo ]
460 
  set_property -dict [ list \
461 
CONFIG.C_ALL_INPUTS {0} \
462 
CONFIG.C_ALL_INPUTS_2 {0} \
463 
CONFIG.C_ALL_OUTPUTS {0} \
464 
CONFIG.C_ALL_OUTPUTS_2 {0} \
465 
CONFIG.C_IS_DUAL {1} \
466 
 ] $axi_gpio_2_netInfo
467 
 
468 
  # Create instance: axi_iic_0, and set properties
469 
  set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
470 
  set_property -dict [ list \
471 
CONFIG.C_SCL_INERTIAL_DELAY {5} \
472 
CONFIG.C_SDA_INERTIAL_DELAY {5} \
473 
 ] $axi_iic_0
474 
 
475 
  # Create instance: axi_interconnect_0_ddr, and set properties
476 
  set axi_interconnect_0_ddr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0_ddr ]
477 
  set_property -dict [ list \
478 
CONFIG.NUM_MI {1} \
479 
CONFIG.NUM_SI {3} \
480 
 ] $axi_interconnect_0_ddr
481 
 
482 
  # Create instance: axi_quad_spi_0, and set properties
483 
  set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
484 
  set_property -dict [ list \
485 
CONFIG.C_FIFO_DEPTH {16} \
486 
CONFIG.C_SCK_RATIO {2} \
487 
CONFIG.C_SHARED_STARTUP {0} \
488 
CONFIG.C_SPI_MEMORY {3} \
489 
CONFIG.C_SPI_MODE {2} \
490 
CONFIG.C_USE_STARTUP {1} \
491 
CONFIG.C_USE_STARTUP_INT {1} \
492 
 ] $axi_quad_spi_0
493 
 
494 
  # Create instance: axi_timer_0, and set properties
495 
  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
496 
 
497 
  # Create instance: axi_uartlite_0, and set properties
498 
  set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
499 
  set_property -dict [ list \
500 
CONFIG.C_BAUDRATE {115200} \
501 
 ] $axi_uartlite_0
502 
 
503 
  # Create instance: clk_wiz_0, and set properties
504 
  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 clk_wiz_0 ]
505 
  set_property -dict [ list \
506 
CONFIG.CLKIN1_JITTER_PS {50.0} \
507 
CONFIG.CLKOUT1_JITTER {112.316} \
508 
CONFIG.CLKOUT1_PHASE_ERROR {89.971} \
509 
CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \
510 
CONFIG.MMCM_CLKIN1_PERIOD {5.0} \
511 
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
512 
CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \
513 
CONFIG.MMCM_COMPENSATION {ZHOLD} \
514 
CONFIG.PRIM_SOURCE {No_buffer} \
515 
CONFIG.USE_RESET {false} \
516 
 ] $clk_wiz_0
517 
 
518 
  # Need to retain value_src of defaults
519 
  set_property -dict [ list \
520 
CONFIG.CLKIN1_JITTER_PS.VALUE_SRC {DEFAULT} \
521 
CONFIG.CLKOUT1_JITTER.VALUE_SRC {DEFAULT} \
522 
CONFIG.CLKOUT1_PHASE_ERROR.VALUE_SRC {DEFAULT} \
523 
CONFIG.MMCM_CLKFBOUT_MULT_F.VALUE_SRC {DEFAULT} \
524 
CONFIG.MMCM_CLKIN1_PERIOD.VALUE_SRC {DEFAULT} \
525 
CONFIG.MMCM_CLKIN2_PERIOD.VALUE_SRC {DEFAULT} \
526 
CONFIG.MMCM_CLKOUT0_DIVIDE_F.VALUE_SRC {DEFAULT} \
527 
CONFIG.MMCM_COMPENSATION.VALUE_SRC {DEFAULT} \
528 
 ] $clk_wiz_0
529 
 
530 
  # Create instance: mdio_master_top_0, and set properties
531 
  set mdio_master_top_0 [ create_bd_cell -type ip -vlnv dfcdesign.cz:dfc:mdio_master_top:1.1 mdio_master_top_0 ]
532 
 
533 
  # Create instance: mdm_1, and set properties
534 
  set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
535 
  set_property -dict [ list \
536 
CONFIG.C_DBG_MEM_ACCESS {1} \
537 
CONFIG.C_USE_UART {1} \
538 
 ] $mdm_1
539 
 
540 
  # Create instance: microblaze_0, and set properties
541 
  set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ]
542 
  set_property -dict [ list \
543 
CONFIG.C_DCACHE_LINE_LEN {8} \
544 
CONFIG.C_DEBUG_ENABLED {1} \
545 
CONFIG.C_D_AXI {1} \
546 
CONFIG.C_D_LMB {1} \
547 
CONFIG.C_ICACHE_LINE_LEN {8} \
548 
CONFIG.C_I_LMB {1} \
549 
CONFIG.C_USE_DCACHE {1} \
550 
CONFIG.C_USE_ICACHE {1} \
551 
 ] $microblaze_0
552 
 
553 
  # Create instance: microblaze_0_axi_intc, and set properties
554 
  set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ]
555 
  set_property -dict [ list \
556 
CONFIG.C_HAS_FAST {0} \
557 
 ] $microblaze_0_axi_intc
558 
 
559 
  # Create instance: microblaze_0_axi_periph, and set properties
560 
  set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
561 
  set_property -dict [ list \
562 
CONFIG.NUM_MI {10} \
563 
CONFIG.NUM_SI {1} \
564 
 ] $microblaze_0_axi_periph
565 
 
566 
  # Create instance: microblaze_0_int_concat, and set properties
567 
  set microblaze_0_int_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_int_concat ]
568 
  set_property -dict [ list \
569 
CONFIG.NUM_PORTS {5} \
570 
 ] $microblaze_0_int_concat
571 
 
572 
  # Create instance: microblaze_0_local_memory
573 
  create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory
574 
 
575 
  # Create instance: mig_7series_0, and set properties
576 
  set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 mig_7series_0 ]
577 
 
578 
  # Generate the PRJ File for MIG
579 
  set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ]
580 
  set str_mig_file_name mig_b.prj
581 
  set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}
582 
 
583 
  write_mig_file_main_bd_mig_7series_0_0 $str_mig_file_path
584 
 
585 
  set_property -dict [ list \
586 
CONFIG.BOARD_MIG_PARAM {Custom} \
587 
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
588 
CONFIG.RESET_BOARD_INTERFACE {Custom} \
589 
CONFIG.XML_INPUT_FILE {mig_b.prj} \
590 
 ] $mig_7series_0
591 
 
592 
  # Create instance: proc_sys_reset_0, and set properties
593 
  set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
594 
 
595 
  # Create instance: rst_mig_7series_0_100M, and set properties
596 
  set rst_mig_7series_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_mig_7series_0_100M ]
597 
 
598 
  # Create instance: version_slice_0, and set properties
599 
  set version_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 version_slice_0 ]
600 
  set_property -dict [ list \
601 
CONFIG.DIN_FROM {31} \
602 
CONFIG.DIN_TO {0} \
603 
CONFIG.DIN_WIDTH {64} \
604 
CONFIG.DOUT_WIDTH {32} \
605 
 ] $version_slice_0
606 
 
607 
  # Create instance: version_slice_1, and set properties
608 
  set version_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 version_slice_1 ]
609 
  set_property -dict [ list \
610 
CONFIG.DIN_FROM {63} \
611 
CONFIG.DIN_TO {32} \
612 
CONFIG.DIN_WIDTH {64} \
613 
CONFIG.DOUT_WIDTH {32} \
614 
 ] $version_slice_1
615 
 
616 
  # Create interface connections
617 
  connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_ports IIC_RTL] [get_bd_intf_pins axi_iic_0/IIC]
618 
  connect_bd_intf_net -intf_net axi_interconnect_0_ddr_M00_AXI [get_bd_intf_pins axi_interconnect_0_ddr/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
619 
  connect_bd_intf_net -intf_net axi_quad_spi_0_SPI_0 [get_bd_intf_ports SPI_RTL] [get_bd_intf_pins axi_quad_spi_0/SPI_0]
620 
  connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports MB_UART] [get_bd_intf_pins axi_uartlite_0/UART]
621 
  connect_bd_intf_net -intf_net mdio_master_top_0_mdio [get_bd_intf_ports MB_MDIO] [get_bd_intf_pins mdio_master_top_0/mdio]
622 
  connect_bd_intf_net -intf_net mdm_1_LMB_0 [get_bd_intf_pins mdm_1/LMB_0] [get_bd_intf_pins microblaze_0_local_memory/SLMB1]
623 
  connect_bd_intf_net -intf_net mdm_1_M_AXI [get_bd_intf_pins axi_interconnect_0_ddr/S02_AXI] [get_bd_intf_pins mdm_1/M_AXI]
624 
  connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_interconnect_0_ddr/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC]
625 
  connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_interconnect_0_ddr/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC]
626 
  connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
627 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins mdio_master_top_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
628 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins mdm_1/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
629 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI]
630 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI]
631 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI]
632 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins axi_gpio_1_version/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI]
633 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M07_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI]
634 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M08_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M08_AXI]
635 
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M09_AXI [get_bd_intf_pins axi_gpio_2_netInfo/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M09_AXI]
636 
  connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
637 
  connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
638 
  connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
639 
  connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
640 
  connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt]
641 
  connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins mig_7series_0/DDR3]
642 
 
643 
  # Create port connections
644 
  connect_bd_net -net Const_no_ext_rst_dout [get_bd_pins Const_no_ext_rst/dout] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins rst_mig_7series_0_100M/aux_reset_in]
645 
  connect_bd_net -net M00_ARESETN_1 [get_bd_pins axi_interconnect_0_ddr/M00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_mig_7series_0_100M/peripheral_aresetn]
646 
  connect_bd_net -net VERSION_GPIO_1 [get_bd_ports VERSION_GPIO] [get_bd_pins version_slice_0/Din] [get_bd_pins version_slice_1/Din]
647 
  connect_bd_net -net axi_gpio_0_gpio2_io_o [get_bd_ports GPIO2_IO_O] [get_bd_pins axi_gpio_0/gpio2_io_o]
648 
  connect_bd_net -net axi_gpio_0_gpio2_io_t [get_bd_ports GPIO2_IO_T] [get_bd_pins axi_gpio_0/gpio2_io_t]
649 
  connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports GPIO_IO_O] [get_bd_pins axi_gpio_0/gpio_io_o]
650 
  connect_bd_net -net axi_gpio_0_gpio_io_t [get_bd_ports GPIO_IO_T] [get_bd_pins axi_gpio_0/gpio_io_t]
651 
  connect_bd_net -net axi_gpio_2_netInfo_gpio2_io_o [get_bd_ports HOST_IP] [get_bd_pins axi_gpio_2_netInfo/gpio2_io_o]
652 
  connect_bd_net -net axi_gpio_2_netInfo_gpio2_io_t [get_bd_ports HOST_IP_NETMASK] [get_bd_pins axi_gpio_2_netInfo/gpio2_io_t]
653 
  connect_bd_net -net axi_gpio_2_netInfo_gpio_io_o [get_bd_ports HOST_MAC0] [get_bd_pins axi_gpio_2_netInfo/gpio_io_o]
654 
  connect_bd_net -net axi_gpio_2_netInfo_gpio_io_t [get_bd_ports HOST_MAC1] [get_bd_pins axi_gpio_2_netInfo/gpio_io_t]
655 
  connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins microblaze_0_int_concat/In3]
656 
  connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins microblaze_0_int_concat/In1]
657 
  connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins microblaze_0_int_concat/In4]
658 
  connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins microblaze_0_int_concat/In2]
659 
  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_0/dcm_locked]
660 
  connect_bd_net -net gpio2_io_i_1 [get_bd_ports GPIO2_IO_I] [get_bd_pins axi_gpio_0/gpio2_io_i]
661 
  connect_bd_net -net gpio_io_i_1 [get_bd_ports GPIO_IO_I] [get_bd_pins axi_gpio_0/gpio_io_i]
662 
  connect_bd_net -net mdm_1_Debug_SYS_Rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins proc_sys_reset_0/mb_debug_sys_rst]
663 
  connect_bd_net -net mdm_1_Interrupt [get_bd_pins mdm_1/Interrupt] [get_bd_pins microblaze_0_int_concat/In0]
664 
  connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_int_concat/dout]
665 
  connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_mig_7series_0_100M/dcm_locked]
666 
  connect_bd_net -net mig_7series_0_ui_clk [get_bd_ports AXI_CLK] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1_version/s_axi_aclk] [get_bd_pins axi_gpio_2_netInfo/s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_interconnect_0_ddr/ACLK] [get_bd_pins axi_interconnect_0_ddr/S00_ACLK] [get_bd_pins axi_interconnect_0_ddr/S01_ACLK] [get_bd_pins axi_interconnect_0_ddr/S02_ACLK] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mdio_master_top_0/S_AXI_ACLK] [get_bd_pins mdm_1/M_AXI_ACLK] [get_bd_pins mdm_1/S_AXI_ACLK] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/M08_ACLK] [get_bd_pins microblaze_0_axi_periph/M09_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
667 
  connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_pins axi_interconnect_0_ddr/M00_ACLK] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_mig_7series_0_100M/slowest_sync_clk]
668 
  connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_mig_7series_0_100M/ext_reset_in]
669 
  connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0_ddr/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
670 
  connect_bd_net -net rst_mig_7series_0_100M_interconnect_aresetn [get_bd_pins proc_sys_reset_0/aux_reset_in] [get_bd_pins rst_mig_7series_0_100M/interconnect_aresetn]
671 
  connect_bd_net -net rst_mig_7series_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins proc_sys_reset_0/mb_reset]
672 
  connect_bd_net -net rst_mig_7series_0_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1_version/s_axi_aresetn] [get_bd_pins axi_gpio_2_netInfo/s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0_ddr/S00_ARESETN] [get_bd_pins axi_interconnect_0_ddr/S01_ARESETN] [get_bd_pins axi_interconnect_0_ddr/S02_ARESETN] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mdio_master_top_0/S_AXI_ARESETN] [get_bd_pins mdm_1/M_AXI_ARESETN] [get_bd_pins mdm_1/S_AXI_ARESETN] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/M08_ARESETN] [get_bd_pins microblaze_0_axi_periph/M09_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
673 
  connect_bd_net -net sys_clk_i_1 [get_bd_ports SYS_CLK_I] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mig_7series_0/sys_clk_i]
674 
  connect_bd_net -net xlslice_0_Dout [get_bd_pins axi_gpio_1_version/gpio_io_i] [get_bd_pins version_slice_0/Dout]
675 
  connect_bd_net -net xlslice_1_Dout [get_bd_pins axi_gpio_1_version/gpio2_io_i] [get_bd_pins version_slice_1/Dout]
676 
 
677 
  # Create address segments
678 
  create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB1/Mem] SEG_dlmb_bram_if_cntlr_Mem
679 
  create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
680 
  create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
681 
  create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_1_version/S_AXI/Reg] SEG_axi_gpio_1_version_Reg
682 
  create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_2_netInfo/S_AXI/Reg] SEG_axi_gpio_2_netInfo_Reg
683 
  create_bd_addr_seg -range 0x00010000 -offset 0x40800000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
684 
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] SEG_axi_quad_spi_0_Reg
685 
  create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
686 
  create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
687 
  create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
688 
  create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
689 
  create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mdio_master_top_0/S_AXI/reg0] SEG_mdio_master_top_0_reg0
690 
  create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mdm_1/S_AXI/Reg] SEG_mdm_1_Reg
691 
  create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_axi_intc/S_AXI/Reg] SEG_microblaze_0_axi_intc_Reg
692 
  create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
693 
  create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
694 
 
695 
  # Perform GUI Layout
696 
  regenerate_bd_layout -layout_string {
697 
   guistr: "# # String gsaved with Nlview 6.6.5b  2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6
698 
#  -string -flagsOSRD
699 
preplace port SYS_CLK_I -pg 1 -y -1190 -defaultsOSRD
700 
preplace port IIC_RTL -pg 1 -y 670 -defaultsOSRD
701 
preplace port SPI_RTL -pg 1 -y 810 -defaultsOSRD
702 
preplace port MB_MDIO -pg 1 -y 1550 -defaultsOSRD
703 
preplace port DDR3 -pg 1 -y -1200 -defaultsOSRD
704 
preplace port AXI_CLK -pg 1 -y 530 -defaultsOSRD
705 
preplace port MB_UART -pg 1 -y 1310 -defaultsOSRD
706 
preplace portBus GPIO2_IO_O -pg 1 -y 1090 -defaultsOSRD
707 
preplace portBus GPIO_IO_T -pg 1 -y 1030 -defaultsOSRD
708 
preplace portBus HOST_MAC0 -pg 1 -y 2320 -defaultsOSRD
709 
preplace portBus GPIO_IO_I -pg 1 -y 590 -defaultsOSRD
710 
preplace portBus HOST_MAC1 -pg 1 -y 2340 -defaultsOSRD
711 
preplace portBus HOST_IP -pg 1 -y 2380 -defaultsOSRD
712 
preplace portBus GPIO2_IO_T -pg 1 -y 1110 -defaultsOSRD
713 
preplace portBus VERSION_GPIO -pg 1 -y 310 -defaultsOSRD
714 
preplace portBus GPIO2_IO_I -pg 1 -y 610 -defaultsOSRD
715 
preplace portBus GPIO_IO_O -pg 1 -y 1010 -defaultsOSRD
716 
preplace portBus HOST_IP_NETMASK -pg 1 -y 2400 -defaultsOSRD
717 
preplace inst rst_mig_7series_0_100M -pg 1 -lvl 4 -y -1370 -defaultsOSRD
718 
preplace inst axi_iic_0 -pg 1 -lvl 4 -y 690 -defaultsOSRD
719 
preplace inst mig_7series_0 -pg 1 -lvl 4 -y -1160 -defaultsOSRD
720 
preplace inst version_slice_0 -pg 1 -lvl 3 -y 310 -defaultsOSRD
721 
preplace inst microblaze_0_axi_periph -pg 1 -lvl 4 -y -370 -defaultsOSRD
722 
preplace inst version_slice_1 -pg 1 -lvl 3 -y 390 -defaultsOSRD
723 
preplace inst proc_sys_reset_0 -pg 1 -lvl 4 -y -1580 -defaultsOSRD
724 
preplace inst microblaze_0_int_concat -pg 1 -lvl 4 -y 300 -defaultsOSRD
725 
preplace inst axi_timer_0 -pg 1 -lvl 4 -y -930 -defaultsOSRD
726 
preplace inst axi_gpio_0 -pg 1 -lvl 4 -y 1040 -defaultsOSRD
727 
preplace inst microblaze_0_axi_intc -pg 1 -lvl 5 -y -140 -defaultsOSRD
728 
preplace inst mdm_1 -pg 1 -lvl 2 -y -330 -defaultsOSRD
729 
preplace inst mdio_master_top_0 -pg 1 -lvl 4 -y 1550 -defaultsOSRD
730 
preplace inst axi_gpio_1_version -pg 1 -lvl 4 -y 510 -defaultsOSRD
731 
preplace inst Const_no_ext_rst -pg 1 -lvl 3 -y -1370 -defaultsOSRD
732 
preplace inst microblaze_0 -pg 1 -lvl 3 -y -330 -defaultsOSRD
733 
preplace inst axi_uartlite_0 -pg 1 -lvl 4 -y 1320 -defaultsOSRD
734 
preplace inst clk_wiz_0 -pg 1 -lvl 1 -y -1060 -defaultsOSRD
735 
preplace inst microblaze_0_local_memory -pg 1 -lvl 4 -y 140 -defaultsOSRD
736 
preplace inst axi_quad_spi_0 -pg 1 -lvl 4 -y 830 -defaultsOSRD
737 
preplace inst axi_interconnect_0_ddr -pg 1 -lvl 3 -y -980 -defaultsOSRD
738 
preplace inst axi_gpio_2_netInfo -pg 1 -lvl 4 -y 2350 -defaultsOSRD
739 
preplace netloc axi_quad_spi_0_SPI_0 1 4 2 NJ 810 NJ
740 
preplace netloc axi_interconnect_0_ddr_M00_AXI 1 3 1 1250J
741 
preplace netloc mig_7series_0_mmcm_locked 1 3 2 1400 -1250 2020
742 
preplace netloc microblaze_0_axi_periph_M08_AXI 1 3 2 1400 -1030 2050
743 
preplace netloc microblaze_0_axi_periph_M04_AXI 1 3 2 1380 20 2070
744 
preplace netloc xlslice_1_Dout 1 3 2 NJ 390 2050
745 
preplace netloc sys_clk_i_1 1 0 4 -130J -1190 NJ -1190 NJ -1190 1240J
746 
preplace netloc gpio2_io_i_1 1 0 5 NJ 610 NJ 610 NJ 610 NJ 610 2020
747 
preplace netloc clk_wiz_0_locked 1 1 3 180 -1540 NJ -1540 NJ
748 
preplace netloc axi_gpio_2_netInfo_gpio2_io_o 1 4 2 NJ 2380 NJ
749 
preplace netloc Const_no_ext_rst_dout 1 3 1 1310J
750 
preplace netloc mig_7series_0_DDR3 1 4 2 NJ -1200 NJ
751 
preplace netloc microblaze_0_intr 1 4 1 2140J
752 
preplace netloc axi_uartlite_0_interrupt 1 3 2 1410 420 2070
753 
preplace netloc axi_iic_0_iic2intc_irpt 1 3 2 1430 410 2040
754 
preplace netloc axi_gpio_0_gpio2_io_t 1 4 2 NJ 1110 NJ
755 
preplace netloc microblaze_0_interrupt 1 2 4 590J -70 NJ -70 2120J -220 2420
756 
preplace netloc microblaze_0_intc_axi 1 4 1 2130J
757 
preplace netloc microblaze_0_axi_periph_M06_AXI 1 3 2 1360 -10 2020
758 
preplace netloc microblaze_0_axi_periph_M03_AXI 1 3 2 1370 10 2080
759 
preplace netloc gpio_io_i_1 1 0 5 NJ 590 NJ 590 NJ 590 NJ 590 2030
760 
preplace netloc microblaze_0_ilmb_1 1 3 1 1260J
761 
preplace netloc microblaze_0_M_AXI_DC 1 2 2 560 -760 1240
762 
preplace netloc mdm_1_M_AXI 1 2 1 510J
763 
preplace netloc mdm_1_LMB_0 1 2 2 530J 140 NJ
764 
preplace netloc mdm_1_Interrupt 1 2 2 510J 260 NJ
765 
preplace netloc axi_gpio_2_netInfo_gpio_io_o 1 4 2 NJ 2320 NJ
766 
preplace netloc microblaze_0_axi_periph_M05_AXI 1 3 2 1330 -20 2030
767 
preplace netloc microblaze_0_axi_dp 1 3 1 1300J
768 
preplace netloc proc_sys_reset_0_interconnect_aresetn 1 2 3 590J -790 1310J -790 2070
769 
preplace netloc mig_7series_0_ui_clk1 1 2 3 580J -1270 1240J -1270 2030
770 
preplace netloc mig_7series_0_ui_clk 1 1 5 160 -750 550J -750 1290J -750 2140 -750 2430
771 
preplace netloc axi_gpio_2_netInfo_gpio2_io_t 1 4 2 NJ 2400 NJ
772 
preplace netloc mdio_master_top_0_mdio 1 4 2 NJ 1550 NJ
773 
preplace netloc rst_mig_7series_0_100M_peripheral_aresetn 1 1 4 170J -780 530J -780 1320J -780 2110J
774 
preplace netloc rst_mig_7series_0_100M_interconnect_aresetn 1 3 2 1400 -1670 2060
775 
preplace netloc axi_gpio_0_gpio_io_o 1 4 2 NJ 1010 NJ
776 
preplace netloc microblaze_0_axi_periph_M01_AXI 1 3 2 1340 0 2090
777 
preplace netloc microblaze_0_M_AXI_IC 1 2 2 570 -770 1250
778 
preplace netloc VERSION_GPIO_1 1 0 3 NJ 310 NJ 310 550J
779 
preplace netloc axi_uartlite_0_UART 1 4 2 NJ 1310 NJ
780 
preplace netloc axi_iic_0_IIC 1 4 2 NJ 670 NJ
781 
preplace netloc rst_mig_7series_0_100M_mb_reset 1 2 3 600J -40 1280J -40 2100
782 
preplace netloc mig_7series_0_ui_clk_sync_rst 1 3 2 1390 -1280 2050
783 
preplace netloc mdm_1_Debug_SYS_Rst 1 2 2 520J -1560 NJ
784 
preplace netloc microblaze_0_dlmb_1 1 3 1 1270J
785 
preplace netloc microblaze_0_axi_periph_M07_AXI 1 3 2 1400 30 2060
786 
preplace netloc microblaze_0_axi_periph_M02_AXI 1 1 4 180J -60 NJ -60 NJ -60 2040
787 
preplace netloc axi_gpio_2_netInfo_gpio_io_t 1 4 2 NJ 2340 NJ
788 
preplace netloc axi_gpio_0_gpio2_io_o 1 4 2 NJ 1090 NJ
789 
preplace netloc M00_ARESETN_1 1 2 3 600J -800 1310J -800 2060
790 
preplace netloc microblaze_0_debug 1 2 1 540J
791 
preplace netloc axi_quad_spi_0_ip2intc_irpt 1 3 2 1420 400 2060
792 
preplace netloc microblaze_0_axi_periph_M09_AXI 1 3 2 1350 40 2050
793 
preplace netloc xlslice_0_Dout 1 3 2 1250J 430 2020
794 
preplace netloc axi_timer_0_interrupt 1 3 2 1390 -1050 2020
795 
preplace netloc axi_gpio_0_gpio_io_t 1 4 2 NJ 1030 NJ
796 
levelinfo -pg 1 -150 80 380 1020 1860 2310 2490 -top -1690 -bot 2650
797 
",
798 
}
799 
 
800 
  # Restore current instance
801 
  current_bd_instance $oldCurInst
802 
 
803 
  save_bd_design
804 
}
805 
# End of create_root_design()
806 
 
807 
 
808 
##################################################################
809 
# MAIN FLOW
810 
##################################################################
811 
 
812 
create_root_design ""
813 
 
814 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.