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DFC |
#
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# Vivado (TM) v2016.4 (64-bit)
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#
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# recreate_project.tcl: Tcl script for re-creating project 'eth_example'
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#
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# Generated by Vivado on Tue Apr 18 13:54:10 +0200 2017
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# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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# file in the Vivado Tcl Shell.
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#
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# * Note that the runs in the created project will be configured the same way as the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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#
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#*****************************************************************************************
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# NOTE: In order to use this script for source control purposes, please make sure that the
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# following files are added to the source control system:-
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#
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# 1. This project restoration tcl script (recreate_project.tcl) that was generated.
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#
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/hdl/udp_ip_10g_test_app.vhd"
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/bd/main_bd/main_bd.bd"
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/ip/rxaui_0/rxaui_0.xci"
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/hdl/xenie_eth_example.vhd"
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/bd/main_bd/ip/main_bd_mig_7series_0_0/mig_b.prj"
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/ip/udp_ip_10g_0/udp_ip_10g_0.xci"
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# "C:/projects/dfc/xenie/Eth_example/trunk/src/constr/xenie_1_0.xdc"
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# <none>
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#
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#*****************************************************************************************
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# Set the reference directory to where the script is
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set origin_dir [file normalize [file dirname [info script]]]
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# Use origin directory path location variable, if specified in the tcl shell
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if { [info exists ::origin_dir_loc] } {
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set origin_dir $::origin_dir_loc
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}
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variable script_file
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set script_file "recreate_project.tcl"
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# Help information for this script
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proc help {} {
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variable script_file
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puts "\nDescription:"
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puts "Recreate a Vivado project from this script. The created project will be"
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puts "functionally equivalent to the original project for which this script was"
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puts "generated. The script contains commands for creating a project, filesets,"
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puts "runs, adding/importing sources and setting properties on various objects.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file -tclargs \[--origin_dir <path>\]"
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puts "$script_file -tclargs \[--help\]\n"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
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puts " origin_dir path value is \".\", otherwise, the value"
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puts " that was set with the \"-paths_relative_to\" switch"
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puts " when this script was generated.\n"
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puts "\[--help\] Print help information for this script"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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}
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if { $::argc > 0 } {
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for {set i 0} {$i < [llength $::argc]} {incr i} {
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set option [string trim [lindex $::argv $i]]
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switch -regexp -- $option {
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"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
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"--help" { help }
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default {
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if { [regexp {^-} $option] } {
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puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
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return 1
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}
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}
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}
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}
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}
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# Set the directory path for the original project from where this script was exported
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set orig_proj_dir "[file normalize "$origin_dir/../../vivado"]"
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# Create project
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create_project eth_example $orig_proj_dir
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# Set the directory path for the new project
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set proj_dir [get_property directory [current_project]]
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# Reconstruct message rules
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# None
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# Set project properties
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set obj [get_projects eth_example]
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set_property "board_part" "" $obj
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set_property "compxlib.activehdl_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/activehdl" $obj
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set_property "compxlib.funcsim" "1" $obj
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set_property "compxlib.ies_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/ies" $obj
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set_property "compxlib.modelsim_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/modelsim" $obj
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set_property "compxlib.overwrite_libs" "0" $obj
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set_property "compxlib.questa_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/questa" $obj
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set_property "compxlib.riviera_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/riviera" $obj
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set_property "compxlib.timesim" "1" $obj
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set_property "compxlib.vcs_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/vcs" $obj
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set_property "compxlib.xsim_compiled_library_dir" "" $obj
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set_property "corecontainer.enable" "0" $obj
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set_property "default_lib" "xil_defaultlib" $obj
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set_property "dsa.num_compute_units" "16" $obj
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set_property "enable_optional_runs_sta" "0" $obj
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set_property "generate_ip_upgrade_log" "1" $obj
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set_property "ip_cache_permissions" "read write" $obj
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set_property "ip_output_repo" "$proj_dir/eth_example.cache/ip" $obj
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set_property "managed_ip" "0" $obj
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set_property "part" "xc7k70tfbg676-1" $obj
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set_property "pr_flow" "0" $obj
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set_property "sim.ip.auto_export_scripts" "1" $obj
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set_property "sim.use_ip_compiled_libs" "1" $obj
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set_property "simulator_language" "Mixed" $obj
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set_property "source_mgmt_mode" "All" $obj
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set_property "target_language" "VHDL" $obj
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set_property "target_simulator" "XSim" $obj
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set_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY" $obj
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set_property "xsim.array_display_limit" "64" $obj
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set_property "xsim.radix" "hex" $obj
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set_property "xsim.time_unit" "ns" $obj
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set_property "xsim.trace_limit" "65536" $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Set IP repository paths
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set obj [get_filesets sources_1]
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set_property "ip_repo_paths" "[file normalize "$origin_dir/../../ip_repo"]" $obj
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# Rebuild user ip_repo's index before adding any source files
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update_ip_catalog -rebuild
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# Create Block Design
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set old_path [pwd]
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cd $origin_dir/../
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proc wrap_recreate_bd {run_dir} {
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source $run_dir/recreate_bd.tcl
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# Generate the wrapper (unused)
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#set design_name [get_bd_designs]
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#make_wrapper -files [get_files $design_name.bd] -top -import
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}
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wrap_recreate_bd $origin_dir
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cd $old_path
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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"[file normalize "$origin_dir/../hdl/udp_ip_10g_test_app.vhd"]"\
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"[file normalize "$origin_dir/../bd/main_bd/main_bd.bd"]"\
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"[file normalize "$origin_dir/../ip/rxaui_0/rxaui_0.xci"]"\
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"[file normalize "$origin_dir/../hdl/xenie_eth_example.vhd"]"\
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"[file normalize "$origin_dir/../bd/main_bd/ip/main_bd_mig_7series_0_0/mig_b.prj"]"\
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]
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add_files -norecurse -fileset $obj $files
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# Set 'sources_1' fileset file properties for remote files
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# None
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# Set 'sources_1' fileset file properties for local files
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set file "hdl/udp_ip_10g_test_app.vhd"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property "file_type" "VHDL" $file_obj
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set_property "is_enabled" "1" $file_obj
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set_property "is_global_include" "0" $file_obj
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set_property "library" "xil_defaultlib" $file_obj
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set_property "path_mode" "RelativeFirst" $file_obj
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set_property "used_in" "synthesis simulation" $file_obj
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set_property "used_in_simulation" "1" $file_obj
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set_property "used_in_synthesis" "1" $file_obj
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| 194 |
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set file "main_bd/main_bd.bd"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property "exclude_debug_logic" "0" $file_obj
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if { ![get_property "is_locked" $file_obj] } {
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set_property "generate_synth_checkpoint" "1" $file_obj
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}
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set_property "is_enabled" "1" $file_obj
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| 201 |
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set_property "is_global_include" "0" $file_obj
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if { ![get_property "is_locked" $file_obj] } {
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set_property "is_locked" "0" $file_obj
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}
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| 205 |
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set_property "library" "xil_defaultlib" $file_obj
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| 206 |
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set_property "path_mode" "RelativeFirst" $file_obj
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if { ![get_property "is_locked" $file_obj] } {
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| 208 |
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set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
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| 209 |
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}
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| 210 |
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set_property "used_in" "synthesis implementation simulation" $file_obj
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| 211 |
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set_property "used_in_implementation" "1" $file_obj
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| 212 |
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set_property "used_in_simulation" "1" $file_obj
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| 213 |
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set_property "used_in_synthesis" "1" $file_obj
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| 214 |
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| 215 |
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set file "rxaui_0/rxaui_0.xci"
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| 216 |
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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| 217 |
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set_property "is_enabled" "1" $file_obj
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| 218 |
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set_property "is_global_include" "0" $file_obj
|
| 219 |
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set_property "library" "xil_defaultlib" $file_obj
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| 220 |
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set_property "path_mode" "RelativeFirst" $file_obj
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| 221 |
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set_property "used_in" "synthesis implementation simulation" $file_obj
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| 222 |
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set_property "used_in_implementation" "1" $file_obj
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| 223 |
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set_property "used_in_simulation" "1" $file_obj
|
| 224 |
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set_property "used_in_synthesis" "1" $file_obj
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| 225 |
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| 226 |
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set file "hdl/xenie_eth_example.vhd"
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| 227 |
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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| 228 |
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set_property "file_type" "VHDL" $file_obj
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| 229 |
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set_property "is_enabled" "1" $file_obj
|
| 230 |
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set_property "is_global_include" "0" $file_obj
|
| 231 |
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set_property "library" "xil_defaultlib" $file_obj
|
| 232 |
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set_property "path_mode" "RelativeFirst" $file_obj
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| 233 |
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set_property "used_in" "synthesis simulation" $file_obj
|
| 234 |
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set_property "used_in_simulation" "1" $file_obj
|
| 235 |
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set_property "used_in_synthesis" "1" $file_obj
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| 236 |
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|
| 237 |
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set file "main_bd_mig_7series_0_0/mig_b.prj"
|
| 238 |
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
| 239 |
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set_property "is_enabled" "1" $file_obj
|
| 240 |
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set_property "is_global_include" "0" $file_obj
|
| 241 |
|
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set_property "library" "xil_defaultlib" $file_obj
|
| 242 |
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set_property "path_mode" "RelativeFirst" $file_obj
|
| 243 |
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set_property "scoped_to_cells" "" $file_obj
|
| 244 |
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set_property "scoped_to_ref" "" $file_obj
|
| 245 |
|
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set_property "used_in" "synthesis" $file_obj
|
| 246 |
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set_property "used_in_synthesis" "1" $file_obj
|
| 247 |
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|
| 248 |
|
|
|
| 249 |
|
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# Set 'sources_1' fileset properties
|
| 250 |
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set obj [get_filesets sources_1]
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| 251 |
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set_property "design_mode" "RTL" $obj
|
| 252 |
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set_property "edif_extra_search_paths" "" $obj
|
| 253 |
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set_property "elab_link_dcps" "1" $obj
|
| 254 |
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set_property "elab_load_timing_constraints" "1" $obj
|
| 255 |
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set_property "generic" "" $obj
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| 256 |
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set_property "include_dirs" "" $obj
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| 257 |
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set_property "lib_map_file" "" $obj
|
| 258 |
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set_property "loop_count" "1000" $obj
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| 259 |
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set_property "name" "sources_1" $obj
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| 260 |
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set_property "top" "xenie_eth_example" $obj
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| 261 |
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set_property "verilog_define" "" $obj
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| 262 |
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set_property "verilog_uppercase" "0" $obj
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| 263 |
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| 264 |
|
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# Set 'sources_1' fileset object
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| 265 |
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set obj [get_filesets sources_1]
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| 266 |
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set files [list \
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| 267 |
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"[file normalize "$origin_dir/../ip/udp_ip_10g_0/udp_ip_10g_0.xci"]"\
|
| 268 |
|
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]
|
| 269 |
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add_files -norecurse -fileset $obj $files
|
| 270 |
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|
| 271 |
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# Set 'sources_1' fileset file properties for remote files
|
| 272 |
|
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# None
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| 273 |
|
|
|
| 274 |
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# Set 'sources_1' fileset file properties for local files
|
| 275 |
|
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set file "udp_ip_10g_0/udp_ip_10g_0.xci"
|
| 276 |
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
| 277 |
|
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if { ![get_property "is_locked" $file_obj] } {
|
| 278 |
|
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set_property "generate_synth_checkpoint" "1" $file_obj
|
| 279 |
|
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}
|
| 280 |
|
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set_property "is_enabled" "1" $file_obj
|
| 281 |
|
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set_property "is_global_include" "0" $file_obj
|
| 282 |
|
|
set_property "library" "xil_defaultlib" $file_obj
|
| 283 |
|
|
set_property "path_mode" "RelativeFirst" $file_obj
|
| 284 |
|
|
set_property "used_in" "synthesis implementation simulation" $file_obj
|
| 285 |
|
|
set_property "used_in_implementation" "1" $file_obj
|
| 286 |
|
|
set_property "used_in_simulation" "1" $file_obj
|
| 287 |
|
|
set_property "used_in_synthesis" "1" $file_obj
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
# Create 'constrs_1' fileset (if not found)
|
| 291 |
|
|
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
| 292 |
|
|
create_fileset -constrset constrs_1
|
| 293 |
|
|
}
|
| 294 |
|
|
|
| 295 |
|
|
# Set 'constrs_1' fileset object
|
| 296 |
|
|
set obj [get_filesets constrs_1]
|
| 297 |
|
|
|
| 298 |
|
|
# Add/Import constrs file and set constrs file properties
|
| 299 |
|
|
set file "[file normalize "$origin_dir/../constr/xenie_1_0.xdc"]"
|
| 300 |
|
|
set file_added [add_files -norecurse -fileset $obj $file]
|
| 301 |
|
|
set file "constr/xenie_1_0.xdc"
|
| 302 |
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
| 303 |
|
|
set_property "file_type" "XDC" $file_obj
|
| 304 |
|
|
set_property "is_enabled" "1" $file_obj
|
| 305 |
|
|
set_property "is_global_include" "0" $file_obj
|
| 306 |
|
|
set_property "library" "xil_defaultlib" $file_obj
|
| 307 |
|
|
set_property "path_mode" "RelativeFirst" $file_obj
|
| 308 |
|
|
set_property "processing_order" "NORMAL" $file_obj
|
| 309 |
|
|
set_property "scoped_to_cells" "" $file_obj
|
| 310 |
|
|
set_property "scoped_to_ref" "" $file_obj
|
| 311 |
|
|
set_property "used_in" "synthesis implementation" $file_obj
|
| 312 |
|
|
set_property "used_in_implementation" "1" $file_obj
|
| 313 |
|
|
set_property "used_in_synthesis" "1" $file_obj
|
| 314 |
|
|
|
| 315 |
|
|
# Set 'constrs_1' fileset properties
|
| 316 |
|
|
set obj [get_filesets constrs_1]
|
| 317 |
|
|
set_property "name" "constrs_1" $obj
|
| 318 |
|
|
set_property "target_constrs_file" "[file normalize "$origin_dir/../constr/xenie_1_0.xdc"]" $obj
|
| 319 |
|
|
|
| 320 |
|
|
# Create 'sim_1' fileset (if not found)
|
| 321 |
|
|
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
| 322 |
|
|
create_fileset -simset sim_1
|
| 323 |
|
|
}
|
| 324 |
|
|
|
| 325 |
|
|
# Set 'sim_1' fileset object
|
| 326 |
|
|
set obj [get_filesets sim_1]
|
| 327 |
|
|
# Empty (no sources present)
|
| 328 |
|
|
|
| 329 |
|
|
# Set 'sim_1' fileset properties
|
| 330 |
|
|
set obj [get_filesets sim_1]
|
| 331 |
|
|
set_property "generic" "" $obj
|
| 332 |
|
|
set_property "include_dirs" "" $obj
|
| 333 |
|
|
set_property "name" "sim_1" $obj
|
| 334 |
|
|
set_property "nl.cell" "" $obj
|
| 335 |
|
|
set_property "nl.incl_unisim_models" "0" $obj
|
| 336 |
|
|
set_property "nl.process_corner" "slow" $obj
|
| 337 |
|
|
set_property "nl.rename_top" "" $obj
|
| 338 |
|
|
set_property "nl.sdf_anno" "1" $obj
|
| 339 |
|
|
set_property "nl.write_all_overrides" "0" $obj
|
| 340 |
|
|
set_property "runtime" "1000ns" $obj
|
| 341 |
|
|
set_property "source_set" "sources_1" $obj
|
| 342 |
|
|
set_property "top" "xenie_eth_example" $obj
|
| 343 |
|
|
set_property "transport_int_delay" "0" $obj
|
| 344 |
|
|
set_property "transport_path_delay" "0" $obj
|
| 345 |
|
|
set_property "unit_under_test" "" $obj
|
| 346 |
|
|
set_property "verilog_define" "" $obj
|
| 347 |
|
|
set_property "verilog_uppercase" "0" $obj
|
| 348 |
|
|
set_property "xelab.debug_level" "typical" $obj
|
| 349 |
|
|
set_property "xelab.dll" "0" $obj
|
| 350 |
|
|
set_property "xelab.load_glbl" "1" $obj
|
| 351 |
|
|
set_property "xelab.more_options" "" $obj
|
| 352 |
|
|
set_property "xelab.mt_level" "auto" $obj
|
| 353 |
|
|
set_property "xelab.nosort" "1" $obj
|
| 354 |
|
|
set_property "xelab.rangecheck" "0" $obj
|
| 355 |
|
|
set_property "xelab.relax" "1" $obj
|
| 356 |
|
|
set_property "xelab.sdf_delay" "sdfmax" $obj
|
| 357 |
|
|
set_property "xelab.snapshot" "" $obj
|
| 358 |
|
|
set_property "xelab.unifast" "" $obj
|
| 359 |
|
|
set_property "xsim.compile.incremental" "0" $obj
|
| 360 |
|
|
set_property "xsim.compile.xvhdl.more_options" "" $obj
|
| 361 |
|
|
set_property "xsim.compile.xvhdl.nosort" "1" $obj
|
| 362 |
|
|
set_property "xsim.compile.xvhdl.relax" "1" $obj
|
| 363 |
|
|
set_property "xsim.compile.xvlog.more_options" "" $obj
|
| 364 |
|
|
set_property "xsim.compile.xvlog.nosort" "1" $obj
|
| 365 |
|
|
set_property "xsim.compile.xvlog.relax" "1" $obj
|
| 366 |
|
|
set_property "xsim.elaborate.debug_level" "typical" $obj
|
| 367 |
|
|
set_property "xsim.elaborate.load_glbl" "1" $obj
|
| 368 |
|
|
set_property "xsim.elaborate.mt_level" "auto" $obj
|
| 369 |
|
|
set_property "xsim.elaborate.rangecheck" "0" $obj
|
| 370 |
|
|
set_property "xsim.elaborate.relax" "1" $obj
|
| 371 |
|
|
set_property "xsim.elaborate.sdf_delay" "sdfmax" $obj
|
| 372 |
|
|
set_property "xsim.elaborate.snapshot" "" $obj
|
| 373 |
|
|
set_property "xsim.elaborate.xelab.more_options" "" $obj
|
| 374 |
|
|
set_property "xsim.more_options" "" $obj
|
| 375 |
|
|
set_property "xsim.saif" "" $obj
|
| 376 |
|
|
set_property "xsim.simulate.log_all_signals" "0" $obj
|
| 377 |
|
|
set_property "xsim.simulate.runtime" "1000ns" $obj
|
| 378 |
|
|
set_property "xsim.simulate.saif" "" $obj
|
| 379 |
|
|
set_property "xsim.simulate.saif_all_signals" "0" $obj
|
| 380 |
|
|
set_property "xsim.simulate.saif_scope" "" $obj
|
| 381 |
|
|
set_property "xsim.simulate.wdb" "" $obj
|
| 382 |
|
|
set_property "xsim.simulate.xsim.more_options" "" $obj
|
| 383 |
|
|
set_property "xsim.tclbatch" "" $obj
|
| 384 |
|
|
set_property "xsim.wdb" "" $obj
|
| 385 |
|
|
|
| 386 |
|
|
# Create 'synth_1' run (if not found)
|
| 387 |
|
|
if {[string equal [get_runs -quiet synth_1] ""]} {
|
| 388 |
|
|
create_run -name synth_1 -part xc7k70tfbg676-1 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
|
| 389 |
|
|
} else {
|
| 390 |
|
|
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
| 391 |
|
|
set_property flow "Vivado Synthesis 2016" [get_runs synth_1]
|
| 392 |
|
|
}
|
| 393 |
|
|
set obj [get_runs synth_1]
|
| 394 |
|
|
set_property "constrset" "constrs_1" $obj
|
| 395 |
|
|
set_property "description" "Vivado Synthesis Defaults" $obj
|
| 396 |
|
|
set_property "flow" "Vivado Synthesis 2016" $obj
|
| 397 |
|
|
set_property "name" "synth_1" $obj
|
| 398 |
|
|
set_property "needs_refresh" "1" $obj
|
| 399 |
|
|
set_property "part" "xc7k70tfbg676-1" $obj
|
| 400 |
|
|
set_property "srcset" "sources_1" $obj
|
| 401 |
|
|
set_property "strategy" "Vivado Synthesis Defaults" $obj
|
| 402 |
|
|
set_property "incremental_checkpoint" "" $obj
|
| 403 |
|
|
set_property "include_in_archive" "1" $obj
|
| 404 |
|
|
set_property "steps.synth_design.tcl.pre" "[file normalize "$origin_dir/setCompileTime.tcl"]" $obj
|
| 405 |
|
|
set_property "steps.synth_design.tcl.post" "" $obj
|
| 406 |
|
|
set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
|
| 407 |
|
|
set_property "steps.synth_design.args.gated_clock_conversion" "off" $obj
|
| 408 |
|
|
set_property "steps.synth_design.args.bufg" "12" $obj
|
| 409 |
|
|
set_property "steps.synth_design.args.fanout_limit" "10000" $obj
|
| 410 |
|
|
set_property "steps.synth_design.args.directive" "Default" $obj
|
| 411 |
|
|
set_property "steps.synth_design.args.retiming" "0" $obj
|
| 412 |
|
|
set_property "steps.synth_design.args.fsm_extraction" "auto" $obj
|
| 413 |
|
|
set_property "steps.synth_design.args.keep_equivalent_registers" "0" $obj
|
| 414 |
|
|
set_property "steps.synth_design.args.resource_sharing" "auto" $obj
|
| 415 |
|
|
set_property "steps.synth_design.args.control_set_opt_threshold" "auto" $obj
|
| 416 |
|
|
set_property "steps.synth_design.args.no_lc" "0" $obj
|
| 417 |
|
|
set_property "steps.synth_design.args.no_srlextract" "0" $obj
|
| 418 |
|
|
set_property "steps.synth_design.args.shreg_min_size" "3" $obj
|
| 419 |
|
|
set_property "steps.synth_design.args.max_bram" "-1" $obj
|
| 420 |
|
|
set_property "steps.synth_design.args.max_uram" "-1" $obj
|
| 421 |
|
|
set_property "steps.synth_design.args.max_dsp" "-1" $obj
|
| 422 |
|
|
set_property "steps.synth_design.args.max_bram_cascade_height" "-1" $obj
|
| 423 |
|
|
set_property "steps.synth_design.args.max_uram_cascade_height" "-1" $obj
|
| 424 |
|
|
set_property "steps.synth_design.args.cascade_dsp" "auto" $obj
|
| 425 |
|
|
set_property "steps.synth_design.args.assert" "0" $obj
|
| 426 |
|
|
set_property -name {steps.synth_design.args.more options} -value {-generic g_compilation_date=$compileTime} -objects $obj
|
| 427 |
|
|
|
| 428 |
|
|
# set the current synth run
|
| 429 |
|
|
current_run -synthesis [get_runs synth_1]
|
| 430 |
|
|
|
| 431 |
|
|
# Create 'impl_1' run (if not found)
|
| 432 |
|
|
if {[string equal [get_runs -quiet impl_1] ""]} {
|
| 433 |
|
|
create_run -name impl_1 -part xc7k70tfbg676-1 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
|
| 434 |
|
|
} else {
|
| 435 |
|
|
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
| 436 |
|
|
set_property flow "Vivado Implementation 2016" [get_runs impl_1]
|
| 437 |
|
|
}
|
| 438 |
|
|
set obj [get_runs impl_1]
|
| 439 |
|
|
set_property "constrset" "constrs_1" $obj
|
| 440 |
|
|
set_property "description" "Default settings for Implementation." $obj
|
| 441 |
|
|
set_property "flow" "Vivado Implementation 2016" $obj
|
| 442 |
|
|
set_property "name" "impl_1" $obj
|
| 443 |
|
|
set_property "needs_refresh" "1" $obj
|
| 444 |
|
|
set_property "part" "xc7k70tfbg676-1" $obj
|
| 445 |
|
|
set_property "pr_configuration" "" $obj
|
| 446 |
|
|
set_property "srcset" "sources_1" $obj
|
| 447 |
|
|
set_property "strategy" "Vivado Implementation Defaults" $obj
|
| 448 |
|
|
set_property "incremental_checkpoint" "" $obj
|
| 449 |
|
|
set_property "include_in_archive" "1" $obj
|
| 450 |
|
|
set_property "steps.opt_design.is_enabled" "1" $obj
|
| 451 |
|
|
set_property "steps.opt_design.tcl.pre" "" $obj
|
| 452 |
|
|
set_property "steps.opt_design.tcl.post" "" $obj
|
| 453 |
|
|
set_property "steps.opt_design.args.verbose" "0" $obj
|
| 454 |
|
|
set_property "steps.opt_design.args.directive" "Default" $obj
|
| 455 |
|
|
set_property -name {steps.opt_design.args.more options} -value {} -objects $obj
|
| 456 |
|
|
set_property "steps.power_opt_design.is_enabled" "0" $obj
|
| 457 |
|
|
set_property "steps.power_opt_design.tcl.pre" "" $obj
|
| 458 |
|
|
set_property "steps.power_opt_design.tcl.post" "" $obj
|
| 459 |
|
|
set_property -name {steps.power_opt_design.args.more options} -value {} -objects $obj
|
| 460 |
|
|
set_property "steps.place_design.tcl.pre" "" $obj
|
| 461 |
|
|
set_property "steps.place_design.tcl.post" "" $obj
|
| 462 |
|
|
set_property "steps.place_design.args.directive" "Default" $obj
|
| 463 |
|
|
set_property -name {steps.place_design.args.more options} -value {} -objects $obj
|
| 464 |
|
|
set_property "steps.post_place_power_opt_design.is_enabled" "0" $obj
|
| 465 |
|
|
set_property "steps.post_place_power_opt_design.tcl.pre" "" $obj
|
| 466 |
|
|
set_property "steps.post_place_power_opt_design.tcl.post" "" $obj
|
| 467 |
|
|
set_property -name {steps.post_place_power_opt_design.args.more options} -value {} -objects $obj
|
| 468 |
|
|
set_property "steps.phys_opt_design.is_enabled" "0" $obj
|
| 469 |
|
|
set_property "steps.phys_opt_design.tcl.pre" "" $obj
|
| 470 |
|
|
set_property "steps.phys_opt_design.tcl.post" "" $obj
|
| 471 |
|
|
set_property "steps.phys_opt_design.args.directive" "Default" $obj
|
| 472 |
|
|
set_property -name {steps.phys_opt_design.args.more options} -value {} -objects $obj
|
| 473 |
|
|
set_property "steps.route_design.tcl.pre" "" $obj
|
| 474 |
|
|
set_property "steps.route_design.tcl.post" "" $obj
|
| 475 |
|
|
set_property "steps.route_design.args.directive" "Default" $obj
|
| 476 |
|
|
set_property -name {steps.route_design.args.more options} -value {} -objects $obj
|
| 477 |
|
|
set_property "steps.post_route_phys_opt_design.is_enabled" "0" $obj
|
| 478 |
|
|
set_property "steps.post_route_phys_opt_design.tcl.pre" "" $obj
|
| 479 |
|
|
set_property "steps.post_route_phys_opt_design.tcl.post" "" $obj
|
| 480 |
|
|
set_property "steps.post_route_phys_opt_design.args.directive" "Default" $obj
|
| 481 |
|
|
set_property -name {steps.post_route_phys_opt_design.args.more options} -value {} -objects $obj
|
| 482 |
|
|
set_property "steps.write_bitstream.tcl.pre" "" $obj
|
| 483 |
|
|
set_property "steps.write_bitstream.tcl.post" "" $obj
|
| 484 |
|
|
set_property "steps.write_bitstream.args.raw_bitfile" "0" $obj
|
| 485 |
|
|
set_property "steps.write_bitstream.args.mask_file" "0" $obj
|
| 486 |
|
|
set_property "steps.write_bitstream.args.no_binary_bitfile" "0" $obj
|
| 487 |
|
|
set_property "steps.write_bitstream.args.bin_file" "0" $obj
|
| 488 |
|
|
set_property "steps.write_bitstream.args.readback_file" "0" $obj
|
| 489 |
|
|
set_property "steps.write_bitstream.args.logic_location_file" "0" $obj
|
| 490 |
|
|
set_property "steps.write_bitstream.args.verbose" "0" $obj
|
| 491 |
|
|
set_property -name {steps.write_bitstream.args.more options} -value {} -objects $obj
|
| 492 |
|
|
|
| 493 |
|
|
# set the current impl run
|
| 494 |
|
|
current_run -implementation [get_runs impl_1]
|
| 495 |
|
|
|
| 496 |
|
|
puts "INFO: Project created:eth_example"
|
