OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [README.txt] - Blame information for rev 102

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rehayes
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
2 14 rehayes
////////////////////////////////////////////////////////////////////////////////
3
////////////////////////////////////////////////////////////////////////////////
4
// SVN tag: None
5
 
6 102 rehayes
January 27,2013
7
RTL - Commited changes to detect PC underflow/overflow as an OP-code error.
8
 
9
////////////////////////////////////////////////////////////////////////////////
10
////////////////////////////////////////////////////////////////////////////////
11
// SVN tag: None
12
 
13 89 rehayes
November 21,2011
14
RTL - No Change
15
 
16
Code cleanup, converted tabs to blanks. Added code to instruction test to cover
17
a few base instructions that weren't being tested. Changed instance name of
18
semaphore registers from "bit" to "sbit" to be compatible with System Verilog.
19
 
20
////////////////////////////////////////////////////////////////////////////////
21
////////////////////////////////////////////////////////////////////////////////
22
 
23
My current idea list for enhancements is:
24
 
25
Add to the software apps:
26 102 rehayes
a - It should be possible to write software to emulate some simple hardware
27
      modules such as I2C, SPI and UART.
28 89 rehayes
b - DMA controller software
29
c - Find open source C compiler for Xgate
30
d - ???
31
 
32 102 rehayes
It would be interesting to integrate the Xgate with some of the other OpenCores
33
  peripheral modules. Again there would be some related software development for
34
  verification. The ultimate goal would be to to create full-blown drivers for
35
  these modules.
36
a - Integrate Xgate with I2C controller and develop software to support
37
     SMBus and PMBus protocols.
38 89 rehayes
b - ???
39
 
40 102 rehayes
Another interesting integration project would be to build a processor core with
41
  the OpenRISC as the host and the Xgate working as a co-processor. Some type of
42
  memory controller module would need to be developed so the Xgate could have
43
  some semiprivate RAM to run code from. Also a separate slave bus would be
44
  nice to isolate peripherals that could be managed mostly by the Xgate. Some
45
  software development would be required for both OpenRISC and Xgate to verify
46
  the functionality.
47 89 rehayes
 
48 102 rehayes
Develop hardware debug module. Survey Freescale debugger and other debugger
49
  specifications and develop hardware debugger/specification that can optionally
50
  be connected to the Xgate module. The debugger should be broken into at least
51
  two modules, one the actual debug interface and the second a flexible serial
52
  interface adaptor. There are already JTAG modules in the design database that
53
  I had thought might be used as one possible interface to the debugger.
54
  (A great project on it's own would be to develop a JTAG module that meets the
55
  latest JTAG specification including the single wire interface.)
56 89 rehayes
 
57 102 rehayes
Upgrade Xgate to the enhanced version that Freescale now ships. This includes
58
  an alternate register set so the Xgate can switch in a few cycles from a low
59
  priority interrupt to a higher priority interrupt and then return to the low
60
  priority interrupt process.
61 89 rehayes
 
62 102 rehayes
Improvements to the architecture to support high speed operation. The current
63
  code was developed in a piecemeal fashion without much pre-planing on the
64
  data path from/to RAM and the internal registers.
65 89 rehayes
 
66
System Verilog class based constrained random verification environment.
67
 
68
////////////////////////////////////////////////////////////////////////////////
69
////////////////////////////////////////////////////////////////////////////////
70
// SVN tag: None
71
 
72 84 rehayes
August 11,2010
73
RTL - No Change
74
 
75
Applications - Added the "application" directory to the "sw" directory. The
76
    first application code added is the SKIPJACK encrypt/decrypt function. This
77
    algorithm works on a 64 bit block of data and uses an 80 bit key. See the
78
    "sw/applications/skipjack/README.txt" file for more information.
79
 
80
Testbench - To aid in software development a simple debug module was added to
81
    the testbench. The debugger loads watchpoint addresses stored in RAM after
82
    the first RAM initialization. The debugger generates trigger signals that
83
    can be watched in the waveform viewer and captures a copy of the CPU
84
    registers at each trigger event. The watch point addresses are captured by
85
    the assembler and stored in RAM addresses reserved for the test bench.
86
    There are enable registers in the testbench that can enable or disable any
87
    of the eight individual watchpoints under testbench control.
88
 
89
Doc - Made corrections to some of the example code in the detailed instruction
90
    descriptions.
91
 
92
////////////////////////////////////////////////////////////////////////////////
93
////////////////////////////////////////////////////////////////////////////////
94
// SVN tag: None
95
 
96 77 rehayes
June 10,2010
97
RTL - No Change
98
 
99
Testbench - No Change.
100
 
101
Doc - Added descriptions for interrupt bypass registers. Added Appendix B for
102
    testbench description.
103
 
104
////////////////////////////////////////////////////////////////////////////////
105
////////////////////////////////////////////////////////////////////////////////
106
// SVN tag: None
107
 
108 76 rehayes
May 18,2010
109
RTL - Fixed xlink synthesis warnings noted by Nachiket Jugade,
110
    missing else statment for chid_sm_ns line 393,
111
    missing default on shifter lines 2382 (Although all cases are covered).
112
 
113
Testbench - No Change.
114
 
115
Doc - No Change.
116
 
117
////////////////////////////////////////////////////////////////////////////////
118
////////////////////////////////////////////////////////////////////////////////
119
// SVN tag: None
120
 
121 74 rehayes
May 13,2010
122
RTL - Code cleanup. Eliminated index [0] of "xgif" and "chan_req_i" output and
123
    input pins along with assoicated status and and control registers. This
124
    channel has never been usable.
125
 
126
Testbench - Changes to match changes in RTL .
127
 
128
Doc - No Change.
129
 
130
////////////////////////////////////////////////////////////////////////////////
131
////////////////////////////////////////////////////////////////////////////////
132
// SVN tag: None
133
 
134 71 rehayes
May 12,2010
135
RTL - Added new control registers for interrupt bypass function. Out of reset
136
    all input interrupts are bypassed directly to the Xgate interrupt outputs.
137
    The interrupts are also disabled from effecting the Xgate till the bypass
138
    is disabled. The interrupt priority has been flipped so that now the lowest
139
    index input interrupt has the highest priority.
140
 
141
Testbench - Added semaphore register and read only registers to observe irq
142
    outputs of Xgate to testbench slave module. Added parameters to support new
143
    Xgate registers and testbench registers. Added new test to checkout
144
    bypass functionality and interrupt priority encoding.
145
 
146
Doc - Updated with additions of IRQ Bypass registers.
147
 
148
////////////////////////////////////////////////////////////////////////////////
149
////////////////////////////////////////////////////////////////////////////////
150
// SVN tag: None
151
 
152 66 rehayes
Apr 22,2010
153
RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
154
    All tests now pass when the RAM wait states are set from zero to four. Five
155
    wait states times out in simulation while running the last test which is
156
    a simple register test otherwise I expect it would pass.
157
 
158
Testbench - Many of the failures while testing wait states were due to fixed
159 76 rehayes
    delays coded in the testbench. As necessary, delays were changed to be a
160 66 rehayes
    function of a parameter that is based on the number of RAM wait states.
161
 
162
Doc - No change.
163
 
164
////////////////////////////////////////////////////////////////////////////////
165
////////////////////////////////////////////////////////////////////////////////
166
// SVN tag: None
167
 
168 61 rehayes
Apr 5,2010
169
RTL - First pass at fixing bug when entering DEBUG by command from the slave
170
    WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
171
    although there are errors in DEBUG mode when RAM wait states are increased.
172 76 rehayes
    Icarus Verilog version 0.9.2 now supports the "generate" command. This is
173 61 rehayes
    now used to instantiate the semaphore registers.
174
 
175
Testbench - Added capability to insert wait states on RAM access.
176
 
177
Doc - No change.
178
 
179
////////////////////////////////////////////////////////////////////////////////
180
////////////////////////////////////////////////////////////////////////////////
181
// SVN tag: None
182
 
183 58 rehayes
Feb 12,2010
184
RTL - Update to the WISHBONE interface when wait states are enabled to trade
185
   16 data flops for 5 address registers. This change now also requires single
186
   cycle timing on the WISHBONE address bus, multi-cycle timing is still
187
   allowed on the WISHBONE write data bus. In the old design WISHBONE read
188
   cycles required the address to be decoded and the read data to be latched
189
   in the first cycle and the there was a whole cycle to drive the read data
190
   bus. The new design latches the address in the first cycle then decodes the
191
   address and outputs the data in the second cycle. (The WISHBONE bus doesn't
192
   require the address or data to be latched for multi-cycle operation but by
193
   doing this it is hoped some power will be saved in the combinational logic
194
   by reducing the decoding activity at each address change.)
195
 
196
Testbench - No change.
197
 
198
Doc - No change.
199
 
200
////////////////////////////////////////////////////////////////////////////////
201
////////////////////////////////////////////////////////////////////////////////
202
// SVN tag: None
203
 
204 56 rehayes
Jan 27,2010
205
RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
206
   enabled. If a slave bus transaction was started but not completed in the
207
   second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
208
   signal to flag this input condition but not sure if it is really needed.
209
  The old testbench was "helping" the Xgate module by sending an almost
210
   continuous wbm_ack_i signal which allowed the RISC state machine to advance
211
   when it shouldn't. Changes were made to the WISHBONE master bus interface
212
   and the RISC control logic.
213
 
214
Updates to testbench -- Extensive changes to testbench. The bus arbitration
215
   module has been completely rewritten. It now completely controls access to the
216
   system bus and RAM. It internally generates a WISHBONE ack signal for the RAM.
217
   The test control registers have been moved out of the top level and put into
218
   a new WISHBONE slave module which also attaches to the system bus. The Xgate
219
   modules master and slave buses are fully integrated with the bus arbitration
220
   module and the system bus. The new testbench looks a lot more like a real
221
   system environment.
222
  To Do: Add back "random" wait state generation for RAM access.
223
 
224
Updates to User Guide -- Minor corrections to instruction set details. Needs more
225
  review on condition code settings.
226
 
227
////////////////////////////////////////////////////////////////////////////////
228
////////////////////////////////////////////////////////////////////////////////
229
// SVN tag: None
230
 
231 51 rehayes
Jan 11,2010
232 56 rehayes
RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
233 51 rehayes
  Fix Error in loading R2 durning cpu_state == BOOT_3.
234 84 rehayes
  There is a bug in DEBUG mode that is sensitive to number of preceding
235 51 rehayes
   instructions and wait states that needs to be resolved.
236
 
237
Updates to testbench --
238
 
239
Updates to User Guide -- First pass with instruction set details. Needs more
240
  review on condition code settings.
241
 
242
////////////////////////////////////////////////////////////////////////////////
243
// SVN tag: None
244
 
245 44 rehayes
Dec 08,2009
246 41 rehayes
RTL - 85% done -- Updated code so there is only one program counter adder.
247
   Updated WISHBONE Slave bus for word addressability and byte selection.
248 44 rehayes
   Deleted two stack pointer registers.
249 41 rehayes
 
250
Updates to testbench --
251
 
252
Updates to User Guide -- Minor cleanup.
253
 
254
////////////////////////////////////////////////////////////////////////////////
255
////////////////////////////////////////////////////////////////////////////////
256
// SVN tag: None
257
 
258 38 rehayes
Nov 09,2009
259
RTL - 85% done - Minor changes to Mastermode bus.
260
 
261
Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
262
   but this is not fully functional. Causes timing problems when master is
263 56 rehayes
   polling Xgate registers durning debug mode tests. Will probably change RAM
264 38 rehayes
   model to dual port in next revision.
265
   Updated master module to include WISHBONE select inputs.
266
 
267
Updates to User Guide.
268
 
269
////////////////////////////////////////////////////////////////////////////////
270
////////////////////////////////////////////////////////////////////////////////
271
// SVN tag: None
272
 
273 23 rehayes
Oct 07,2009
274
RTL - 85% done
275
All debug commands now working, including writes to XGCHID register.
276
 
277
Updates to testbench, added timeout and total error count.
278 41 rehayes
 
279
Updates to User Guide --.
280
 
281 23 rehayes
Created the sw directory and copied over the software stuff from the bench
282
directory.
283
 
284
////////////////////////////////////////////////////////////////////////////////
285
////////////////////////////////////////////////////////////////////////////////
286
// SVN tag: None
287
 
288 14 rehayes
Sept 23,2009
289
BRK instruction working. Single Step Command in debug mode working.
290
Software error interrupt added.
291
 
292
Updates to testbench.
293
New assembly code directory: debug_test
294
 
295
////////////////////////////////////////////////////////////////////////////////
296
////////////////////////////////////////////////////////////////////////////////
297
// SVN tag: None
298
 
299 5 rehayes
Sept 10,2009
300
Added WISHBONE master bus submodule and some related top level signals but still
301
  not much real functionality.
302
 
303
Added code to allow for memory access stalls.
304
 
305
Upgraded testbench to insert memory wait states. Added more error detection
306
  and summery.
307
 
308
Improved instruction decoder. Still needs more work to remove redundant adders
309
  to improve synthesis results.
310
 
311 14 rehayes
////////////////////////////////////////////////////////////////////////////////
312
////////////////////////////////////////////////////////////////////////////////
313
// SVN tag: None
314 5 rehayes
 
315 2 rehayes
Sept 1, 2009
316
This is a prerelease checkin and should be looked at as an incremental backup
317
and not representative of what may be in the final release.
318
 
319
RTL - 75% done
320
What works:
321
  Basic instruction set execution simulated and verified. Condition code
322
  operation on instructions partially verified.
323
 
324
  Basic WISHBONE slave bus operation used, full functionality not verified.
325
 
326
What's broken or unimplemented:
327
  All things related to debug mode.
328
  WISHBONE master bus interface.
329
 
330 5 rehayes
User Documentation - 30% done
331
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.