| 1 |
2 |
rehayes |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
|
| 2 |
14 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
| 3 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 4 |
|
|
// SVN tag: None
|
| 5 |
|
|
|
| 6 |
38 |
rehayes |
Nov 09,2009
|
| 7 |
|
|
RTL - 85% done - Minor changes to Mastermode bus.
|
| 8 |
|
|
|
| 9 |
|
|
Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
|
| 10 |
|
|
but this is not fully functional. Causes timing problems when master is
|
| 11 |
|
|
polling xgate registers durning debug mode tests. Will probably change RAM
|
| 12 |
|
|
model to dual port in next revision.
|
| 13 |
|
|
Updated master module to include WISHBONE select inputs.
|
| 14 |
|
|
|
| 15 |
|
|
Updates to User Guide.
|
| 16 |
|
|
|
| 17 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 18 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 19 |
|
|
// SVN tag: None
|
| 20 |
|
|
|
| 21 |
23 |
rehayes |
Oct 07,2009
|
| 22 |
|
|
RTL - 85% done
|
| 23 |
|
|
All debug commands now working, including writes to XGCHID register.
|
| 24 |
|
|
|
| 25 |
|
|
Updates to testbench, added timeout and total error count.
|
| 26 |
|
|
Updates to User Guide.
|
| 27 |
|
|
Created the sw directory and copied over the software stuff from the bench
|
| 28 |
|
|
directory.
|
| 29 |
|
|
|
| 30 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 31 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 32 |
|
|
// SVN tag: None
|
| 33 |
|
|
|
| 34 |
14 |
rehayes |
Sept 23,2009
|
| 35 |
|
|
BRK instruction working. Single Step Command in debug mode working.
|
| 36 |
|
|
Software error interrupt added.
|
| 37 |
|
|
|
| 38 |
|
|
Updates to testbench.
|
| 39 |
|
|
New assembly code directory: debug_test
|
| 40 |
|
|
|
| 41 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 42 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 43 |
|
|
// SVN tag: None
|
| 44 |
|
|
|
| 45 |
5 |
rehayes |
Sept 10,2009
|
| 46 |
|
|
Added WISHBONE master bus submodule and some related top level signals but still
|
| 47 |
|
|
not much real functionality.
|
| 48 |
|
|
|
| 49 |
|
|
Added code to allow for memory access stalls.
|
| 50 |
|
|
|
| 51 |
|
|
Upgraded testbench to insert memory wait states. Added more error detection
|
| 52 |
|
|
and summery.
|
| 53 |
|
|
|
| 54 |
|
|
Improved instruction decoder. Still needs more work to remove redundant adders
|
| 55 |
|
|
to improve synthesis results.
|
| 56 |
|
|
|
| 57 |
14 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
| 58 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 59 |
|
|
// SVN tag: None
|
| 60 |
5 |
rehayes |
|
| 61 |
2 |
rehayes |
Sept 1, 2009
|
| 62 |
|
|
This is a prerelease checkin and should be looked at as an incremental backup
|
| 63 |
|
|
and not representative of what may be in the final release.
|
| 64 |
|
|
|
| 65 |
|
|
RTL - 75% done
|
| 66 |
|
|
What works:
|
| 67 |
|
|
Basic instruction set execution simulated and verified. Condition code
|
| 68 |
|
|
operation on instructions partially verified.
|
| 69 |
|
|
|
| 70 |
|
|
Basic WISHBONE slave bus operation used, full functionality not verified.
|
| 71 |
|
|
|
| 72 |
|
|
What's broken or unimplemented:
|
| 73 |
|
|
All things related to debug mode.
|
| 74 |
|
|
WISHBONE master bus interface.
|
| 75 |
|
|
|
| 76 |
5 |
rehayes |
User Documentation - 30% done
|
| 77 |
|
|
|
