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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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51 |
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Jan 11,2010
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RTL - 85% done -- Fix error in Zero Flag caculation for ADC and SBC instructions
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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THere is a bug in DEBUG mode that is sensitive to number of preceding
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instructions and wait states that needs to be resolved.
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Updates to testbench --
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Updates to User Guide -- First pass with instruction set details. Needs more
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review on condition code settings.
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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44 |
rehayes |
Dec 08,2009
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RTL - 85% done -- Updated code so there is only one program counter adder.
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Updated WISHBONE Slave bus for word addressability and byte selection.
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44 |
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Deleted two stack pointer registers.
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41 |
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Updates to testbench --
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Updates to User Guide -- Minor cleanup.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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Nov 09,2009
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RTL - 85% done - Minor changes to Mastermode bus.
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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but this is not fully functional. Causes timing problems when master is
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polling xgate registers durning debug mode tests. Will probably change RAM
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model to dual port in next revision.
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Updated master module to include WISHBONE select inputs.
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Updates to User Guide.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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rehayes |
Oct 07,2009
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RTL - 85% done
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All debug commands now working, including writes to XGCHID register.
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Updates to testbench, added timeout and total error count.
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41 |
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Updates to User Guide --.
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Created the sw directory and copied over the software stuff from the bench
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directory.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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rehayes |
Sept 23,2009
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BRK instruction working. Single Step Command in debug mode working.
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Software error interrupt added.
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Updates to testbench.
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New assembly code directory: debug_test
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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5 |
rehayes |
Sept 10,2009
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Added WISHBONE master bus submodule and some related top level signals but still
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not much real functionality.
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Added code to allow for memory access stalls.
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Upgraded testbench to insert memory wait states. Added more error detection
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and summery.
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Improved instruction decoder. Still needs more work to remove redundant adders
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to improve synthesis results.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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5 |
rehayes |
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2 |
rehayes |
Sept 1, 2009
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This is a prerelease checkin and should be looked at as an incremental backup
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and not representative of what may be in the final release.
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RTL - 75% done
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What works:
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Basic instruction set execution simulated and verified. Condition code
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operation on instructions partially verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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What's broken or unimplemented:
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All things related to debug mode.
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WISHBONE master bus interface.
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5 |
rehayes |
User Documentation - 30% done
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